From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56C83C4338F for ; Mon, 9 Aug 2021 03:09:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3F20160FD8 for ; Mon, 9 Aug 2021 03:09:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232889AbhHIDJU (ORCPT ); Sun, 8 Aug 2021 23:09:20 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:54262 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232791AbhHIDJF (ORCPT ); Sun, 8 Aug 2021 23:09:05 -0400 X-UUID: 6cb089efe0924ae48da6af0fe3f955b9-20210809 X-UUID: 6cb089efe0924ae48da6af0fe3f955b9-20210809 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1680718106; Mon, 09 Aug 2021 11:08:39 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 9 Aug 2021 11:08:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 9 Aug 2021 11:08:35 +0800 From: Nina Wu CC: Rob Herring , Matthias Brugger , Nina Wu , Neal Liu , Zhen Lei , , , , , , , Subject: [v4 2/7] soc: mediatek: devapc: get 'vio_idx_num' info from DT Date: Mon, 9 Aug 2021 11:08:14 +0800 Message-ID: <1628478499-29460-2-git-send-email-nina-cm.wu@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1628478499-29460-1-git-send-email-nina-cm.wu@mediatek.com> References: <1628478499-29460-1-git-send-email-nina-cm.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Nina Wu For new ICs, there are multiple devapc HWs for different subsys. The number of devices controlled by each devapc (i.e. 'vio_idx_num') will be set in DT for per devapc node. On the other hand, for old ICs which have only one devapc HW, the 'vio_idx_num' info is set in compatible data. To be backward compatible, the 'vio_idx_num' in compatible data is set as the default value. Only when the default value is 0 will we get the 'vio_idx_num' from DT. Signed-off-by: Nina Wu --- drivers/soc/mediatek/mtk-devapc.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c index 7c65ad3..86bddb2 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -32,7 +32,7 @@ struct mtk_devapc_vio_dbgs { }; struct mtk_devapc_data { - /* numbers of violation index */ + /* default numbers of violation index */ u32 vio_idx_num; /* reg offset */ @@ -51,6 +51,9 @@ struct mtk_devapc_context { void __iomem *infra_base; struct clk *infra_clk; const struct mtk_devapc_data *data; + + /* numbers of violation index */ + u32 vio_idx_num; }; static void clear_vio_status(struct mtk_devapc_context *ctx) @@ -60,10 +63,10 @@ static void clear_vio_status(struct mtk_devapc_context *ctx) reg = ctx->infra_base + ctx->data->vio_sta_offset; - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num) - 1; i++) writel(GENMASK(31, 0), reg + 4 * i); - writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0), + writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num) - 1, 0), reg + 4 * i); } @@ -80,15 +83,15 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask) else val = 0; - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num) - 1; i++) writel(val, reg + 4 * i); val = readl(reg + 4 * i); if (mask) - val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, + val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num) - 1, 0); else - val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, + val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num) - 1, 0); writel(val, reg + 4 * i); @@ -257,6 +260,16 @@ static int mtk_devapc_probe(struct platform_device *pdev) if (!ctx->infra_base) return -EINVAL; + /* Set vio_idx_num to default value. + * If the value is 0, get the info from DT. + */ + ctx->vio_idx_num = ctx->data->vio_idx_num; + if (!ctx->vio_idx_num) + if (of_property_read_u32(node, + "vio-idx-num", + &ctx->vio_idx_num)) + return -EINVAL; + devapc_irq = irq_of_parse_and_map(node, 0); if (!devapc_irq) return -EINVAL; -- 2.6.4