[v6 0/3] Add L3 provider support for SC7280

[v6 0/3] Add L3 provider support for SC7280

[Odelu Kukatla]

Add Epoch Subsystem (EPSS) L3 provider support on SM7280 SoCs.

v6:
 - Addressed review comments(v5) and added a chage missed in v5.
 
Depends on: https://lore.kernel.org/patchwork/patch/1466834/

Odelu Kukatla (3):
  dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
  interconnect: qcom: Add EPSS L3 support on SC7280
  arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

 .../bindings/interconnect/qcom,osm-l3.yaml         |   9 +-
 arch/arm64/boot/dts/qcom/sc7280.dtsi               |   9 ++
 drivers/interconnect/qcom/osm-l3.c                 | 136 +++++++++++++++++----
 drivers/interconnect/qcom/sc7280.h                 |  10 ++
 include/dt-bindings/interconnect/qcom,osm-l3.h     |  10 +-
 5 files changed, 151 insertions(+), 23 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

[Odelu Kukatla]

Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
 .../devicetree/bindings/interconnect/qcom,osm-l3.yaml          |  9 ++++++++-
 include/dt-bindings/interconnect/qcom,osm-l3.h                 | 10 +++++++++-
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index e701524..919fce4 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -18,13 +18,20 @@ properties:
   compatible:
     enum:
       - qcom,sc7180-osm-l3
+      - qcom,sc7280-epss-l3
       - qcom,sc8180x-osm-l3
       - qcom,sdm845-osm-l3
       - qcom,sm8150-osm-l3
       - qcom,sm8250-epss-l3
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 4
+    items:
+      - description: OSM clock domain-0 base address and size
+      - description: OSM clock domain-1 base address and size
+      - description: OSM clock domain-2 base address and size
+      - description: OSM clock domain-3 base address and size
 
   clocks:
     items:
diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h
index 61ef649..99534a5 100644
--- a/include/dt-bindings/interconnect/qcom,osm-l3.h
+++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2019 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved.
  */
 
 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
@@ -11,5 +11,13 @@
 
 #define MASTER_EPSS_L3_APPS	0
 #define SLAVE_EPSS_L3_SHARED	1
+#define SLAVE_EPSS_L3_CPU0	2
+#define SLAVE_EPSS_L3_CPU1	3
+#define SLAVE_EPSS_L3_CPU2	4
+#define SLAVE_EPSS_L3_CPU3	5
+#define SLAVE_EPSS_L3_CPU4	6
+#define SLAVE_EPSS_L3_CPU5	7
+#define SLAVE_EPSS_L3_CPU6	8
+#define SLAVE_EPSS_L3_CPU7	9
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[v6 2/3] interconnect: qcom: Add EPSS L3 support on SC7280

[Odelu Kukatla]

Add Epoch Subsystem (EPSS) L3 interconnect provider support on
SC7280 SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
 drivers/interconnect/qcom/osm-l3.c | 136 +++++++++++++++++++++++++++++++------
 drivers/interconnect/qcom/sc7280.h |  10 +++
 2 files changed, 125 insertions(+), 21 deletions(-)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index c7af143..3b16e73 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -9,12 +9,14 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
 
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 
 #include "sc7180.h"
+#include "sc7280.h"
 #include "sc8180x.h"
 #include "sdm845.h"
 #include "sm8150.h"
@@ -33,17 +35,33 @@
 
 /* EPSS Register offsets */
 #define EPSS_LUT_ROW_SIZE		4
+#define EPSS_REG_L3_VOTE		0x90
 #define EPSS_REG_FREQ_LUT		0x100
 #define EPSS_REG_PERF_STATE		0x320
+#define EPSS_CORE_OFFSET		0x4
+#define EPSS_L3_VOTE_REG(base, cpu)\
+			(((base) + EPSS_REG_L3_VOTE) +\
+			((cpu) * EPSS_CORE_OFFSET))
 
-#define OSM_L3_MAX_LINKS		1
+#define L3_DOMAIN_CNT		4
+#define L3_MAX_LINKS		9
 
 #define to_osm_l3_provider(_provider) \
 	container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
 
+/**
+ * @domain_base: an array of base address for each clock domain
+ * @max_state: max supported frequency level
+ * @per_core_dcvs: flag used to indicate whether the frequency scaling
+ * for each core is enabled
+ * @reg_perf_state: requested frequency level
+ * @lut_tables: an array of supported frequency levels
+ * @provider: interconnect provider of this node
+ */
 struct qcom_osm_l3_icc_provider {
-	void __iomem *base;
+	void __iomem *domain_base[L3_DOMAIN_CNT];
 	unsigned int max_state;
+	bool per_core_dcvs;
 	unsigned int reg_perf_state;
 	unsigned long lut_tables[LUT_MAX_ENTRIES];
 	struct icc_provider provider;
@@ -56,32 +74,44 @@ struct qcom_osm_l3_icc_provider {
  * @id: a unique node identifier
  * @num_links: the total number of @links
  * @buswidth: width of the interconnect between a node and the bus
+ * @domain: clock domain of the cpu node
+ * @cpu: cpu instance within its clock domain
  */
 struct qcom_osm_l3_node {
 	const char *name;
-	u16 links[OSM_L3_MAX_LINKS];
+	u16 links[L3_MAX_LINKS];
 	u16 id;
 	u16 num_links;
 	u16 buswidth;
+	u8 domain;
+	u8 cpu;
 };
 
 struct qcom_osm_l3_desc {
 	const struct qcom_osm_l3_node **nodes;
 	size_t num_nodes;
+	bool per_core_dcvs;
 	unsigned int lut_row_size;
 	unsigned int reg_freq_lut;
 	unsigned int reg_perf_state;
 };
 
-#define DEFINE_QNODE(_name, _id, _buswidth, ...)			\
+#define __DEFINE_QNODE(_name, _id, _buswidth, _domain, _cpu, ...)	\
 	static const struct qcom_osm_l3_node _name = {			\
 		.name = #_name,						\
 		.id = _id,						\
 		.buswidth = _buswidth,					\
+		.domain = _domain,					\
+		.cpu = _cpu,						\
 		.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),	\
 		.links = { __VA_ARGS__ },				\
 	}
 
+#define DEFINE_QNODE(_name, _id, _buswidth, ...)		\
+		__DEFINE_QNODE(_name, _id, _buswidth, 0, 0, __VA_ARGS__ )
+#define DEFINE_DCVS_QNODE(_name, _id, _buswidth, _domain, _cpu, ...)		\
+		__DEFINE_QNODE(_name, _id, _buswidth, _domain, _cpu, __VA_ARGS__ )
+
 DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
 DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
 
@@ -162,26 +192,80 @@ static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
 	.reg_perf_state = EPSS_REG_PERF_STATE,
 };
 
+DEFINE_DCVS_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, 0, 0,
+					SC7280_SLAVE_EPSS_L3_SHARED, SC7280_SLAVE_EPSS_L3_CPU0,
+					SC7280_SLAVE_EPSS_L3_CPU1, SC7280_SLAVE_EPSS_L3_CPU2,
+					SC7280_SLAVE_EPSS_L3_CPU3, SC7280_SLAVE_EPSS_L3_CPU4,
+					SC7280_SLAVE_EPSS_L3_CPU5, SC7280_SLAVE_EPSS_L3_CPU6,
+					SC7280_SLAVE_EPSS_L3_CPU7);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_shared, SC7280_SLAVE_EPSS_L3_SHARED, 32, 0, 0);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu0, SC7280_SLAVE_EPSS_L3_CPU0, 32, 1, 0);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu1, SC7280_SLAVE_EPSS_L3_CPU1, 32, 1, 1);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu2, SC7280_SLAVE_EPSS_L3_CPU2, 32, 1, 2);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu3, SC7280_SLAVE_EPSS_L3_CPU3, 32, 1, 3);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu4, SC7280_SLAVE_EPSS_L3_CPU4, 32, 2, 0);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu5, SC7280_SLAVE_EPSS_L3_CPU5, 32, 2, 1);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu6, SC7280_SLAVE_EPSS_L3_CPU6, 32, 2, 2);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu7, SC7280_SLAVE_EPSS_L3_CPU7, 32, 3, 0);
+
+static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {
+	[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
+	[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3_shared,
+	[SLAVE_EPSS_L3_CPU0] = &sc7280_epss_l3_cpu0,
+	[SLAVE_EPSS_L3_CPU1] = &sc7280_epss_l3_cpu1,
+	[SLAVE_EPSS_L3_CPU2] = &sc7280_epss_l3_cpu2,
+	[SLAVE_EPSS_L3_CPU3] = &sc7280_epss_l3_cpu3,
+	[SLAVE_EPSS_L3_CPU4] = &sc7280_epss_l3_cpu4,
+	[SLAVE_EPSS_L3_CPU5] = &sc7280_epss_l3_cpu5,
+	[SLAVE_EPSS_L3_CPU6] = &sc7280_epss_l3_cpu6,
+	[SLAVE_EPSS_L3_CPU7] = &sc7280_epss_l3_cpu7,
+};
+
+static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
+	.nodes = sc7280_epss_l3_nodes,
+	.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
+	.per_core_dcvs = true,
+	.lut_row_size = EPSS_LUT_ROW_SIZE,
+	.reg_freq_lut = EPSS_REG_FREQ_LUT,
+	.reg_perf_state = EPSS_REG_PERF_STATE,
+};
+
+static u32 qcom_osm_l3_aggregate_peak(struct icc_node *src, struct icc_node *dst)
+{
+	struct icc_node *n;
+	u32 agg_peak = 0;
+	u32 agg_avg = 0;
+	struct qcom_osm_l3_icc_provider *qp;
+	struct icc_provider *provider;
+
+	provider = src->provider;
+	qp = to_osm_l3_provider(provider);
+
+	/* Skip aggregation when per core l3 scaling is enabled */
+	if (qp->per_core_dcvs)
+		return dst->peak_bw;
+
+	list_for_each_entry(n, &provider->nodes, node_list)
+		provider->aggregate(n, 0, n->avg_bw, n->peak_bw, &agg_avg, &agg_peak);
+
+	agg_peak = max(agg_avg, agg_peak);
+
+	return agg_peak;
+}
+
 static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 {
 	struct qcom_osm_l3_icc_provider *qp;
 	struct icc_provider *provider;
 	const struct qcom_osm_l3_node *qn;
-	struct icc_node *n;
 	unsigned int index;
-	u32 agg_peak = 0;
-	u32 agg_avg = 0;
 	u64 rate;
 
-	qn = src->data;
+	qn = dst->data;
 	provider = src->provider;
 	qp = to_osm_l3_provider(provider);
 
-	list_for_each_entry(n, &provider->nodes, node_list)
-		provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
-				    &agg_avg, &agg_peak);
-
-	rate = max(agg_avg, agg_peak);
+	rate = qcom_osm_l3_aggregate_peak(src, dst);
 	rate = icc_units_to_bps(rate);
 	do_div(rate, qn->buswidth);
 
@@ -190,7 +274,10 @@ static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 			break;
 	}
 
-	writel_relaxed(index, qp->base + qp->reg_perf_state);
+	if (qp->per_core_dcvs)
+		writel_relaxed(index, EPSS_L3_VOTE_REG(qp->domain_base[qn->domain], qn->cpu));
+	else
+		writel_relaxed(index, qp->domain_base[qn->domain] + qp->reg_perf_state);
 
 	return 0;
 }
@@ -205,7 +292,7 @@ static int qcom_osm_l3_remove(struct platform_device *pdev)
 
 static int qcom_osm_l3_probe(struct platform_device *pdev)
 {
-	u32 info, src, lval, i, prev_freq = 0, freq;
+	u32 info, src, lval, i = 0, prev_freq = 0, freq;
 	static unsigned long hw_rate, xo_rate;
 	struct qcom_osm_l3_icc_provider *qp;
 	const struct qcom_osm_l3_desc *desc;
@@ -215,7 +302,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 	struct icc_node *node;
 	size_t num_nodes;
 	struct clk *clk;
-	int ret;
+	int ret, nr_domain_bases = 0;
 
 	clk = clk_get(&pdev->dev, "xo");
 	if (IS_ERR(clk))
@@ -235,12 +322,17 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 	if (!qp)
 		return -ENOMEM;
 
-	qp->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(qp->base))
-		return PTR_ERR(qp->base);
+	while (of_get_address(pdev->dev.of_node, i++, NULL, NULL))
+		nr_domain_bases++;
+
+	for (i = 0; i < nr_domain_bases ; i++) {
+		qp->domain_base[i] = devm_platform_ioremap_resource(pdev, i);
+		if (IS_ERR(qp->domain_base[i]))
+			return PTR_ERR(qp->domain_base[i]);
+	}
 
 	/* HW should be in enabled state to proceed */
-	if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
+	if (!(readl_relaxed(qp->domain_base[0] + REG_ENABLE) & 0x1)) {
 		dev_err(&pdev->dev, "error hardware not enabled\n");
 		return -ENODEV;
 	}
@@ -252,7 +344,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 	qp->reg_perf_state = desc->reg_perf_state;
 
 	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
-		info = readl_relaxed(qp->base + desc->reg_freq_lut +
+		info = readl_relaxed(qp->domain_base[0] + desc->reg_freq_lut +
 				     i * desc->lut_row_size);
 		src = FIELD_GET(LUT_SRC, info);
 		lval = FIELD_GET(LUT_L_VAL, info);
@@ -271,6 +363,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 		prev_freq = freq;
 	}
 	qp->max_state = i;
+	qp->per_core_dcvs = desc->per_core_dcvs;
 
 	qnodes = desc->nodes;
 	num_nodes = desc->num_nodes;
@@ -326,6 +419,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 
 static const struct of_device_id osm_l3_of_match[] = {
 	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
+	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
 	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
 	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
 	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h
index 175e400..5df7600 100644
--- a/drivers/interconnect/qcom/sc7280.h
+++ b/drivers/interconnect/qcom/sc7280.h
@@ -150,5 +150,15 @@
 #define SC7280_SLAVE_PCIE_1			139
 #define SC7280_SLAVE_QDSS_STM			140
 #define SC7280_SLAVE_TCU			141
+#define SC7280_MASTER_EPSS_L3_APPS			142
+#define SC7280_SLAVE_EPSS_L3_SHARED			143
+#define SC7280_SLAVE_EPSS_L3_CPU0			144
+#define SC7280_SLAVE_EPSS_L3_CPU1			145
+#define SC7280_SLAVE_EPSS_L3_CPU2			146
+#define SC7280_SLAVE_EPSS_L3_CPU3			147
+#define SC7280_SLAVE_EPSS_L3_CPU4			148
+#define SC7280_SLAVE_EPSS_L3_CPU5			149
+#define SC7280_SLAVE_EPSS_L3_CPU6			150
+#define SC7280_SLAVE_EPSS_L3_CPU7			151
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[Odelu Kukatla]

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d0..e78f055 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -586,6 +586,15 @@
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc7280-epss-l3";
+			reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
+				<0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			#interconnect-cells = <1>;
+		};
+
 		ipa: ipa@1e40000 {
 			compatible = "qcom,sc7280-ipa";
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [v6 2/3] interconnect: qcom: Add EPSS L3 support on SC7280

[Georgi Djakov]

Hi Odelu,

On 10.08.21 9:46, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider support on
> SC7280 SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>   drivers/interconnect/qcom/osm-l3.c | 136 +++++++++++++++++++++++++++++++------
>   drivers/interconnect/qcom/sc7280.h |  10 +++
>   2 files changed, 125 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index c7af143..3b16e73 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -9,12 +9,14 @@
>   #include <linux/io.h>
>   #include <linux/kernel.h>
>   #include <linux/module.h>
> +#include <linux/of_address.h>
>   #include <linux/of_device.h>
>   #include <linux/platform_device.h>
>   
>   #include <dt-bindings/interconnect/qcom,osm-l3.h>
>   
>   #include "sc7180.h"
> +#include "sc7280.h"
>   #include "sc8180x.h"
>   #include "sdm845.h"
>   #include "sm8150.h"
> @@ -33,17 +35,33 @@
>   
>   /* EPSS Register offsets */
>   #define EPSS_LUT_ROW_SIZE		4
> +#define EPSS_REG_L3_VOTE		0x90
>   #define EPSS_REG_FREQ_LUT		0x100
>   #define EPSS_REG_PERF_STATE		0x320
> +#define EPSS_CORE_OFFSET		0x4
> +#define EPSS_L3_VOTE_REG(base, cpu)\
> +			(((base) + EPSS_REG_L3_VOTE) +\
> +			((cpu) * EPSS_CORE_OFFSET))
>   
> -#define OSM_L3_MAX_LINKS		1
> +#define L3_DOMAIN_CNT		4
> +#define L3_MAX_LINKS		9
>   
>   #define to_osm_l3_provider(_provider) \
>   	container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
>   
> +/**
> + * @domain_base: an array of base address for each clock domain

This is not a valid kerneldoc. Please add a title for
	struct qcom_osm_l3_icc_provider

> + * @max_state: max supported frequency level
> + * @per_core_dcvs: flag used to indicate whether the frequency scaling
> + * for each core is enabled
> + * @reg_perf_state: requested frequency level
> + * @lut_tables: an array of supported frequency levels
> + * @provider: interconnect provider of this node
> + */
>   struct qcom_osm_l3_icc_provider {
> -	void __iomem *base;
> +	void __iomem *domain_base[L3_DOMAIN_CNT];
>   	unsigned int max_state;
> +	bool per_core_dcvs;
>   	unsigned int reg_perf_state;
>   	unsigned long lut_tables[LUT_MAX_ENTRIES];
>   	struct icc_provider provider;
> @@ -56,32 +74,44 @@ struct qcom_osm_l3_icc_provider {
>    * @id: a unique node identifier
>    * @num_links: the total number of @links
>    * @buswidth: width of the interconnect between a node and the bus
> + * @domain: clock domain of the cpu node
> + * @cpu: cpu instance within its clock domain
>    */
>   struct qcom_osm_l3_node {
>   	const char *name;
> -	u16 links[OSM_L3_MAX_LINKS];
> +	u16 links[L3_MAX_LINKS];
>   	u16 id;
>   	u16 num_links;
>   	u16 buswidth;
> +	u8 domain;
> +	u8 cpu;
>   };
>   
>   struct qcom_osm_l3_desc {
>   	const struct qcom_osm_l3_node **nodes;
>   	size_t num_nodes;
> +	bool per_core_dcvs;
>   	unsigned int lut_row_size;
>   	unsigned int reg_freq_lut;
>   	unsigned int reg_perf_state;
>   };
>   
> -#define DEFINE_QNODE(_name, _id, _buswidth, ...)			\
> +#define __DEFINE_QNODE(_name, _id, _buswidth, _domain, _cpu, ...)	\
>   	static const struct qcom_osm_l3_node _name = {			\
>   		.name = #_name,						\
>   		.id = _id,						\
>   		.buswidth = _buswidth,					\
> +		.domain = _domain,					\
> +		.cpu = _cpu,						\
>   		.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),	\
>   		.links = { __VA_ARGS__ },				\
>   	}
>   
> +#define DEFINE_QNODE(_name, _id, _buswidth, ...)		\
> +		__DEFINE_QNODE(_name, _id, _buswidth, 0, 0, __VA_ARGS__ )

Nit: No space before the close parenthesis please.

> +#define DEFINE_DCVS_QNODE(_name, _id, _buswidth, _domain, _cpu, ...)		\
> +		__DEFINE_QNODE(_name, _id, _buswidth, _domain, _cpu, __VA_ARGS__ )

Ditto

> +
>   DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
>   DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
>   
> @@ -162,26 +192,80 @@ static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
>   	.reg_perf_state = EPSS_REG_PERF_STATE,
>   };
>   
> +DEFINE_DCVS_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, 0, 0,
> +					SC7280_SLAVE_EPSS_L3_SHARED, SC7280_SLAVE_EPSS_L3_CPU0,
> +					SC7280_SLAVE_EPSS_L3_CPU1, SC7280_SLAVE_EPSS_L3_CPU2,
> +					SC7280_SLAVE_EPSS_L3_CPU3, SC7280_SLAVE_EPSS_L3_CPU4,
> +					SC7280_SLAVE_EPSS_L3_CPU5, SC7280_SLAVE_EPSS_L3_CPU6,
> +					SC7280_SLAVE_EPSS_L3_CPU7);

Nit: Please align these to the open parenthesis.

Thanks,
Georgi

Re: [v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[Georgi Djakov]

Hi Odelu,

On 10.08.21 9:46, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..e78f055 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -586,6 +586,15 @@
>   			qcom,bcm-voters = <&apps_bcm_voter>;
>   		};
>   
> +		epss_l3: interconnect@18590000 {

This DT node should be moved after apps_rsc: rsc@18200000
and before cpufreq@18591000

> +			compatible = "qcom,sc7280-epss-l3";
> +			reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
> +				<0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;

Please align to the open parenthesis, to be consistent with the rest of
the file.

> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +			#interconnect-cells = <1>;
> +		};
> +
>   		ipa: ipa@1e40000 {
>   			compatible = "qcom,sc7280-ipa";

Thanks,
Georgi

Re: [v6 2/3] interconnect: qcom: Add EPSS L3 support on SC7280

[Alex Elder]

On 8/10/21 1:46 AM, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider support on
> SC7280 SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>

I don't have much to say about what this is doing but I
have a few suggestions.

					-Alex

> ---
>   drivers/interconnect/qcom/osm-l3.c | 136 +++++++++++++++++++++++++++++++------
>   drivers/interconnect/qcom/sc7280.h |  10 +++
>   2 files changed, 125 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index c7af143..3b16e73 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -9,12 +9,14 @@
>   #include <linux/io.h>
>   #include <linux/kernel.h>
>   #include <linux/module.h>
> +#include <linux/of_address.h>
>   #include <linux/of_device.h>
>   #include <linux/platform_device.h>
>   
>   #include <dt-bindings/interconnect/qcom,osm-l3.h>
>   
>   #include "sc7180.h"
> +#include "sc7280.h"
>   #include "sc8180x.h"
>   #include "sdm845.h"
>   #include "sm8150.h"
> @@ -33,17 +35,33 @@
>   
>   /* EPSS Register offsets */
>   #define EPSS_LUT_ROW_SIZE		4
> +#define EPSS_REG_L3_VOTE		0x90
>   #define EPSS_REG_FREQ_LUT		0x100
>   #define EPSS_REG_PERF_STATE		0x320
> +#define EPSS_CORE_OFFSET		0x4
> +#define EPSS_L3_VOTE_REG(base, cpu)\
> +			(((base) + EPSS_REG_L3_VOTE) +\
> +			((cpu) * EPSS_CORE_OFFSET))
>   
> -#define OSM_L3_MAX_LINKS		1
> +#define L3_DOMAIN_CNT		4
> +#define L3_MAX_LINKS		9

It may not matter much, but if you specified the
qcom_osm_l3_node->links[] field as the last field
in the structure, I think it could be a flexible
array and you wouldn't have to specify the maximum
number of links.  (You are already using the actual
array size to set ->num_links in __DEFINE_QNODE().)

>   #define to_osm_l3_provider(_provider) \
>   	container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
>   
> +/**
> + * @domain_base: an array of base address for each clock domain
> + * @max_state: max supported frequency level
> + * @per_core_dcvs: flag used to indicate whether the frequency scaling
> + * for each core is enabled
> + * @reg_perf_state: requested frequency level
> + * @lut_tables: an array of supported frequency levels
> + * @provider: interconnect provider of this node
> + */

Run this to check your kernel doc validity:
     scripts/kernel-doc -none <file> [<file>...]

>   struct qcom_osm_l3_icc_provider {
> -	void __iomem *base;
> +	void __iomem *domain_base[L3_DOMAIN_CNT];
>   	unsigned int max_state;
> +	bool per_core_dcvs;
>   	unsigned int reg_perf_state;
>   	unsigned long lut_tables[LUT_MAX_ENTRIES];
>   	struct icc_provider provider;

. . .

> @@ -235,12 +322,17 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
>   	if (!qp)
>   		return -ENOMEM;
>   
> -	qp->base = devm_platform_ioremap_resource(pdev, 0);
> -	if (IS_ERR(qp->base))
> -		return PTR_ERR(qp->base);
> +	while (of_get_address(pdev->dev.of_node, i++, NULL, NULL))
> +		nr_domain_bases++;

Maybe you could combine these two loops by counting as you go.
I.e.:

     i = 0;
     while (true) {
	void __iomem *base;

	if (of_get_address(pdev->dev.of_node, i, NULL, NULL))
		break;
	base = devm_platform_ioremap_resource(pdev, i);
	if (IS_ERR(base))
	    return PTR_ERR(base);
	qp->domain_base[i++] = base
     }
     nr_domain_bases = i;

> +
> +	for (i = 0; i < nr_domain_bases ; i++) {
> +		qp->domain_base[i] = devm_platform_ioremap_resource(pdev, i);
> +		if (IS_ERR(qp->domain_base[i]))
> +			return PTR_ERR(qp->domain_base[i]);
> +	}
>   
>   	/* HW should be in enabled state to proceed */
> -	if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
> +	if (!(readl_relaxed(qp->domain_base[0] + REG_ENABLE) & 0x1)) {
>   		dev_err(&pdev->dev, "error hardware not enabled\n");
>   		return -ENODEV;
>   	}
> @@ -252,7 +344,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
>   	qp->reg_perf_state = desc->reg_perf_state;
>   
>   	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
> -		info = readl_relaxed(qp->base + desc->reg_freq_lut +
> +		info = readl_relaxed(qp->domain_base[0] + desc->reg_freq_lut +
>   				     i * desc->lut_row_size);

Maybe you could define a macro to encapsulate computing this
register offset, along the lines of EPSS_L3_VOTE_REG().  (Here
and elsewhere.)

>   		src = FIELD_GET(LUT_SRC, info);
>   		lval = FIELD_GET(LUT_L_VAL, info);
> @@ -271,6 +363,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
>   		prev_freq = freq;
>   	}
>   	qp->max_state = i;
> +	qp->per_core_dcvs = desc->per_core_dcvs;
>   
>   	qnodes = desc->nodes;
>   	num_nodes = desc->num_nodes;
> @@ -326,6 +419,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
>   
>   static const struct of_device_id osm_l3_of_match[] = {
>   	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
> +	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
>   	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
>   	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
>   	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
> diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h
> index 175e400..5df7600 100644
> --- a/drivers/interconnect/qcom/sc7280.h
> +++ b/drivers/interconnect/qcom/sc7280.h
> @@ -150,5 +150,15 @@
>   #define SC7280_SLAVE_PCIE_1			139
>   #define SC7280_SLAVE_QDSS_STM			140
>   #define SC7280_SLAVE_TCU			141
> +#define SC7280_MASTER_EPSS_L3_APPS			142
> +#define SC7280_SLAVE_EPSS_L3_SHARED			143
> +#define SC7280_SLAVE_EPSS_L3_CPU0			144
> +#define SC7280_SLAVE_EPSS_L3_CPU1			145
> +#define SC7280_SLAVE_EPSS_L3_CPU2			146
> +#define SC7280_SLAVE_EPSS_L3_CPU3			147
> +#define SC7280_SLAVE_EPSS_L3_CPU4			148
> +#define SC7280_SLAVE_EPSS_L3_CPU5			149
> +#define SC7280_SLAVE_EPSS_L3_CPU6			150
> +#define SC7280_SLAVE_EPSS_L3_CPU7			151
>   
>   #endif
> 

Re: [v6 2/3] interconnect: qcom: Add EPSS L3 support on SC7280

[okukatla]

On 2021-08-10 17:28, Georgi Djakov wrote:
> Hi Odelu,
> 
> On 10.08.21 9:46, Odelu Kukatla wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider support on
>> SC7280 SoCs.
>> 
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>>   drivers/interconnect/qcom/osm-l3.c | 136 
>> +++++++++++++++++++++++++++++++------
>>   drivers/interconnect/qcom/sc7280.h |  10 +++
>>   2 files changed, 125 insertions(+), 21 deletions(-)
>> 
>> diff --git a/drivers/interconnect/qcom/osm-l3.c 
>> b/drivers/interconnect/qcom/osm-l3.c
>> index c7af143..3b16e73 100644
>> --- a/drivers/interconnect/qcom/osm-l3.c
>> +++ b/drivers/interconnect/qcom/osm-l3.c
>> @@ -9,12 +9,14 @@
>>   #include <linux/io.h>
>>   #include <linux/kernel.h>
>>   #include <linux/module.h>
>> +#include <linux/of_address.h>
>>   #include <linux/of_device.h>
>>   #include <linux/platform_device.h>
>>     #include <dt-bindings/interconnect/qcom,osm-l3.h>
>>     #include "sc7180.h"
>> +#include "sc7280.h"
>>   #include "sc8180x.h"
>>   #include "sdm845.h"
>>   #include "sm8150.h"
>> @@ -33,17 +35,33 @@
>>     /* EPSS Register offsets */
>>   #define EPSS_LUT_ROW_SIZE		4
>> +#define EPSS_REG_L3_VOTE		0x90
>>   #define EPSS_REG_FREQ_LUT		0x100
>>   #define EPSS_REG_PERF_STATE		0x320
>> +#define EPSS_CORE_OFFSET		0x4
>> +#define EPSS_L3_VOTE_REG(base, cpu)\
>> +			(((base) + EPSS_REG_L3_VOTE) +\
>> +			((cpu) * EPSS_CORE_OFFSET))
>>   -#define OSM_L3_MAX_LINKS		1
>> +#define L3_DOMAIN_CNT		4
>> +#define L3_MAX_LINKS		9
>>     #define to_osm_l3_provider(_provider) \
>>   	container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
>>   +/**
>> + * @domain_base: an array of base address for each clock domain
> 
> This is not a valid kerneldoc. Please add a title for
> 	struct qcom_osm_l3_icc_provider
> 
Thanks for review! will address this in next revision.
>> + * @max_state: max supported frequency level
>> + * @per_core_dcvs: flag used to indicate whether the frequency 
>> scaling
>> + * for each core is enabled
>> + * @reg_perf_state: requested frequency level
>> + * @lut_tables: an array of supported frequency levels
>> + * @provider: interconnect provider of this node
>> + */
>>   struct qcom_osm_l3_icc_provider {
>> -	void __iomem *base;
>> +	void __iomem *domain_base[L3_DOMAIN_CNT];
>>   	unsigned int max_state;
>> +	bool per_core_dcvs;
>>   	unsigned int reg_perf_state;
>>   	unsigned long lut_tables[LUT_MAX_ENTRIES];
>>   	struct icc_provider provider;
>> @@ -56,32 +74,44 @@ struct qcom_osm_l3_icc_provider {
>>    * @id: a unique node identifier
>>    * @num_links: the total number of @links
>>    * @buswidth: width of the interconnect between a node and the bus
>> + * @domain: clock domain of the cpu node
>> + * @cpu: cpu instance within its clock domain
>>    */
>>   struct qcom_osm_l3_node {
>>   	const char *name;
>> -	u16 links[OSM_L3_MAX_LINKS];
>> +	u16 links[L3_MAX_LINKS];
>>   	u16 id;
>>   	u16 num_links;
>>   	u16 buswidth;
>> +	u8 domain;
>> +	u8 cpu;
>>   };
>>     struct qcom_osm_l3_desc {
>>   	const struct qcom_osm_l3_node **nodes;
>>   	size_t num_nodes;
>> +	bool per_core_dcvs;
>>   	unsigned int lut_row_size;
>>   	unsigned int reg_freq_lut;
>>   	unsigned int reg_perf_state;
>>   };
>>   -#define DEFINE_QNODE(_name, _id, _buswidth, ...)			\
>> +#define __DEFINE_QNODE(_name, _id, _buswidth, _domain, _cpu, ...)	\
>>   	static const struct qcom_osm_l3_node _name = {			\
>>   		.name = #_name,						\
>>   		.id = _id,						\
>>   		.buswidth = _buswidth,					\
>> +		.domain = _domain,					\
>> +		.cpu = _cpu,						\
>>   		.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),	\
>>   		.links = { __VA_ARGS__ },				\
>>   	}
>>   +#define DEFINE_QNODE(_name, _id, _buswidth, ...)		\
>> +		__DEFINE_QNODE(_name, _id, _buswidth, 0, 0, __VA_ARGS__ )
> 
> Nit: No space before the close parenthesis please.
> 
Thanks for review! will address this in next revision.
>> +#define DEFINE_DCVS_QNODE(_name, _id, _buswidth, _domain, _cpu, 
>> ...)		\
>> +		__DEFINE_QNODE(_name, _id, _buswidth, _domain, _cpu, __VA_ARGS__ )
> 
> Ditto
> 
>> +
>>   DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, 
>> SDM845_SLAVE_OSM_L3);
>>   DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
>>   @@ -162,26 +192,80 @@ static const struct qcom_osm_l3_desc 
>> sm8250_icc_epss_l3 = {
>>   	.reg_perf_state = EPSS_REG_PERF_STATE,
>>   };
>>   +DEFINE_DCVS_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 
>> 32, 0, 0,
>> +					SC7280_SLAVE_EPSS_L3_SHARED, SC7280_SLAVE_EPSS_L3_CPU0,
>> +					SC7280_SLAVE_EPSS_L3_CPU1, SC7280_SLAVE_EPSS_L3_CPU2,
>> +					SC7280_SLAVE_EPSS_L3_CPU3, SC7280_SLAVE_EPSS_L3_CPU4,
>> +					SC7280_SLAVE_EPSS_L3_CPU5, SC7280_SLAVE_EPSS_L3_CPU6,
>> +					SC7280_SLAVE_EPSS_L3_CPU7);
> 
> Nit: Please align these to the open parenthesis.
> 
Thanks for review! will address this in next revision.
> Thanks,
> Georgi

Re: [v6 2/3] interconnect: qcom: Add EPSS L3 support on SC7280

[okukatla]

On 2021-08-10 18:16, Alex Elder wrote:
> On 8/10/21 1:46 AM, Odelu Kukatla wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider support on
>> SC7280 SoCs.
>> 
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> 
> I don't have much to say about what this is doing but I
> have a few suggestions.
> 
> 					-Alex
> 
Thanks for review Alex!
>> ---
>>   drivers/interconnect/qcom/osm-l3.c | 136 
>> +++++++++++++++++++++++++++++++------
>>   drivers/interconnect/qcom/sc7280.h |  10 +++
>>   2 files changed, 125 insertions(+), 21 deletions(-)
>> 
>> diff --git a/drivers/interconnect/qcom/osm-l3.c 
>> b/drivers/interconnect/qcom/osm-l3.c
>> index c7af143..3b16e73 100644
>> --- a/drivers/interconnect/qcom/osm-l3.c
>> +++ b/drivers/interconnect/qcom/osm-l3.c
>> @@ -9,12 +9,14 @@
>>   #include <linux/io.h>
>>   #include <linux/kernel.h>
>>   #include <linux/module.h>
>> +#include <linux/of_address.h>
>>   #include <linux/of_device.h>
>>   #include <linux/platform_device.h>
>>     #include <dt-bindings/interconnect/qcom,osm-l3.h>
>>     #include "sc7180.h"
>> +#include "sc7280.h"
>>   #include "sc8180x.h"
>>   #include "sdm845.h"
>>   #include "sm8150.h"
>> @@ -33,17 +35,33 @@
>>     /* EPSS Register offsets */
>>   #define EPSS_LUT_ROW_SIZE		4
>> +#define EPSS_REG_L3_VOTE		0x90
>>   #define EPSS_REG_FREQ_LUT		0x100
>>   #define EPSS_REG_PERF_STATE		0x320
>> +#define EPSS_CORE_OFFSET		0x4
>> +#define EPSS_L3_VOTE_REG(base, cpu)\
>> +			(((base) + EPSS_REG_L3_VOTE) +\
>> +			((cpu) * EPSS_CORE_OFFSET))
>>   -#define OSM_L3_MAX_LINKS		1
>> +#define L3_DOMAIN_CNT		4
>> +#define L3_MAX_LINKS		9
> 
> It may not matter much, but if you specified the
> qcom_osm_l3_node->links[] field as the last field
> in the structure, I think it could be a flexible
> array and you wouldn't have to specify the maximum
> number of links.  (You are already using the actual
> array size to set ->num_links in __DEFINE_QNODE().)
> 
I will address this in next revision, will see if we can move it to 
flexible array.
>>   #define to_osm_l3_provider(_provider) \
>>   	container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
>>   +/**
>> + * @domain_base: an array of base address for each clock domain
>> + * @max_state: max supported frequency level
>> + * @per_core_dcvs: flag used to indicate whether the frequency 
>> scaling
>> + * for each core is enabled
>> + * @reg_perf_state: requested frequency level
>> + * @lut_tables: an array of supported frequency levels
>> + * @provider: interconnect provider of this node
>> + */
> 
> Run this to check your kernel doc validity:
>     scripts/kernel-doc -none <file> [<file>...]
> 
Done!
>>   struct qcom_osm_l3_icc_provider {
>> -	void __iomem *base;
>> +	void __iomem *domain_base[L3_DOMAIN_CNT];
>>   	unsigned int max_state;
>> +	bool per_core_dcvs;
>>   	unsigned int reg_perf_state;
>>   	unsigned long lut_tables[LUT_MAX_ENTRIES];
>>   	struct icc_provider provider;
> 
> . . .
> 
>> @@ -235,12 +322,17 @@ static int qcom_osm_l3_probe(struct 
>> platform_device *pdev)
>>   	if (!qp)
>>   		return -ENOMEM;
>>   -	qp->base = devm_platform_ioremap_resource(pdev, 0);
>> -	if (IS_ERR(qp->base))
>> -		return PTR_ERR(qp->base);
>> +	while (of_get_address(pdev->dev.of_node, i++, NULL, NULL))
>> +		nr_domain_bases++;
> 
> Maybe you could combine these two loops by counting as you go.
> I.e.:
> 
>     i = 0;
>     while (true) {
> 	void __iomem *base;
> 
> 	if (of_get_address(pdev->dev.of_node, i, NULL, NULL))
> 		break;
> 	base = devm_platform_ioremap_resource(pdev, i);
> 	if (IS_ERR(base))
> 	    return PTR_ERR(base);
> 	qp->domain_base[i++] = base
>     }
>     nr_domain_bases = i;
> 
Not exactly as above, but will merge these two loops.
>> +
>> +	for (i = 0; i < nr_domain_bases ; i++) {
>> +		qp->domain_base[i] = devm_platform_ioremap_resource(pdev, i);
>> +		if (IS_ERR(qp->domain_base[i]))
>> +			return PTR_ERR(qp->domain_base[i]);
>> +	}
>>     	/* HW should be in enabled state to proceed */
>> -	if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
>> +	if (!(readl_relaxed(qp->domain_base[0] + REG_ENABLE) & 0x1)) {
>>   		dev_err(&pdev->dev, "error hardware not enabled\n");
>>   		return -ENODEV;
>>   	}
>> @@ -252,7 +344,7 @@ static int qcom_osm_l3_probe(struct 
>> platform_device *pdev)
>>   	qp->reg_perf_state = desc->reg_perf_state;
>>     	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
>> -		info = readl_relaxed(qp->base + desc->reg_freq_lut +
>> +		info = readl_relaxed(qp->domain_base[0] + desc->reg_freq_lut +
>>   				     i * desc->lut_row_size);
> 
> Maybe you could define a macro to encapsulate computing this
> register offset, along the lines of EPSS_L3_VOTE_REG().  (Here
> and elsewhere.)
> 
This register OFFSET calculation is here only, will keep this code as 
is.
>>   		src = FIELD_GET(LUT_SRC, info);
>>   		lval = FIELD_GET(LUT_L_VAL, info);
>> @@ -271,6 +363,7 @@ static int qcom_osm_l3_probe(struct 
>> platform_device *pdev)
>>   		prev_freq = freq;
>>   	}
>>   	qp->max_state = i;
>> +	qp->per_core_dcvs = desc->per_core_dcvs;
>>     	qnodes = desc->nodes;
>>   	num_nodes = desc->num_nodes;
>> @@ -326,6 +419,7 @@ static int qcom_osm_l3_probe(struct 
>> platform_device *pdev)
>>     static const struct of_device_id osm_l3_of_match[] = {
>>   	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
>> +	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 
>> },
>>   	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
>>   	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
>>   	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 
>> },
>> diff --git a/drivers/interconnect/qcom/sc7280.h 
>> b/drivers/interconnect/qcom/sc7280.h
>> index 175e400..5df7600 100644
>> --- a/drivers/interconnect/qcom/sc7280.h
>> +++ b/drivers/interconnect/qcom/sc7280.h
>> @@ -150,5 +150,15 @@
>>   #define SC7280_SLAVE_PCIE_1			139
>>   #define SC7280_SLAVE_QDSS_STM			140
>>   #define SC7280_SLAVE_TCU			141
>> +#define SC7280_MASTER_EPSS_L3_APPS			142
>> +#define SC7280_SLAVE_EPSS_L3_SHARED			143
>> +#define SC7280_SLAVE_EPSS_L3_CPU0			144
>> +#define SC7280_SLAVE_EPSS_L3_CPU1			145
>> +#define SC7280_SLAVE_EPSS_L3_CPU2			146
>> +#define SC7280_SLAVE_EPSS_L3_CPU3			147
>> +#define SC7280_SLAVE_EPSS_L3_CPU4			148
>> +#define SC7280_SLAVE_EPSS_L3_CPU5			149
>> +#define SC7280_SLAVE_EPSS_L3_CPU6			150
>> +#define SC7280_SLAVE_EPSS_L3_CPU7			151
>>     #endif
>> 

Re: [v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[okukatla]

On 2021-08-10 18:03, Georgi Djakov wrote:
> Hi Odelu,
> 
> On 10.08.21 9:46, Odelu Kukatla wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>> 
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 53a21d0..e78f055 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -586,6 +586,15 @@
>>   			qcom,bcm-voters = <&apps_bcm_voter>;
>>   		};
>>   +		epss_l3: interconnect@18590000 {
> 
> This DT node should be moved after apps_rsc: rsc@18200000
> and before cpufreq@18591000
> 
Thanks for review! will address this in next revision.
>> +			compatible = "qcom,sc7280-epss-l3";
>> +			reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
>> +				<0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
> 
> Please align to the open parenthesis, to be consistent with the rest of
> the file.
> 
will address this in next revision.
>> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>> +			clock-names = "xo", "alternate";
>> +			#interconnect-cells = <1>;
>> +		};
>> +
>>   		ipa: ipa@1e40000 {
>>   			compatible = "qcom,sc7280-ipa";
> 
> Thanks,
> Georgi

Re: [v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

[Sibi Sankar]

Hey Odelu,
Thanks for the patch.

On 2021-08-10 12:16, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>  .../devicetree/bindings/interconnect/qcom,osm-l3.yaml          |  9 
> ++++++++-
>  include/dt-bindings/interconnect/qcom,osm-l3.h                 | 10 
> +++++++++-
>  2 files changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> index e701524..919fce4 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> @@ -18,13 +18,20 @@ properties:
>    compatible:
>      enum:
>        - qcom,sc7180-osm-l3
> +      - qcom,sc7280-epss-l3
>        - qcom,sc8180x-osm-l3
>        - qcom,sdm845-osm-l3
>        - qcom,sm8150-osm-l3
>        - qcom,sm8250-epss-l3
> 
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 4
> +    items:
> +      - description: OSM clock domain-0 base address and size
> +      - description: OSM clock domain-1 base address and size
> +      - description: OSM clock domain-2 base address and size
> +      - description: OSM clock domain-3 base address and size

Looks like you missed addressing
Stephen's comment from v4 i.e.
having descriptions based on
compatibles.

> 
>    clocks:
>      items:
> diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h
> b/include/dt-bindings/interconnect/qcom,osm-l3.h
> index 61ef649..99534a5 100644
> --- a/include/dt-bindings/interconnect/qcom,osm-l3.h
> +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
> @@ -1,6 +1,6 @@
>  /* SPDX-License-Identifier: GPL-2.0 */
>  /*
> - * Copyright (C) 2019 The Linux Foundation. All rights reserved.
> + * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved.
>   */
> 
>  #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
> @@ -11,5 +11,13 @@
> 
>  #define MASTER_EPSS_L3_APPS	0
>  #define SLAVE_EPSS_L3_SHARED	1
> +#define SLAVE_EPSS_L3_CPU0	2
> +#define SLAVE_EPSS_L3_CPU1	3
> +#define SLAVE_EPSS_L3_CPU2	4
> +#define SLAVE_EPSS_L3_CPU3	5
> +#define SLAVE_EPSS_L3_CPU4	6
> +#define SLAVE_EPSS_L3_CPU5	7
> +#define SLAVE_EPSS_L3_CPU6	8
> +#define SLAVE_EPSS_L3_CPU7	9
> 
>  #endif

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