From: Kewei Xu <kewei.xu@mediatek.com>
To: <wsa@the-dreams.de>
Cc: <matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<linux-i2c@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <leilk.liu@mediatek.com>,
<qii.wang@mediatek.com>, <liguo.zhang@mediatek.com>,
<caiyu.chen@mediatek.com>, <ot_daolong.zhu@mediatek.com>,
<yuhan.wei@mediatek.com>, <kewei.xu@mediatek.com>
Subject: [PATCH 7/7] i2c: mediatek: modify bus speed calculation formula
Date: Mon, 23 Aug 2021 21:05:37 +0800 [thread overview]
Message-ID: <1629723937-10839-8-git-send-email-kewei.xu@mediatek.com> (raw)
In-Reply-To: <1629723937-10839-1-git-send-email-kewei.xu@mediatek.com>
When clock-div is 0 or greater than 1, the bus speed
calculated by the old speed calculation formula will be
larger than the target speed. So we update the formula.
Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 35 +++++++++++++++++++++++++----------
1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 18b5659..0b42acd8 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -69,11 +69,12 @@
#define I2C_DEFAULT_CLK_DIV 5
#define MAX_SAMPLE_CNT_DIV 8
#define MAX_STEP_CNT_DIV 64
-#define MAX_CLOCK_DIV 256
+#define MAX_CLOCK_DIV_8BITS 256
+#define MAX_CLOCK_DIV_5BITS 32
#define MAX_HS_STEP_CNT_DIV 8
-#define I2C_STANDARD_MODE_BUFFER (1000 / 2)
-#define I2C_FAST_MODE_BUFFER (300 / 2)
-#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2)
+#define I2C_STANDARD_MODE_BUFFER (1000 / 3)
+#define I2C_FAST_MODE_BUFFER (300 / 3)
+#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3)
#define I2C_CONTROL_RS (0x1 << 1)
#define I2C_CONTROL_DMA_EN (0x1 << 2)
@@ -725,14 +726,26 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
unsigned int best_mul;
unsigned int cnt_mul;
int ret = -EINVAL;
+ int clock_div_constraint = 0;
if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
+ if (i2c->use_default_timing) {
+ clock_div_constraint = 0;
+ } else if (i2c->dev_comp->ltiming_adjust &&
+ i2c->ac_timing.inter_clk_div > 1) {
+ clock_div_constraint = 1;
+ } else if (i2c->dev_comp->ltiming_adjust &&
+ i2c->ac_timing.inter_clk_div == 0) {
+ clock_div_constraint = -1;
+ }
+
max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
base_step_cnt = max_step_cnt;
/* Find the best combination */
- opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
+ opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed) +
+ clock_div_constraint;
best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
/* Search for the best pair (sample_cnt, step_cnt) with
@@ -767,7 +780,8 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
sample_cnt = base_sample_cnt;
step_cnt = base_step_cnt;
- if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
+ if ((clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint))) >
+ target_speed) {
/* In this case, hardware can't support such
* low i2c_bus_freq
*/
@@ -854,13 +868,16 @@ static int mtk_i2c_set_speed_adjust_timing(struct mtk_i2c *i2c,
target_speed = i2c->speed_hz;
parent_clk /= i2c->clk_src_div;
- if (i2c->dev_comp->timing_adjust)
- max_clk_div = MAX_CLOCK_DIV;
+ if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
+ max_clk_div = MAX_CLOCK_DIV_5BITS;
+ else if (i2c->dev_comp->timing_adjust)
+ max_clk_div = MAX_CLOCK_DIV_8BITS;
else
max_clk_div = 1;
for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
clk_src = parent_clk / clk_div;
+ i2c->ac_timing.inter_clk_div = clk_div - 1;
if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
/* Set master code speed register */
@@ -907,8 +924,6 @@ static int mtk_i2c_set_speed_adjust_timing(struct mtk_i2c *i2c,
break;
}
- i2c->ac_timing.inter_clk_div = clk_div - 1;
-
return 0;
}
--
1.9.1
prev parent reply other threads:[~2021-08-23 13:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 13:05 [PATCH v5 0/7] Introducing an attribute to select the time setting Kewei Xu
2021-08-23 13:05 ` [PATCH 1/7] i2c: mediatek: fixing the incorrect register offset Kewei Xu
2021-08-23 13:05 ` [PATCH 2/7] i2c: mediatek: Reset the handshake signal between i2c and dma Kewei Xu
2021-08-23 13:05 ` [PATCH 3/7] i2c: mediatek: Dump i2c/dma register when a timeout occurs Kewei Xu
2021-08-23 13:05 ` [PATCH 4/7] dt-bindings: i2c: add attribute use-default-timing Kewei Xu
2021-08-23 13:05 ` [PATCH 5/7] i2c: mediatek: Add OFFSET_EXT_CONF setting back Kewei Xu
2021-08-23 13:05 ` [PATCH 6/7] i2c: mediatek: Isolate speed setting via dts for special devices Kewei Xu
2021-08-23 13:05 ` Kewei Xu [this message]
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