From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A372C433F5 for ; Tue, 14 Sep 2021 22:19:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DEA2861164 for ; Tue, 14 Sep 2021 22:19:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235785AbhINWVA (ORCPT ); Tue, 14 Sep 2021 18:21:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:55184 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235765AbhINWUy (ORCPT ); Tue, 14 Sep 2021 18:20:54 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id BC94D61164; Tue, 14 Sep 2021 22:19:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1631657976; bh=+KmAmWtMfypw9Fo3nOIC+Li00raIN7DW8K+8HiWqjv8=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=pYKEq2kho+6E/8YNSJRFJHbuQFcZpmzjanSTHkAFoBx+1fv4EHsHvYy6i8v2ySqll TgRFzq7p6yZVCkUf0uNMOLWNkK2pfubwJF2LK+OC9MsUR0qFfUJtDUn5c+JI4P9c/V nyFN31s2F6gLaWXKaD8uLeSMprzOldTpSlUmnh2Gdh4XpkQG18gyJa+WBqvLzcCqvB enf1ZVPnXSTvSohvRfLqWpfqQnDKOzX5GGSBUq0T0SKAFDGi3R00kD87H5NSW+SvM4 EnVW6J7plyhIVKL5DS2mEDX1BYIGuwP8N+HzFzqhEgYh/N9EiWchrPl9s+AHKy7BMN pX5tujO7FOelw== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20210914021633.26377-18-chun-jie.chen@mediatek.com> References: <20210914021633.26377-1-chun-jie.chen@mediatek.com> <20210914021633.26377-18-chun-jie.chen@mediatek.com> Subject: Re: [v3 17/24] clk: mediatek: Add MT8195 vdosys0 clock support From: Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, srv_heupstream@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, Chun-Jie Chen To: Chun-Jie Chen , Matthias Brugger , Nicolas Boichat , Rob Herring Date: Tue, 14 Sep 2021 15:19:35 -0700 Message-ID: <163165797561.763609.17217948869258296181@swboyd.mtv.corp.google.com> User-Agent: alot/0.9.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Chun-Jie Chen (2021-09-13 19:16:26) > Add MT8195 vdosys0 clock controller which provides clock gate > control in video system. This is integrated with mtk-mmsys > driver which will populate device by platform_device_register_data > to start vdosys clock driver. >=20 > Signed-off-by: Chun-Jie Chen > --- Applied to clk-next