From: Prasad Malisetty <pmaliset@codeaurora.org>
To: sanm@codeaurora.org, agross@kernel.org,
bjorn.andersson@linaro.org, robh+dt@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, vbadigan@codeaurora.org,
manivannan.sadhasivam@linaro.org
Cc: Prasad Malisetty <pmaliset@codeaurora.org>
Subject: [PATCH v1] arm64: dts: qcom: sc7280: Add pcie clock support
Date: Tue, 12 Oct 2021 18:06:11 +0530 [thread overview]
Message-ID: <1634042171-31461-1-git-send-email-pmaliset@codeaurora.org> (raw)
Add pcie clock phandle for sc7280 SoC
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
This change is depends on the below patch series.
https://lkml.org/lkml/2021/10/7/841
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 39635da..78694c1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -569,9 +569,10 @@
reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
- <0>, <0>, <0>, <0>, <0>, <0>;
+ <0>, <&pcie1_lane 0>,
+ <0>, <0>, <0>, <0>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
- "pcie_0_pipe_clk", "pcie_1_pipe-clk",
+ "pcie_0_pipe_clk", "pcie_1_pipe_clk",
"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
"ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next reply other threads:[~2021-10-12 12:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-12 12:36 Prasad Malisetty [this message]
2021-10-12 17:26 ` [PATCH v1] arm64: dts: qcom: sc7280: Add pcie clock support Stephen Boyd
2021-10-14 18:09 ` Prasad Malisetty
2021-10-12 23:00 ` kernel test robot
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