From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93CF5C433EF for ; Tue, 16 Nov 2021 11:02:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7830463213 for ; Tue, 16 Nov 2021 11:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234646AbhKPLF3 (ORCPT ); Tue, 16 Nov 2021 06:05:29 -0500 Received: from m43-7.mailgun.net ([69.72.43.7]:63499 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234592AbhKPLFM (ORCPT ); Tue, 16 Nov 2021 06:05:12 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1637060534; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=lkYYKJ9rC188XMHqEjBHgL+sHAmWDWuj2LTR40sZorg=; b=tVqM7jpdgJnz/Cvh6lbOBuLLMZAiRIdqkZ+PtDA4uCmnZZfRpbZpaHZZ+zYcYApSwstGKTxz r/Z3cCKWbjlCD68Uwed+sjMA5wTNQUxoVf45gbDe1bYJRWQ60xK5vEz+PfigQECR2kWvm3C5 sZWZrd8+6dFFfAjU2dBKinZxggc= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-west-2.postgun.com with SMTP id 61938fb64db4233966bbb1c7 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 16 Nov 2021 11:02:14 GMT Sender: pmaliset=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 7C5F2C43616; Tue, 16 Nov 2021 11:02:14 +0000 (UTC) Received: from pmaliset-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmaliset) by smtp.codeaurora.org (Postfix) with ESMTPSA id 25BE7C4360C; Tue, 16 Nov 2021 11:02:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 25BE7C4360C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org From: Prasad Malisetty To: swboyd@chromium.org, agross@kernel.org, bjorn.andersson@linaro.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org, mka@chromium.org, lorenzo.pieralisi@arm.com, svarbanov@mm-sol.com, bhelgaas@google.com Cc: Prasad Malisetty Subject: [PATCH v3 3/3] arm64: dts: qcom: Fix 'interrupt-map' parent address cells Date: Tue, 16 Nov 2021 16:31:48 +0530 Message-Id: <1637060508-30375-4-git-send-email-pmaliset@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1637060508-30375-1-git-send-email-pmaliset@codeaurora.org> References: <1637060508-30375-1-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update interrupt-map parent address cells for sc7280 Similar to existing Qcom SoCs. Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Signed-off-by: Prasad Malisetty --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3fb9338..9ca9c31 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1593,10 +1593,10 @@ interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project