From: Abel Vesa <abel.vesa@nxp.com>
To: Rob Herring <robh@kernel.org>,
Dong Aisheng <aisheng.dong@nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Fabio Estevam <festevam@gmail.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>,
linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org,
NXP Linux Team <linux-imx@nxp.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
Abel Vesa <abel.vesa@nxp.com>, Jacky Bai <ping.bai@nxp.com>
Subject: [RESEND v4 06/10] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
Date: Thu, 16 Dec 2021 20:48:10 +0200 [thread overview]
Message-ID: <1639680494-23183-7-git-send-email-abel.vesa@nxp.com> (raw)
In-Reply-To: <1639680494-23183-1-git-send-email-abel.vesa@nxp.com>
From: Jacky Bai <ping.bai@nxp.com>
Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
compared to i.MX8QXP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
.../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
new file mode 100644
index 000000000000..75b482966d94
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+&ddr_subsys {
+ db_ipg_clk: clock-db-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <456000000>;
+ clock-output-names = "db_ipg_clk";
+ };
+
+ db_pmu0: db-pmu@5ca40000 {
+ compatible = "fsl,imx8dxl-db-pmu";
+ reg = <0x5ca40000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_0>,
+ <&db_pmu0_lpcg IMX_LPCG_CLK_1>;
+ clock-names = "ipg", "cnt";
+ power-domains = <&pd IMX_SC_R_PERF>;
+ };
+
+ db_pmu0_lpcg: clock-controller@5cae0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5cae0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&db_ipg_clk>, <&db_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>,
+ <IMX_LPCG_CLK_1>;
+ clock-output-names = "perf_lpcg_cnt_clk",
+ "perf_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_PERF>;
+ };
+};
--
2.31.1
next prev parent reply other threads:[~2021-12-16 18:49 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 18:48 [RESEND v4 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
2021-12-16 18:48 ` [RESEND v4 01/10] dt-bindings: serial: fsl-lpuart: Fix i.MX 8QM compatible matching Abel Vesa
2021-12-16 18:48 ` [RESEND v4 02/10] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Abel Vesa
2022-01-26 12:27 ` Shawn Guo
2022-02-10 21:49 ` Abel Vesa
2021-12-16 18:48 ` [RESEND v4 03/10] arm64: dts: imx8-ss-lsio: Add mu5a mailbox Abel Vesa
2021-12-16 18:48 ` [RESEND v4 04/10] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl Abel Vesa
2022-01-26 12:36 ` Shawn Guo
2021-12-16 18:48 ` [RESEND v4 05/10] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi Abel Vesa
2022-01-26 12:47 ` Shawn Guo
2022-02-10 21:33 ` Abel Vesa
2021-12-16 18:48 ` Abel Vesa [this message]
2021-12-16 18:48 ` [RESEND v4 07/10] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl Abel Vesa
2021-12-16 18:48 ` [RESEND v4 08/10] arm64: dts: imx8dxl: Add i.MX8DXL evk board support Abel Vesa
2022-01-26 12:53 ` Shawn Guo
2022-02-10 21:27 ` Abel Vesa
2021-12-16 18:48 ` [RESEND v4 09/10] dt-bindings: fsl: scu: Add i.MX8DXL ocotp binding Abel Vesa
2021-12-16 18:48 ` [RESEND v4 10/10] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible Abel Vesa
2021-12-17 16:59 ` Greg Kroah-Hartman
2021-12-18 21:58 ` Abel Vesa
2021-12-20 15:35 ` Greg Kroah-Hartman
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