From: Will Deacon <will@kernel.org>
To: catalin.marinas@arm.com, Linu Cherian <lcherian@marvell.com>,
maz@kernel.org, tglx@linutronix.de
Cc: kernel-team@android.com, Will Deacon <will@kernel.org>,
linuc.decode@gmail.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
Date: Mon, 7 Mar 2022 22:03:32 +0000 [thread overview]
Message-ID: <164668950224.3277206.2552145973830842260.b4-ty@kernel.org> (raw)
In-Reply-To: <20220307143014.22758-1-lcherian@marvell.com>
On Mon, 7 Mar 2022 20:00:14 +0530, Linu Cherian wrote:
> When a IAR register read races with a GIC interrupt RELEASE event,
> GIC-CPU interface could wrongly return a valid INTID to the CPU
> for an interrupt that is already released(non activated) instead of 0x3ff.
>
> As a side effect, an interrupt handler could run twice, once with
> interrupt priority and then with idle priority.
>
> [...]
Applied to arm64 (for-next/errata), thanks!
[1/1] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
https://git.kernel.org/arm64/c/24a147bcef8c
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
next prev parent reply other threads:[~2022-03-07 22:04 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 14:30 [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR Linu Cherian
2022-03-07 14:39 ` Marc Zyngier
2022-03-07 16:00 ` Catalin Marinas
2022-03-07 22:03 ` Will Deacon [this message]
2023-05-30 8:13 ` Geert Uytterhoeven
2023-05-30 8:15 ` Geert Uytterhoeven
2022-03-09 17:40 ` Qian Cai
2022-03-09 17:50 ` Marc Zyngier
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