From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD795C433F5 for ; Tue, 8 Mar 2022 11:04:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346181AbiCHLFB (ORCPT ); Tue, 8 Mar 2022 06:05:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241299AbiCHLE4 (ORCPT ); Tue, 8 Mar 2022 06:04:56 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 252DA369D5; Tue, 8 Mar 2022 03:04:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646737440; x=1678273440; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=YpjfEbvehiXe8e4XM4EUc1DJ9S6Xucnc90uQamt5Q2Q=; b=guRE+BxB+yWtqGJsp/57WLVcQVRYGMrM+hSd9AvktjXrdRbrxHPkRNa8 H0PltwJ0LVGZXKYz8gLzRbgz6oLkwA/OEauc8AGIilPlZTfpUJtfVk54+ quB/KlviVNPzI9UxnormN5Ar6LJZysOolB0THumiuHHcGZGiJCPhC/Kgu U=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 08 Mar 2022 03:04:00 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 03:03:59 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 8 Mar 2022 03:03:58 -0800 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 8 Mar 2022 03:03:52 -0800 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v10 4/7] pinctrl: qcom: Update lpi pin group structure Date: Tue, 8 Mar 2022 16:33:11 +0530 Message-ID: <1646737394-4740-5-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646737394-4740-1-git-send-email-quic_srivasam@quicinc.com> References: <1646737394-4740-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update lpi group structure with core group_desc structure to avoid redundant struct params. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- drivers/pinctrl/qcom/Kconfig | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 44 +++++++++++++++----------------- 2 files changed, 22 insertions(+), 23 deletions(-) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index ca6f68a..31c4aa6 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -351,6 +351,7 @@ config PINCTRL_LPASS_LPI select PINMUX select PINCONF select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS depends on GPIOLIB help This is the pinctrl, pinmux, pinconf and gpiolib driver for the diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 3c15f80..54750ba 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -51,11 +51,11 @@ #define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ + .group.name = "gpio" #id, \ + .group.pins = gpio##id##_pins, \ .pin = id, \ .slew_offset = soff, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ + .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \ .funcs = (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -67,9 +67,7 @@ } struct lpi_pingroup { - const char *name; - const unsigned int *pins; - unsigned int npins; + struct group_desc group; unsigned int pin; /* Bit offset in slew register for SoundWire pins only */ int slew_offset; @@ -150,20 +148,20 @@ enum sm8250_lpi_functions { LPI_MUX__, }; -static const unsigned int gpio0_pins[] = { 0 }; -static const unsigned int gpio1_pins[] = { 1 }; -static const unsigned int gpio2_pins[] = { 2 }; -static const unsigned int gpio3_pins[] = { 3 }; -static const unsigned int gpio4_pins[] = { 4 }; -static const unsigned int gpio5_pins[] = { 5 }; -static const unsigned int gpio6_pins[] = { 6 }; -static const unsigned int gpio7_pins[] = { 7 }; -static const unsigned int gpio8_pins[] = { 8 }; -static const unsigned int gpio9_pins[] = { 9 }; -static const unsigned int gpio10_pins[] = { 10 }; -static const unsigned int gpio11_pins[] = { 11 }; -static const unsigned int gpio12_pins[] = { 12 }; -static const unsigned int gpio13_pins[] = { 13 }; +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; static const char * const swr_tx_clk_groups[] = { "gpio0" }; static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; static const char * const swr_rx_clk_groups[] = { "gpio3" }; @@ -262,7 +260,7 @@ static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev, { struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - return pctrl->data->groups[group].name; + return pctrl->data->groups[group].group.name; } static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev, @@ -272,8 +270,8 @@ static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev, { struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - *pins = pctrl->data->groups[group].pins; - *num_pins = pctrl->data->groups[group].npins; + *pins = pctrl->data->groups[group].group.pins; + *num_pins = pctrl->data->groups[group].group.num_pins; return 0; } -- 2.7.4