[PATCH v3 0/4] layerscape-pci binding updates

[PATCH v3 0/4] layerscape-pci binding updates

[Li Yang]

This series includes two binding changes from Zhiqiang's previous
submission ("[PATCHv5 0/6] PCI: layerscape: Add power management
support") and rebased to latest 5.17-rc1:

They describe the hardware and are not necessarily connected with the PM
driver changes.  The series also includes two other binding updates to
better describe the pcie hardware.

Updates in v3:
- Change the example to ls1088a as recommended by Hou Zhiqiang
- Change leading tabs in schema example to spaces
- Added reviewed by from Rob.  Now all the patches in the series are
  reviewed by DT maintainer.

Updates in v2:
- Refined the description of AER/PME in binding and updated commit
  message
- Changed AER/PME to upper case
- Added Ack from Rob

Hou Zhiqiang (2):
  dt-bindings: pci: layerscape-pci: Add a optional property big-endian
  dt-bindings: pci: layerscape-pci: Update the description of SCFG
    property

Li Yang (1):
  dt-bindings: pci: layerscape-pci: define AER/PME interrupts

Xiaowei Bao (1):
  dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for
    ls1028a

 .../bindings/pci/layerscape-pci.txt           | 65 +++++++++++--------
 1 file changed, 38 insertions(+), 27 deletions(-)

-- 
2.25.1

[PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

[Li Yang]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index f36efa73a470..215d2ee65c83 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -40,6 +40,10 @@ Required properties:
   of the data transferred from/to the IP block. This can avoid the software
   cache flush/invalid actions, and improve the performance significantly.
 
+Optional properties:
+- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
+  this property.
+
 Example:
 
 	pcie@3400000 {
-- 
2.25.1

[PATCH v3 2/4] dt-bindings: pci: layerscape-pci: Update the description of SCFG property

[Li Yang]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 215d2ee65c83..f1115fcd8088 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -34,7 +34,7 @@ Required properties:
   "intr": The interrupt that is asserted for controller interrupts
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
-  The second entry must be '0' or '1' based on physical PCIe controller index.
+  The second entry is the physical PCIe controller index starting from '0'.
   This is used to get SCFG PEXN registers
 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
   of the data transferred from/to the IP block. This can avoid the software
-- 
2.25.1

[PATCH v3 3/4] dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a

[Li Yang]

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add EP mode compatible string for ls1028a.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index f1115fcd8088..8fd6039a826b 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -23,6 +23,7 @@ Required properties:
         "fsl,ls1012a-pcie"
         "fsl,ls1028a-pcie"
   EP mode:
+	"fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
 	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
 	"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
 	"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
-- 
2.25.1

[PATCH v3 4/4] dt-bindings: pci: layerscape-pci: define AER/PME interrupts

[Li Yang]

Different platforms using this controller are using different numbers of
interrupt lines and the routing of events to these interrupt lines are
different too.  So instead of trying to define names for these interrupt
lines, we define the more specific AER/PME events that are routed to
these interrupt lines.

For platforms which only has a single interrupt line for miscellaneous
controller events, we can keep using the original "intr" name for
backward compatibility.

Also change the example from ls1021a to ls1088a for better representation.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/pci/layerscape-pci.txt           | 58 ++++++++++---------
 1 file changed, 32 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 8fd6039a826b..ee8a4791a78b 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -31,8 +31,14 @@ Required properties:
 - reg: base addresses and lengths of the PCIe controller register blocks.
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
+- interrupt-names: It could include the following entries:
+  "aer": Used for interrupt line which reports AER events when
+	 non MSI/MSI-X/INTx mode is used
+  "pme": Used for interrupt line which reports PME events when
+	 non MSI/MSI-X/INTx mode is used
+  "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
+	  which has a single interrupt line for miscellaneous controller
+	  events(could include AER and PME events).
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
   The second entry is the physical PCIe controller index starting from '0'.
@@ -47,27 +53,27 @@ Optional properties:
 
 Example:
 
-	pcie@3400000 {
-		compatible = "fsl,ls1021a-pcie";
-		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
-		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
-		reg-names = "regs", "config";
-		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "intr";
-		fsl,pcie-scfg = <&scfg 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		dma-coherent;
-		num-lanes = <4>;
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
-			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */
-			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
-	};
+        pcie@3400000 {
+                compatible = "fsl,ls1088a-pcie";
+                reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+                      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+                reg-names = "regs", "config";
+                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+                interrupt-names = "aer";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                dma-coherent;
+                num-viewport = <256>;
+                bus-range = <0x0 0xff>;
+                ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
+                          0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                msi-parent = <&its>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
+                                <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
+                                <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
+                                <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
+                iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+        };
-- 
2.25.1

Re: [PATCH v3 0/4] layerscape-pci binding updates

[Lorenzo Pieralisi]

On Fri, 11 Mar 2022 17:49:34 -0600, Li Yang wrote:
> This series includes two binding changes from Zhiqiang's previous
> submission ("[PATCHv5 0/6] PCI: layerscape: Add power management
> support") and rebased to latest 5.17-rc1:
> 
> They describe the hardware and are not necessarily connected with the PM
> driver changes.  The series also includes two other binding updates to
> better describe the pcie hardware.
> 
> [...]

Applied to pci/layerscape, thanks!

[1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian
      https://git.kernel.org/lpieralisi/pci/c/6c389328c9
[2/4] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
      https://git.kernel.org/lpieralisi/pci/c/84f293b204
[3/4] dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a
      https://git.kernel.org/lpieralisi/pci/c/cddc1a9ab3
[4/4] dt-bindings: pci: layerscape-pci: define AER/PME interrupts
      https://git.kernel.org/lpieralisi/pci/c/a3b18f5f1d

Thanks,
Lorenzo

Re: [PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

[Bjorn Helgaas]

On Fri, Mar 11, 2022 at 05:49:35PM -0600, Li Yang wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> This property is to indicate the endianness when accessing the
> PEX_LUT and PF register block, so if these registers are
> implemented in big-endian, specify this property.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index f36efa73a470..215d2ee65c83 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -40,6 +40,10 @@ Required properties:
>    of the data transferred from/to the IP block. This can avoid the software
>    cache flush/invalid actions, and improve the performance significantly.
>  
> +Optional properties:
> +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
> +  this property.

What's the purpose of this?  I don't see any code that uses this
property.

I guess this might be related to of_device_is_big_endian()?  I do see
some code that uses of_device_is_big_endian(), but nothing that looks
relevant to layerscape in particular.

>  Example:
>  
>  	pcie@3400000 {
> -- 
> 2.25.1
> 

Re: [PATCH v3 4/4] dt-bindings: pci: layerscape-pci: define AER/PME interrupts

[Bjorn Helgaas]

On Fri, Mar 11, 2022 at 05:49:38PM -0600, Li Yang wrote:
> Different platforms using this controller are using different numbers of
> interrupt lines and the routing of events to these interrupt lines are
> different too.  So instead of trying to define names for these interrupt
> lines, we define the more specific AER/PME events that are routed to
> these interrupt lines.
> 
> For platforms which only has a single interrupt line for miscellaneous
> controller events, we can keep using the original "intr" name for
> backward compatibility.
> 
> Also change the example from ls1021a to ls1088a for better representation.
> 
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>

1) Please pay attention to your subject lines and make them match.
In this series you have:

  dt-bindings: pci: layerscape-pci: Add a optional property big-endian
  dt-bindings: pci: layerscape-pci: Update the description of SCFG property
  dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a
  dt-bindings: pci: layerscape-pci: define AER/PME interrupt

Note that all are capitalized except "define AER/PME interrupt".

2) Also capitalize "AER" in the comment below so it matches usage in
the commit log and the property descriptions.

3) This diff is HUGE because you replace a bunch of tabs with spaces.
That seems like a pointless change, but if you want to do it, at least
do it in a separate patch all by itself that *only* changes tabs to
spaces.  Then we'll be able to see what actually happened in the
patch that adds the properties.

This has already been merged, so unless you need to update this series
for some other reason, these are just tips for the future.

> ---
>  .../bindings/pci/layerscape-pci.txt           | 58 ++++++++++---------
>  1 file changed, 32 insertions(+), 26 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 8fd6039a826b..ee8a4791a78b 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -31,8 +31,14 @@ Required properties:
>  - reg: base addresses and lengths of the PCIe controller register blocks.
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
> -- interrupt-names: Must include the following entries:
> -  "intr": The interrupt that is asserted for controller interrupts
> +- interrupt-names: It could include the following entries:
> +  "aer": Used for interrupt line which reports AER events when
> +	 non MSI/MSI-X/INTx mode is used
> +  "pme": Used for interrupt line which reports PME events when
> +	 non MSI/MSI-X/INTx mode is used
> +  "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
> +	  which has a single interrupt line for miscellaneous controller
> +	  events(could include AER and PME events).
>  - fsl,pcie-scfg: Must include two entries.
>    The first entry must be a link to the SCFG device node
>    The second entry is the physical PCIe controller index starting from '0'.
> @@ -47,27 +53,27 @@ Optional properties:
>  
>  Example:
>  
> -	pcie@3400000 {
> -		compatible = "fsl,ls1021a-pcie";
> -		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
> -		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
> -		reg-names = "regs", "config";
> -		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> -		interrupt-names = "intr";
> -		fsl,pcie-scfg = <&scfg 0>;
> -		#address-cells = <3>;
> -		#size-cells = <2>;
> -		device_type = "pci";
> -		dma-coherent;
> -		num-lanes = <4>;
> -		bus-range = <0x0 0xff>;
> -		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
> -			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */
> -			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> -		#interrupt-cells = <1>;
> -		interrupt-map-mask = <0 0 0 7>;
> -		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
> -				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> -				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> -				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> -	};
> +        pcie@3400000 {
> +                compatible = "fsl,ls1088a-pcie";
> +                reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
> +                      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
> +                reg-names = "regs", "config";
> +                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> +                interrupt-names = "aer";
> +                #address-cells = <3>;
> +                #size-cells = <2>;
> +                device_type = "pci";
> +                dma-coherent;
> +                num-viewport = <256>;
> +                bus-range = <0x0 0xff>;
> +                ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
> +                          0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> +                msi-parent = <&its>;
> +                #interrupt-cells = <1>;
> +                interrupt-map-mask = <0 0 0 7>;
> +                interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
> +                                <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
> +                                <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
> +                                <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
> +                iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> +        };
> -- 
> 2.25.1
> 

RE: [PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

[Leo Li]

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Thursday, April 14, 2022 2:28 PM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>; Z.Q. Hou
> <zhiqiang.hou@nxp.com>; Rob Herring <robh@kernel.org>; linux-
> pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional
> property big-endian
> 
> On Fri, Mar 11, 2022 at 05:49:35PM -0600, Li Yang wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > This property is to indicate the endianness when accessing the PEX_LUT
> > and PF register block, so if these registers are implemented in
> > big-endian, specify this property.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > ---
> >  Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index f36efa73a470..215d2ee65c83 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -40,6 +40,10 @@ Required properties:
> >    of the data transferred from/to the IP block. This can avoid the software
> >    cache flush/invalid actions, and improve the performance significantly.
> >
> > +Optional properties:
> > +- big-endian: If the PEX_LUT and PF register block is in big-endian,
> > +specify
> > +  this property.
> 
> What's the purpose of this?  I don't see any code that uses this property.
> 
> I guess this might be related to of_device_is_big_endian()?  I do see some
> code that uses of_device_is_big_endian(), but nothing that looks relevant to
> layerscape in particular.

These two register blocks are not used in basic operation but are needed for the power management support.  There is patch in review from Zhiqiang ("PCI: layerscape: Add power management support") that need to use these registers.

But since this is an intrinsic property of the hardware, I think we should include it in the binding and dtses before the code using it hit the mainline.

> 
> >  Example:
> >
> >  	pcie@3400000 {
> > --
> > 2.25.1
> >

RE: [PATCH v3 4/4] dt-bindings: pci: layerscape-pci: define AER/PME interrupts

[Leo Li]

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Thursday, April 14, 2022 2:40 PM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>; Z.Q. Hou
> <zhiqiang.hou@nxp.com>; Rob Herring <robh@kernel.org>; linux-
> pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 4/4] dt-bindings: pci: layerscape-pci: define AER/PME
> interrupts
> 
> On Fri, Mar 11, 2022 at 05:49:38PM -0600, Li Yang wrote:
> > Different platforms using this controller are using different numbers
> > of interrupt lines and the routing of events to these interrupt lines
> > are different too.  So instead of trying to define names for these
> > interrupt lines, we define the more specific AER/PME events that are
> > routed to these interrupt lines.
> >
> > For platforms which only has a single interrupt line for miscellaneous
> > controller events, we can keep using the original "intr" name for
> > backward compatibility.
> >
> > Also change the example from ls1021a to ls1088a for better representation.
> >
> > Signed-off-by: Li Yang <leoyang.li@nxp.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> 
> 1) Please pay attention to your subject lines and make them match.
> In this series you have:
> 
>   dt-bindings: pci: layerscape-pci: Add a optional property big-endian
>   dt-bindings: pci: layerscape-pci: Update the description of SCFG property
>   dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a
>   dt-bindings: pci: layerscape-pci: define AER/PME interrupt
> 
> Note that all are capitalized except "define AER/PME interrupt".
> 
> 2) Also capitalize "AER" in the comment below so it matches usage in the
> commit log and the property descriptions.

Thanks for the suggestion.

> 
> 3) This diff is HUGE because you replace a bunch of tabs with spaces.
> That seems like a pointless change, but if you want to do it, at least do it in a
> separate patch all by itself that *only* changes tabs to spaces.  Then we'll be
> able to see what actually happened in the patch that adds the properties.

Right.  I changed to use space because the examples in yaml bindings do require space instead of tab.  But it is not really necessary now as this binding has not been converted to yaml yet.

> 
> This has already been merged, so unless you need to update this series for
> some other reason, these are just tips for the future.
> 
> > ---
> >  .../bindings/pci/layerscape-pci.txt           | 58 ++++++++++---------
> >  1 file changed, 32 insertions(+), 26 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 8fd6039a826b..ee8a4791a78b 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -31,8 +31,14 @@ Required properties:
> >  - reg: base addresses and lengths of the PCIe controller register blocks.
> >  - interrupts: A list of interrupt outputs of the controller. Must contain an
> >    entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > -  "intr": The interrupt that is asserted for controller interrupts
> > +- interrupt-names: It could include the following entries:
> > +  "aer": Used for interrupt line which reports AER events when
> > +	 non MSI/MSI-X/INTx mode is used
> > +  "pme": Used for interrupt line which reports PME events when
> > +	 non MSI/MSI-X/INTx mode is used
> > +  "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
> > +	  which has a single interrupt line for miscellaneous controller
> > +	  events(could include AER and PME events).
> >  - fsl,pcie-scfg: Must include two entries.
> >    The first entry must be a link to the SCFG device node
> >    The second entry is the physical PCIe controller index starting from '0'.
> > @@ -47,27 +53,27 @@ Optional properties:
> >
> >  Example:
> >
> > -	pcie@3400000 {
> > -		compatible = "fsl,ls1021a-pcie";
> > -		reg = <0x00 0x03400000 0x0 0x00010000   /* controller
> registers */
> > -		       0x40 0x00000000 0x0 0x00002000>; /* configuration space
> */
> > -		reg-names = "regs", "config";
> > -		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt */
> > -		interrupt-names = "intr";
> > -		fsl,pcie-scfg = <&scfg 0>;
> > -		#address-cells = <3>;
> > -		#size-cells = <2>;
> > -		device_type = "pci";
> > -		dma-coherent;
> > -		num-lanes = <4>;
> > -		bus-range = <0x0 0xff>;
> > -		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0
> 0x00010000   /* downstream I/O */
> > -			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0
> 0x20000000   /* prefetchable memory */
> > -			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > -		#interrupt-cells = <1>;
> > -		interrupt-map-mask = <0 0 0 7>;
> > -		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91
> IRQ_TYPE_LEVEL_HIGH>,
> > -				<0000 0 0 2 &gic GIC_SPI 188
> IRQ_TYPE_LEVEL_HIGH>,
> > -				<0000 0 0 3 &gic GIC_SPI 190
> IRQ_TYPE_LEVEL_HIGH>,
> > -				<0000 0 0 4 &gic GIC_SPI 192
> IRQ_TYPE_LEVEL_HIGH>;
> > -	};
> > +        pcie@3400000 {
> > +                compatible = "fsl,ls1088a-pcie";
> > +                reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers
> */
> > +                      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
> > +                reg-names = "regs", "config";
> > +                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> > +                interrupt-names = "aer";
> > +                #address-cells = <3>;
> > +                #size-cells = <2>;
> > +                device_type = "pci";
> > +                dma-coherent;
> > +                num-viewport = <256>;
> > +                bus-range = <0x0 0xff>;
> > +                ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0
> 0x00010000   /* downstream I/O */
> > +                          0x82000000 0x0 0x40000000 0x20 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > +                msi-parent = <&its>;
> > +                #interrupt-cells = <1>;
> > +                interrupt-map-mask = <0 0 0 7>;
> > +                interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
> > +                                <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
> > +                                <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
> > +                                <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
> > +                iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> > +        };
> > --
> > 2.25.1
> >