From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AE3AC433F5 for ; Sun, 17 Apr 2022 09:59:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233855AbiDQKBv (ORCPT ); Sun, 17 Apr 2022 06:01:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233831AbiDQKBt (ORCPT ); Sun, 17 Apr 2022 06:01:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EB46C03 for ; Sun, 17 Apr 2022 02:59:14 -0700 (PDT) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1650189552; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=YkYt3Tcru6U/tvL6nk1qOZUP7dY9n3fkRkbnXJoebFE=; b=ZGQAGQCbew+ivI4I5SYfRkpWeFkhEUlCf9kvQd5nL1AOXkX1zMxoC0F0BdCaScB+IlNq3C RalHuiW2TmNwzM1RhxMtjed2WovGu7cFExCARcm4XoVCnUFwxUnjdEToDUza19JMFraV/n lXwXEJpAvrxxJFcmeKlBUuGd2bY7eh0bMlVtM7b0SyfL+Ktm8njy/YSmGJIMOjum1Rw6in px8YQLBV8vPynPl3ZYZibZQiKP/t2DCaXIzAfCQnh/dSTZXp7MJHGaXDkj1meGAO0Mg6Vx RW/Z6CcvmN/A0M974z2CxKRblKMRFv+4RjcXO3yXPYxSJ03wKp6vNHPDCzb8gA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1650189552; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=YkYt3Tcru6U/tvL6nk1qOZUP7dY9n3fkRkbnXJoebFE=; b=09CE+gZ5bDYCvErZDYgrjLS6AJjOhaS7KDz5xFPnYlfVlRcXHIjzP0mw/0LvDBvAc+GSwV liLsPXNyG7uDSjDQ== To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Subject: [GIT pull] irq/urgent for v5.18-rc3 Message-ID: <165018953450.44773.6382828227632028472.tglx@xen13> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Date: Sun, 17 Apr 2022 11:59:11 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Linus, please pull the latest irq/urgent branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-urgent-2022-= 04-17 up to: 08d835dff916: genirq/affinity: Consider that CPUs on nodes can be unb= alanced A single fix for the interrupt affinity spreading logic to take into account that there can be an imbalance between present and possible CPUs, which causes already assigned bits to be overwritten. Thanks, tglx ------------------> Rei Yamamoto (1): genirq/affinity: Consider that CPUs on nodes can be unbalanced kernel/irq/affinity.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/kernel/irq/affinity.c b/kernel/irq/affinity.c index f7ff8919dc9b..fdf170404650 100644 --- a/kernel/irq/affinity.c +++ b/kernel/irq/affinity.c @@ -269,8 +269,9 @@ static int __irq_build_affinity_masks(unsigned int startv= ec, */ if (numvecs <=3D nodes) { for_each_node_mask(n, nodemsk) { - cpumask_or(&masks[curvec].mask, &masks[curvec].mask, - node_to_cpumask[n]); + /* Ensure that only CPUs which are in both masks are set */ + cpumask_and(nmsk, cpu_mask, node_to_cpumask[n]); + cpumask_or(&masks[curvec].mask, &masks[curvec].mask, nmsk); if (++curvec =3D=3D last_affv) curvec =3D firstvec; }