From: Sibi Sankar <quic_sibis@quicinc.com>
To: <bjorn.andersson@linaro.org>
Cc: <agross@kernel.org>, <djakov@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <p.zabel@pengutronix.de>,
<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>,
Sibi Sankar <quic_sibis@quicinc.com>
Subject: [PATCH 1/3] dt-bindings: interconnect: Update email address
Date: Thu, 2 Jun 2022 06:18:41 +0530 [thread overview]
Message-ID: <1654130923-18722-1-git-send-email-quic_sibis@quicinc.com> (raw)
Update email address to the quicinc.com domain.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index 116e434d0daa..bf538c0c5a81 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
maintainers:
- - Sibi Sankar <sibis@codeaurora.org>
+ - Sibi Sankar <quic_sibis@quicinc.com>
description:
L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
--
2.7.4
next reply other threads:[~2022-06-02 0:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-02 0:48 Sibi Sankar [this message]
2022-06-02 0:48 ` [PATCH 2/3] dt-bindings: reset: aoss: Update e-mail address Sibi Sankar
2022-06-02 0:48 ` [PATCH 3/3] dt-bindings: reset: pdc: Update email address Sibi Sankar
2022-06-02 11:48 ` [PATCH 1/3] dt-bindings: interconnect: " Krzysztof Kozlowski
2022-06-02 14:43 ` Rob Herring
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