From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04BCACCA473 for ; Mon, 27 Jun 2022 11:50:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238338AbiF0Lut (ORCPT ); Mon, 27 Jun 2022 07:50:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238246AbiF0LsK (ORCPT ); Mon, 27 Jun 2022 07:48:10 -0400 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 569A2BCB6 for ; Mon, 27 Jun 2022 04:40:08 -0700 (PDT) Received: from localhost.localdomain.localdomain (unknown [10.2.5.46]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dx39kNl7liP_FfAA--.6156S2; Mon, 27 Jun 2022 19:39:57 +0800 (CST) From: Jianmin Lv To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Hanjun Guo , Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen Subject: [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Date: Mon, 27 Jun 2022 19:39:44 +0800 Message-Id: <1656329997-20524-1-git-send-email-lvjianmin@loongson.cn> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CM-TRANSID: AQAAf9Dx39kNl7liP_FfAA--.6156S2 X-Coremail-Antispam: 1UD129KBjvJXoWxKFyrWFy5Cr4rWF17CFWUtwb_yoWfKw18pF 43Cr1aqF4UGryaqr13Aw48WFy5JFn3Jw4Dta4xtryxXrn8Ar1DKr18JFykZry7ArWxXr1U ZFWjqw4UGw1UAr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUvY1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AE w4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2 IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr1UM28EF7xvwVC2 z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcV Aq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j 6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64 vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVCm-wCF04k20xvY0x0EwIxGrwCF 04k20xvE74AGY7Cv6cx26ryrJr1UJwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1l IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6rWUJVWrZr1UMIIF0xvEx4A2jsIE14v2 6r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0J UdHUDUUUUU= X-CM-SenderInfo: 5oymxthqpl0qxorr0wxvrqhubq/ Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its boot protocol LoongArch-specific interrupt controllers (similar to APIC) are already added in the ACPI Specification 6.5(which may be published in early June this year and the board is reviewing the draft). Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all controllers out of CPU (i.e., in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, and there are two models of hierarchy (legacy model and extended model). Legacy IRQ model: In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC. +---------------------------------------------+ | | | +-----+ +---------+ +-------+ | | | IPI | --> | CPUINTC | <-- | Timer | | | +-----+ +---------+ +-------+ | | ^ | | | | | +---------+ +-------+ | | | LIOINTC | <-- | UARTs | | | +---------+ +-------+ | | ^ | | | | | +-----------+ | | | HTVECINTC | | | +-----------+ | | ^ ^ | | | | | | +---------+ +---------+ | | | PCH-PIC | | PCH-MSI | | | +---------+ +---------+ | | ^ ^ ^ | | | | | | | +---------+ +---------+ +---------+ | | | PCH-LPC | | Devices | | Devices | | | +---------+ +---------+ +---------+ | | ^ | | | | | +---------+ | | | Devices | | | +---------+ | | | | | +---------------------------------------------+ Extended IRQ model: In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to to CPUINTC directly. +--------------------------------------------------------+ | | | +-----+ +---------+ +-------+ | | | IPI | --> | CPUINTC | <-- | Timer | | | +-----+ +---------+ +-------+ | | ^ ^ | | | | | | +---------+ +---------+ +-------+ | | | EIOINTC | | LIOINTC | <-- | UARTs | | | +---------+ +---------+ +-------+ | | ^ ^ | | | | | | +---------+ +---------+ | | | PCH-PIC | | PCH-MSI | | | +---------+ +---------+ | | ^ ^ ^ | | | | | | | +---------+ +---------+ +---------+ | | | PCH-LPC | | Devices | | Devices | | | +---------+ +---------+ +---------+ | | ^ | | | | | +---------+ | | | Devices | | | +---------+ | | | | | +--------------------------------------------------------+ The hierarchy model is constructed by parsing irq contronler structures in MADT. Some controllers((e.g. LIOINTC, HTVECINTC, EIOINTC and PCH-LPC) are hardcodingly connected to their parents, so their irqdomins are separately routed to their parents in a fixed way. Some controllers (e.g. PCH-PIC and PCH-MSI) could be routed to different parents for different CPU. The firmware will config EIOINTC for the newer CPU and config HTVECINTC for old CPU in MADT. By this way, PCH-PIC and PCH-MSI irqdomain can only be routed one parent irqdomin: HTVECINTC or EIOINTC. Example of irqchip topology in a system with two chipsets: +------------------------------------------------------------+ | | | +------------------+ | | | CPUINTC | | | +------------------+ | | ^ ^ | | | | | | +----------+ +----------+ | | | EIOINTC 0| | EIOINTC 1| | | +----------+ +----------+ | | ^ ^ ^ ^ | | | | | | | | +----------+ +----------+ +----------+ +----------+ | | | PCH-PIC 0| | PCH-MSI 0| | PCH-PIC 1| | PCH-MSI 1| | | +----------+ +----------+ +----------+ +----------+ | | | | | +------------------------------------------------------------+ For systems with two chipsets, there are tow group(consists of EIOINTC, PCH-PIC and PCH-MSI) irqdomains, and each group has same node id. So we defined a structure to mantain the relation of node and it's parent irqdomain. struct acpi_vector_group { int node; int pci_segment; struct irq_domain *parent; }; The initialization and use of acpi_vector_group array are following: 1 Entry of struct acpi_vector_group array initialization: By parsing MCFG, the node id（from bit44-47 of Base Address）and pci segment are extracted. And from MADT, we have the node id of each EIOINTC. entry.node = node id of pci segment entry.pci_segment = pci segment (only for msi irqdomain) By matching node id of entry and EIOINTC to set parent. entry.parent = EIOINTC irqdomain(node id of EIOINTC == node id of pci segment) 2 Get parent irqdomain for PCH-PIC: >From MADT, we have the node id of each PCH-PIC(from bit44-47 of Base Address). if (node of entry i == node of PCH-PIC) return entrys[i].parent; 3 Get parent irqdomain for PCH-MSI of pci segment: return entrys[i].parent; (i is the index of msi irqdomain) 4 How to select a correct irqdomain to map irq for a device? For devices using legacy irq behind PCH-PIC, GSI is used to select correct PCH-PIC irqdomain. For devices using msi irq behind PCH-MSI, the pci segmen of the device is used to select correct PCH-MSI irqdomain. V1 -> V2: 1, Remove queued patches; 2, Move common logic of DT/ACPI probing to common functions; 3, Split .suspend()/.resume() functions to separate patches. V2 -> V3: 1, Fix a bug for loongson-pch-pic probe; 2, Some minor improvements for LPC controller. V3 -> V4: 1, Rework the CPU interrupt controller driver; 2, Some minor improvements for other controllers. V4 -> V5: 1, Add a description of LoonArch's IRQ model; 2, Support multiple EIOINTCs in one system; 3, Some minor improvements for other controllers. V5 -> V6: 1, Attach a fwnode to CPUINTC irq domain; 2, Use raw spinlock instead of generic spinlock; 3, Improve the method of restoring EIOINTC state; 4, Update documentation, comments and commit messages. V6 -> V7: 1, Fix build warnings reported by kernel test robot. V7 -> V8: 1, Add arguments sanity checking for irqchip init functions; 2, Support Loongson-3C5000 (One NUMA Node includes 4 EIOINTC Node). V8 -> V9: 1, Rebase on 5.17-rc5; 2, Update cover letter; 3, Some small improvements. V9 -> V10: 1, Rebase on 5.17-rc6; 2, Fix build warnings reported by kernel test robot. V10 -> V11: 1, Rebase on 5.18-rc4; 2, Fix irq affinity setting for EIOINTC; 3, Fix hwirq allocation failure for EIOINTC. V11 -> RFC: 1, Refactored the way to build irqchip hierarchy topology. RFC -> RFC V2: 1, Move all IO-interrupt related code to driver/irqchip from arch directory. 2. Add description for an example of two chipsets system. RFC V2 -> RFC V3: 1, Add support for multiple GSI domains 2, Use ACPI_GENERIC_GSI for GSI handling 3, Drop suspend-resume stuff 4, Export fwnode handles instead of irq domain handles RFC V3 -> V12: 1, Address patch attributions of the patch series V12 -> V13 1 Based on 5.19-rc2 2 Remove arch specified gsi code 3 Split some 'common' code into the various drivers where they belong. 4 Allow acpi_gsi_to_irq() to have an arch-specific fallback Huacai Chen (7): irqchip: Add Loongson PCH LPC controller support irqchip/loongson-pch-pic: Add ACPI init support irqchip/loongson-pch-msi: Add ACPI init support irqchip/loongson-htvec: Add ACPI init support irqchip/loongson-liointc: Add ACPI init support irqchip: Add Loongson Extended I/O interrupt controller support irqchip: Add LoongArch CPU interrupt controller support Jianmin Lv (4): genirq/generic_chip: export irq_unmap_generic_chip LoongArch: Use ACPI_GENERIC_GSI for gsi handling irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch LoongArch: Fix irq number for timer and ipi Marc Zyngier (2): APCI: irq: Add support for multiple GSI domains ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback arch/loongarch/Kconfig | 1 + arch/loongarch/include/asm/irq.h | 43 ++-- arch/loongarch/kernel/acpi.c | 65 ------ arch/loongarch/kernel/irq.c | 37 +++- arch/loongarch/kernel/time.c | 2 +- drivers/acpi/bus.c | 3 + drivers/acpi/irq.c | 58 +++-- drivers/irqchip/Kconfig | 28 +++ drivers/irqchip/Makefile | 3 + drivers/irqchip/irq-gic-v3.c | 18 +- drivers/irqchip/irq-gic.c | 18 +- drivers/irqchip/irq-loongarch-cpu.c | 168 +++++++++++++++ drivers/irqchip/irq-loongson-eiointc.c | 375 +++++++++++++++++++++++++++++++++ drivers/irqchip/irq-loongson-htvec.c | 121 ++++++++--- drivers/irqchip/irq-loongson-liointc.c | 227 +++++++++++++------- drivers/irqchip/irq-loongson-pch-lpc.c | 203 ++++++++++++++++++ drivers/irqchip/irq-loongson-pch-msi.c | 147 +++++++++---- drivers/irqchip/irq-loongson-pch-pic.c | 200 +++++++++++++++--- include/linux/acpi.h | 4 +- include/linux/cpuhotplug.h | 1 + include/linux/irq.h | 1 + kernel/irq/generic-chip.c | 2 +- 22 files changed, 1416 insertions(+), 309 deletions(-) create mode 100644 drivers/irqchip/irq-loongarch-cpu.c create mode 100644 drivers/irqchip/irq-loongson-eiointc.c create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c -- 1.8.3.1