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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT014.mail.protection.outlook.com (10.13.177.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5482.10 via Frontend Transport; Mon, 1 Aug 2022 20:56:15 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 1 Aug 2022 15:56:12 -0500 Subject: [PATCH v2 05/10] x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag From: Babu Moger To: , , , , CC: , , , , , , , Date: Mon, 1 Aug 2022 15:56:12 -0500 Message-ID: <165938737200.724959.7329082251366107356.stgit@bmoger-ubuntu> In-Reply-To: <165938717220.724959.10931629283087443782.stgit@bmoger-ubuntu> References: <165938717220.724959.10931629283087443782.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2022 20:56:15.3976 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c95c3c4-d690-4509-1b62-08da7400464f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3492 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer AMD processors support the new feature Bandwidth Monitoring Event=0A= Configuration (BMEC).=0A= =0A= Support of this feature is available via CPUID Fn8000_0020_EBX_x0 (ECX=3D0)= .=0A= Bits Field Name Description=0A= 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC)=0A= =0A= Currently, the bandwidth monitoring events mbm_total_bytes and=0A= mbm_local_bytes are set to count all the total and local reads/writes=0A= respectively. With the introduction of SLOW memory, the two counters are=0A= not enough to count all the different types of memory events. With the=0A= feature BMEC, the users have the option to configure mbm_total_bytes and=0A= mbm_local_bytes to count the specific type of events.=0A= =0A= Each BMEC event has a configuration MSR, QOS_EVT_CFG (0x000_0400h +=0A= EventID) which contains one field for each Bandwidth Type that can be used= =0A= to configure the Bandwidth Event to track any combination of supported=0A= bandwidth types. The event will count requests from every Bandwidth Type= =0A= bit that is set in the corresponding configuration register.=0A= =0A= Following are the types of events supported.=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= Bits Description 6 Dirty Victims from the QOS domain to all types= =0A= of memory 5 Reads to slow memory in the non-local NUMA domain 4=0A= Reads to slow memory in the local NUMA domain 3 Non-temporal writes= =0A= to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1= =0A= Reads to memory in the non-local NUMA domain 0 Reads to memory in the= =0A= local NUMA domain=0A= =0A= Feature description is available in the specification, "AMD64 Technology=0A= Platform Quality of Service Extensions, Revision: 1.03 Publication # 56375= =0A= Revision: 1.03 Issue Date: February 2022".=0A= =0A= Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions=0A= Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537=0A= Signed-off-by: Babu Moger =0A= ---=0A= arch/x86/include/asm/cpufeatures.h | 1 +=0A= arch/x86/kernel/cpu/scattered.c | 1 +=0A= 2 files changed, 2 insertions(+)=0A= =0A= diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h=0A= index 14b5cc8da75c..2608416f5d0a 100644=0A= --- a/arch/x86/include/asm/cpufeatures.h=0A= +++ b/arch/x86/include/asm/cpufeatures.h=0A= @@ -304,6 +304,7 @@=0A= #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */=0A= #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */=0A= #define X86_FEATURE_SMBA (11*32+17) /* SLOW Memory Bandwidth Allocation *= /=0A= +#define X86_FEATURE_BMEC (11*32+18) /* AMD Bandwidth Monitoring Event Con= figuration (BMEC) */=0A= =0A= /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */= =0A= #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */=0A= diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c=0A= index 885ecf46abb2..7981df0b910e 100644=0A= --- a/arch/x86/kernel/cpu/scattered.c=0A= +++ b/arch/x86/kernel/cpu/scattered.c=0A= @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] =3D {=0A= { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },=0A= { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },=0A= { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },=0A= + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },=0A= { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },=0A= { 0, 0, 0, 0, 0 }=0A= };=0A= =0A=