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Subject: Re: [RFC V1 02/11] arm64/perf: Add register definitions for BRBE
To:     Marc Zyngier <maz@kernel.org>
Cc:     linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        linux-perf-users@vger.kernel.org
References: <1642998653-21377-1-git-send-email-anshuman.khandual@arm.com>
 <1642998653-21377-3-git-send-email-anshuman.khandual@arm.com>
 <877dap8c0o.wl-maz@kernel.org>
From:   Anshuman Khandual <anshuman.khandual@arm.com>
Message-ID: <165b3f65-c92e-75e3-9485-548e1c862ec4@arm.com>
Date:   Tue, 25 Jan 2022 10:34:22 +0530
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On 1/24/22 7:35 PM, Marc Zyngier wrote:
> On Mon, 24 Jan 2022 04:30:44 +0000,
> Anshuman Khandual <anshuman.khandual@arm.com> wrote:
>>
>> This adds BRBE related register definitions and various other related field
>> macros there in. These will be used subsequently in a BRBE driver which is
>> being added later on.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>  arch/arm64/include/asm/sysreg.h | 216 ++++++++++++++++++++++++++++++++
>>  1 file changed, 216 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 898bee0004ae..d8fd7e806a47 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -141,6 +141,218 @@
>>  #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
>>  #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
>>  
>> +/*
>> + * BRBINF<N>_EL1 Encoding: [2, 1, 8, CRm, op2]
>> + *
>> + * derived as <CRm> = c{N<3:0>} <op2> = (N<4>x4 + 0)
>> + */
>> +#define SYS_BRBINF0_EL1			sys_reg(2, 1, 8, 0, 0)
>> +#define SYS_BRBINF1_EL1			sys_reg(2, 1, 8, 1, 0)
>> +#define SYS_BRBINF2_EL1			sys_reg(2, 1, 8, 2, 0)
>> +#define SYS_BRBINF3_EL1			sys_reg(2, 1, 8, 3, 0)
>> +#define SYS_BRBINF4_EL1			sys_reg(2, 1, 8, 4, 0)
>> +#define SYS_BRBINF5_EL1			sys_reg(2, 1, 8, 5, 0)
>> +#define SYS_BRBINF6_EL1			sys_reg(2, 1, 8, 6, 0)
>> +#define SYS_BRBINF7_EL1			sys_reg(2, 1, 8, 7, 0)
>> +#define SYS_BRBINF8_EL1			sys_reg(2, 1, 8, 8, 0)
>> +#define SYS_BRBINF9_EL1			sys_reg(2, 1, 8, 9, 0)
> 
> [snip]
> 
> Since the architecture gives you the formula to build these, why do
> you enumerate each and every register encoding? I'd rather see
> something like:
> 
> #define __SYS_BRBINFO(n) sys_reg(2, 1, 8, ((n) & 0xf), (((n) & 0x10)) >> 2)
> #define SYS_BRBINF0_EL1	__SYS_BRBINFO(0)
> [...]
> 
> and something similar for all the new registers that come in packs of
> 32... We already have similar things for AMU, PMU, GIC and co.

Sure, above method seems like a better idea indeed. I will create these
constructs for BRBINF, BRBSRC and BRBTGT based registers set.

> 
> Thanks,
> 
> 	M.
> 
>