From: Sibi Sankar <quic_sibis@quicinc.com>
To: <andersson@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<robh+dt@kernel.org>, <jassisinghbrar@gmail.com>,
<manivannan.sadhasivam@linaro.org>
Cc: <agross@kernel.org>, <linux-arm-msm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<konrad.dybcio@somainline.org>,
Sibi Sankar <quic_sibis@quicinc.com>
Subject: [PATCH 1/2] dt-bindings: mailbox: Add dt binding for QTI CPUCP mailbox controller
Date: Wed, 14 Sep 2022 11:33:05 +0530 [thread overview]
Message-ID: <1663135386-26270-2-git-send-email-quic_sibis@quicinc.com> (raw)
In-Reply-To: <1663135386-26270-1-git-send-email-quic_sibis@quicinc.com>
Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox
controller.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
.../bindings/mailbox/qcom,cpucp-mbox.yaml | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
new file mode 100644
index 000000000000..1f7e1204cda0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
+
+maintainers:
+ - Sibi Sankar <quic_sibis@qti.qualcomm.com>
+
+description:
+ The CPUSS Control Processor (CPUCP) mailbox controller enables communication
+ between AP and CPUCP by acting as a doorbell between them.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sc7280-cpucp-mbox
+ - const: qcom,cpucp-mbox
+
+ reg:
+ items:
+ - description: CPUCP tx register region
+ - description: CPUCP rx register region
+
+ interrupts:
+ maxItems: 1
+
+ "#mbox-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mailbox@17400000 {
+ compatible = "qcom,sc7280-cpucp-mbox", "qcom,cpucp-mbox";
+ reg = <0x0 0x17c00000 0x0 0x10>, <0x0 0x18590300 0x0 0x700>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <0>;
+ };
--
2.7.4
next prev parent reply other threads:[~2022-09-14 6:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 6:03 [PATCH 0/2] Add support for CPUCP mailbox controller Sibi Sankar
2022-09-14 6:03 ` Sibi Sankar [this message]
2022-09-14 11:08 ` [PATCH 1/2] dt-bindings: mailbox: Add dt binding for QTI " Rob Herring
2022-09-15 1:39 ` Sibi Sankar
2022-09-14 6:03 ` [PATCH 2/2] mailbox: Add support " Sibi Sankar
2022-09-14 17:38 ` Trilok Soni
2022-09-15 1:33 ` Sibi Sankar
2022-09-14 17:52 ` Bjorn Andersson
2022-11-03 11:02 ` Sudeep Holla
2022-12-13 14:04 [PATCH 0/2] Add support for " Sibi Sankar
2022-12-13 14:04 ` [PATCH 1/2] dt-bindings: mailbox: Add dt binding for QTI " Sibi Sankar
2022-12-13 14:09 ` Sibi Sankar
2022-12-13 16:51 ` Rob Herring
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