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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT048.mail.protection.outlook.com (10.13.177.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5723.20 via Frontend Transport; Mon, 17 Oct 2022 22:27:37 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 17:27:34 -0500 Subject: [PATCH v7 12/12] Documentation/x86: Update resctrl.rst for new features From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 17 Oct 2022 17:27:34 -0500 Message-ID: <166604565437.5345.14867510739122394750.stgit@bmoger-ubuntu> In-Reply-To: <166604543832.5345.9696970469830919982.stgit@bmoger-ubuntu> References: <166604543832.5345.9696970469830919982.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2022 22:27:37.4968 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b739b5cc-791d-47f0-0aed-08dab08ecbaf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7260 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the documentation for the new features:=0A= 1. Slow Memory Bandwidth allocation (SMBA).=0A= With this feature, the QOS enforcement policies can be applied=0A= to the external slow memory connected to the host. QOS enforcement=0A= is accomplished by assigning a Class Of Service (COS) to a processor=0A= and specifying allocations or limits for that COS for each resource=0A= to be allocated.=0A= =0A= 2. Bandwidth Monitoring Event Configuration (BMEC).=0A= The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes=0A= are set to count all the total and local reads/writes respectively.=0A= With the introduction of slow memory, the two counters are not=0A= enough to count all the different types of memory events. With the=0A= feature BMEC, the users have the option to configure mbm_total_bytes=0A= and mbm_local_bytes to count the specific type of events.=0A= =0A= Also add configuration instructions with examples.=0A= =0A= Signed-off-by: Babu Moger =0A= ---=0A= Documentation/x86/resctrl.rst | 139 +++++++++++++++++++++++++++++++++++++= +++-=0A= 1 file changed, 137 insertions(+), 2 deletions(-)=0A= =0A= diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst= =0A= index 71a531061e4e..d0b4e1a2cb8d 100644=0A= --- a/Documentation/x86/resctrl.rst=0A= +++ b/Documentation/x86/resctrl.rst=0A= @@ -17,14 +17,16 @@ AMD refers to this feature as AMD Platform Quality of S= ervice(AMD QoS).=0A= This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cp= uinfo=0A= flag bits:=0A= =0A= -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=0A= RDT (Resource Director Technology) Allocation "rdt_a"=0A= CAT (Cache Allocation Technology) "cat_l3", "cat_l2"=0A= CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2"=0A= CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc"=0A= MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"=0A= MBA (Memory Bandwidth Allocation) "mba"=0A= -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0A= +SMBA (Slow Memory Bandwidth Allocation) "smba"=0A= +BMEC (Bandwidth Monitoring Event Configuration) "bmec"=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=0A= =0A= To use the feature mount the file system::=0A= =0A= @@ -161,6 +163,79 @@ with the following files:=0A= "mon_features":=0A= Lists the monitoring events if=0A= monitoring is enabled for the resource.=0A= + Example::=0A= +=0A= + # cat /sys/fs/resctrl/info/L3_MON/mon_features=0A= + llc_occupancy=0A= + mbm_total_bytes=0A= + mbm_local_bytes=0A= +=0A= + If the system supports Bandwidth Monitoring Event=0A= + Configuration (BMEC), then the bandwidth events will=0A= + be configurable. The output will be::=0A= +=0A= + # cat /sys/fs/resctrl/info/L3_MON/mon_features=0A= + llc_occupancy=0A= + mbm_total_bytes=0A= + mbm_total_config=0A= + mbm_local_bytes=0A= + mbm_local_config=0A= +=0A= +"mbm_total_config", "mbm_local_config":=0A= + These files contain the current event configuration for the events= =0A= + mbm_total_bytes and mbm_local_bytes, respectively, when the=0A= + Bandwidth Monitoring Event Configuration (BMEC) feature is support= ed.=0A= + The event configuration settings are domain specific and will affe= ct=0A= + all the CPUs in the domain.=0A= +=0A= + Following are the types of events supported:=0A= +=0A= + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= + Bits Description=0A= + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= + 6 Dirty Victims from the QOS domain to all types of memory= =0A= + 5 Reads to slow memory in the non-local NUMA domain=0A= + 4 Reads to slow memory in the local NUMA domain=0A= + 3 Non-temporal writes to non-local NUMA domain=0A= + 2 Non-temporal writes to local NUMA domain=0A= + 1 Reads to memory in the non-local NUMA domain=0A= + 0 Reads to memory in the local NUMA domain=0A= + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= +=0A= + By default, the mbm_total_bytes configuration is set to 0x7f to co= unt=0A= + all the event types and the mbm_local_bytes configuration is set t= o=0A= + 0x15 to count all the local memory events.=0A= +=0A= + Examples:=0A= +=0A= + * To view the current configuration::=0A= + ::=0A= +=0A= + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config=0A= + 0=3D0x7f;1=3D0x7f;2=3D0x7f;3=3D0x7f=0A= +=0A= + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config=0A= + 0=3D0x15;1=3D0x15;3=3D0x15;4=3D0x15=0A= +=0A= + * To change the mbm_total_bytes to count only reads on domain 0,= =0A= + the bits 0, 1, 4 and 5 needs to be set, which is 110011b in bina= ry=0A= + (in hexadecimal 0x33):=0A= + ::=0A= +=0A= + # echo "0=3D0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_con= fig=0A= +=0A= + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config=0A= + 0=3D0x33;1=3D0x7f;2=3D0x7f;3=3D0x7f=0A= +=0A= + * To change the mbm_local_bytes to count all the slow memory reads= =0A= + on domain 1, the bits 4 and 5 needs to be set, which is 110000b= =0A= + in binary (in hexadecimal 0x30):=0A= + ::=0A= +=0A= + # echo "1=3D0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_con= fig=0A= +=0A= + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config=0A= + 0=3D0x15;1=3D0x30;3=3D0x15;4=3D0x15=0A= =0A= "max_threshold_occupancy":=0A= Read/write file provides the largest value (in=0A= @@ -464,6 +539,26 @@ Memory bandwidth domain is L3 cache.=0A= =0A= MB:=3Dbw_MBps0;=3Dbw_MBps1;...=0A= =0A= +Slow Memory bandwidth Allocation (SMBA)=0A= +---------------------------------------=0A= +AMD hardwares support Slow Memory bandwidth Allocation (SMBA) feature.=0A= +Currently, CXL.memory is the only supported "slow" memory device.=0A= +With the support of SMBA, the hardware enables bandwidth allocation=0A= +on the slow memory devices. If there are multiple such devices in the=0A= +system, the throttling logic groups all the slow sources together=0A= +and applies the limit on them as a whole.=0A= +=0A= +The presence of SMBA (with CXL.memory) is independent of slow memory=0A= +devices presence. If there is no such devices on the system, then=0A= +setting the configuring SMBA will have no impact on the performance=0A= +of the system.=0A= +=0A= +The bandwidth domain for slow memory is L3 cache. Its schemata file=0A= +is formatted as:=0A= +::=0A= +=0A= + SMBA:=3Dbandwidth0;=3Dbandwidth1;...=0A= +=0A= Reading/writing the schemata file=0A= ---------------------------------=0A= Reading the schemata file will show the state of all resources=0A= @@ -479,6 +574,46 @@ which you wish to change. E.g.=0A= L3DATA:0=3Dfffff;1=3Dfffff;2=3D3c0;3=3Dfffff=0A= L3CODE:0=3Dfffff;1=3Dfffff;2=3Dfffff;3=3Dfffff=0A= =0A= +Reading/writing the schemata file (on AMD systems)=0A= +--------------------------------------------------=0A= +Reading the schemata file will show the current bandwidth limit on all=0A= +domains. The allocated resources are in multiples of one eighth GB/s.=0A= +When writing to the file, you need to specify what cache id you wish to=0A= +configure the bandwidth limit.=0A= +=0A= +For example, to allocate 2GB/s limit on the first cache id:=0A= +=0A= +::=0A= +=0A= + # cat schemata=0A= + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048=0A= + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff=0A= +=0A= + # echo "MB:1=3D16" > schemata=0A= + # cat schemata=0A= + MB:0=3D2048;1=3D 16;2=3D2048;3=3D2048=0A= + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff=0A= +=0A= +Reading/writing the schemata file (on AMD systems) with SMBA feature=0A= +--------------------------------------------------------------------=0A= +Reading and writing the schemata file is the same as without SMBA in=0A= +above section.=0A= +=0A= +For example, to allocate 8GB/s limit on the first cache id:=0A= +=0A= +::=0A= +=0A= + # cat schemata=0A= + SMBA:0=3D2048;1=3D2048;2=3D2048;3=3D2048=0A= + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048=0A= + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff=0A= +=0A= + # echo "SMBA:1=3D64" > schemata=0A= + # cat schemata=0A= + SMBA:0=3D2048;1=3D 64;2=3D2048;3=3D2048=0A= + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048=0A= + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff=0A= +=0A= Cache Pseudo-Locking=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= CAT enables a user to specify the amount of cache space that an=0A= =0A=