From: "tip-bot2 for Breno Leitao" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
Breno Leitao <leitao@debian.org>,
"Borislav Petkov (AMD)" <bp@alien8.de>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/cpu] x86/bugs: Reset speculation control settings on init
Date: Thu, 12 Jan 2023 10:41:50 -0000 [thread overview]
Message-ID: <167352011025.4906.15940595409237822889.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20221128153148.1129350-1-leitao@debian.org>
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 0125acda7d76b943ca55811df40ed6ec0ecf670f
Gitweb: https://git.kernel.org/tip/0125acda7d76b943ca55811df40ed6ec0ecf670f
Author: Breno Leitao <leitao@debian.org>
AuthorDate: Mon, 28 Nov 2022 07:31:48 -08:00
Committer: Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Thu, 12 Jan 2023 11:37:01 +01:00
x86/bugs: Reset speculation control settings on init
Currently, x86_spec_ctrl_base is read at boot time and speculative bits
are set if Kconfig items are enabled. For example, IBRS is enabled if
CONFIG_CPU_IBRS_ENTRY is configured, etc. These MSR bits are not cleared
if the mitigations are disabled.
This is a problem when kexec-ing a kernel that has the mitigation
disabled from a kernel that has the mitigation enabled. In this case,
the MSR bits are not cleared during the new kernel boot. As a result,
this might have some performance degradation that is hard to pinpoint.
This problem does not happen if the machine is (hard) rebooted because
the bit will be cleared by default.
[ bp: Massage. ]
Suggested-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Breno Leitao <leitao@debian.org>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20221128153148.1129350-1-leitao@debian.org
---
arch/x86/include/asm/msr-index.h | 4 ++++
arch/x86/kernel/cpu/bugs.c | 10 +++++++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 37ff475..cb359d6 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -49,6 +49,10 @@
#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
+/* A mask for bits which the kernel toggles when controlling mitigations */
+#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
+ | SPEC_CTRL_RRSBA_DIS_S)
+
#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 19e1ce0..5f33704 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -145,9 +145,17 @@ void __init check_bugs(void)
* have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
* init code as it is not enumerated and depends on the family.
*/
- if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
+ if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
+ /*
+ * Previously running kernel (kexec), may have some controls
+ * turned ON. Clear them and let the mitigations setup below
+ * rediscover them based on configuration.
+ */
+ x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
+ }
+
/* Select the proper CPU mitigations before patching alternatives: */
spectre_v1_select_mitigation();
spectre_v2_select_mitigation();
prev parent reply other threads:[~2023-01-12 10:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 15:31 [PATCH v3] x86/bugs: Explicitly clear speculative MSR bits Breno Leitao
2023-01-11 12:51 ` Borislav Petkov
2023-01-12 7:00 ` Pawan Gupta
2023-01-12 10:34 ` Borislav Petkov
2023-01-12 10:41 ` tip-bot2 for Breno Leitao [this message]
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