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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT041.mail.protection.outlook.com (10.13.172.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6477.31 via Frontend Transport; Mon, 12 Jun 2023 11:43:03 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Mon, 12 Jun 2023 06:43:02 -0500 Received: from xhdsgoud40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Mon, 12 Jun 2023 06:42:59 -0500 From: Srinivas Goud To: , , , , , , CC: , , , , , Srinivas Goud Subject: [PATCH 0/3] can: xilinx_can: Add ECC feature support Date: Mon, 12 Jun 2023 17:12:54 +0530 Message-ID: <1686570177-2836108-1-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2023 11:43:03.4691 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ff2fd19-ed16-4a3f-ff1f-08db6b3a2e7f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7502 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ECC feature added to Tx and Rx FIFO’s for Xilinx CAN Controller. Part of this feature configuration and counter registers added in Xilinx CAN Controller for 1bit/2bit ECC errors count and reset. Please find more details in PG096 v5.1 document. xlnx,has-ecc is optional property and added to Xilinx CAN Controller node if ECC block enabled in the HW. Driver reports 1bit/2bit ECC errors for FIFO's based on ECC error interrupts and also create debugfs entry for reading all the ECC errors. Srinivas Goud (3): dt-bindings: can: xilinx_can: Add ECC property ‘xlnx,has-ecc’ can: xilinx_can: Add ECC support can: xilinx_can: Add debugfs support for ECC .../devicetree/bindings/net/can/xilinx,can.yaml | 5 + drivers/net/can/xilinx_can.c | 169 ++++++++++++++++++++- 2 files changed, 169 insertions(+), 5 deletions(-) -- 2.1.1