Re: [PATCH] clk: rockchip: Fix initialization of mux_pll_src_4plls_p

[Heiko Stuebner <heiko@sntech.de>]

Am Mittwoch, 12. August 2020, 09:52:32 CEST schrieb Stephen Boyd:
> Quoting Nathan Chancellor (2020-08-09 21:40:20)
> > A new warning in Clang points out that the initialization of
> > mux_pll_src_4plls_p appears incorrect:
> > 
> > ../drivers/clk/rockchip/clk-rk3228.c:140:58: warning: suspicious
> > concatenation of string literals in an array initialization; did you
> > mean to separate the elements with a comma? [-Wstring-concatenation]
> > PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
> >                                                               ^
> >                                                              ,
> > ../drivers/clk/rockchip/clk-rk3228.c:140:48: note: place parentheses
> > around the string literal to silence warning
> > PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
> >                                                     ^
> > 1 warning generated.
> > 
> > Given the name of the variable and the same variable name in rv1108, it
> > seems that this should have been four distinct elements. Fix it up by
> > adding the comma as suggested.
> > 
> > Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
> > Link: https://github.com/ClangBuiltLinux/linux/issues/1123
> > Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
> > ---
> 
> Looks good to me. I can pick it up for clk-fixes if Heiko agrees.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

@Stephen you can pick this up as suggested


Thanks
Heiko