From: Jon Hunter <jonathanh@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thierry Reding <thierry.reding@gmail.com>,
"Peter De Schrijver" <pdeschrijver@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 3/8] clocksource/drivers/tegra: Set and use timer's period
Date: Tue, 18 Jun 2019 17:32:10 +0100 [thread overview]
Message-ID: <16c20c1b-d106-cb1e-6d67-bdd402ecf57f@nvidia.com> (raw)
In-Reply-To: <20190618140358.13148-4-digetx@gmail.com>
On 18/06/2019 15:03, Dmitry Osipenko wrote:
> The of_clk structure has a period field that is set up initially by
> timer_of_clk_init(), that period value need to be adjusted for a case of
> TIMER1-9 that are running at a fixed rate that doesn't match the clock's
> rate. Note that the period value is currently used only by some of the
> clocksource drivers internally and hence this is just a minor cleanup
> change that doesn't fix anything.
>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> drivers/clocksource/timer-tegra.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
> index ff5a4ccb5d52..e6221e070499 100644
> --- a/drivers/clocksource/timer-tegra.c
> +++ b/drivers/clocksource/timer-tegra.c
> @@ -71,9 +71,9 @@ static int tegra_timer_shutdown(struct clock_event_device *evt)
> static int tegra_timer_set_periodic(struct clock_event_device *evt)
> {
> void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> + unsigned long period = timer_of_period(to_timer_of(evt));
>
> - writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER |
> - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
> + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
> reg_base + TIMER_PTV);
>
> return 0;
> @@ -297,6 +297,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
> cpu_to->clkevt.rating = rating;
> cpu_to->clkevt.cpumask = cpumask_of(cpu);
> cpu_to->of_base.base = timer_reg_base + base;
> + cpu_to->of_clk.period = rate / HZ;
> cpu_to->of_clk.rate = rate;
>
> irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
next prev parent reply other threads:[~2019-06-18 16:32 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-18 14:03 [PATCH v3 0/8] Few more cleanups for tegra-timer Dmitry Osipenko
2019-06-18 14:03 ` [PATCH v3 1/8] clocksource/drivers/tegra: Restore timer rate on Tegra210 Dmitry Osipenko
2019-06-19 8:17 ` Thierry Reding
2019-06-18 14:03 ` [PATCH v3 2/8] clocksource/drivers/tegra: Remove duplicated use of per_cpu_ptr Dmitry Osipenko
2019-06-19 8:18 ` Thierry Reding
2019-06-18 14:03 ` [PATCH v3 3/8] clocksource/drivers/tegra: Set and use timer's period Dmitry Osipenko
2019-06-18 16:32 ` Jon Hunter [this message]
2019-06-19 0:41 ` Dmitry Osipenko
2019-06-19 8:18 ` Thierry Reding
2019-06-18 14:03 ` [PATCH v3 4/8] clocksource/drivers/tegra: Drop unneeded typecasting in one place Dmitry Osipenko
2019-06-19 8:18 ` Thierry Reding
2019-06-18 14:03 ` [PATCH v3 5/8] clocksource/drivers/tegra: Add verbose definition for 1MHz constant Dmitry Osipenko
2019-06-19 8:18 ` Thierry Reding
2019-06-18 14:03 ` [PATCH v3 6/8] clocksource/drivers/tegra: Restore base address before cleanup Dmitry Osipenko
2019-06-18 17:51 ` Jon Hunter
2019-06-19 8:18 ` Thierry Reding
2019-06-18 14:03 ` [PATCH v3 7/8] clocksource/drivers/tegra: Cycles can't be 0 Dmitry Osipenko
2019-06-18 17:51 ` Jon Hunter
2019-06-19 8:19 ` Thierry Reding
2019-06-20 21:59 ` Dmitry Osipenko
2019-06-18 14:03 ` [PATCH v3 8/8] clocksource/drivers/tegra: Set up maximum-ticks limit properly Dmitry Osipenko
2019-06-18 17:52 ` Jon Hunter
2019-06-19 8:19 ` Thierry Reding
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