From: David Laight <David.Laight@ACULAB.COM>
To: 'Koba Ko' <koba.ko@canonical.com>,
Heiner Kallweit <hkallweit1@gmail.com>
Cc: "David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH] r8169: introduce polling method for link change
Date: Mon, 7 Jun 2021 12:32:29 +0000 [thread overview]
Message-ID: <16f24c21776a4772ac41e6d3e0a9150c@AcuMS.aculab.com> (raw)
In-Reply-To: <CAJB-X+UDRK5-fKEGc+PS+_02HePmb34Pw_+tMyNr_iGGeE+jbQ@mail.gmail.com>
From: Koba Ko
> Sent: 07 June 2021 05:35
...
> After consulting with REALTEK, I can identify RTL8106e by PCI_VENDOR
> REALTEK, DEVICE 0x8136, Revision 0x7.
> I would like to make PHY_POLL as default for RTL8106E on V2.
> because there's no side effects besides the cpu usage rate would be a
> little higher,
> How do you think?
If reading the PHY registers involves a software bit-bang
of an MII register (rather than, say, a sleep for interrupt
while the MAC unit does the bit-bang) then you can clobber
interrupt latency because of all the time spent spinning.
While this is less of a problem on multi-cpu systems I have
seen it result in ethernet packet loss on old systems.
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2021-06-07 12:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-03 2:54 [PATCH] r8169: introduce polling method for link change Koba Ko
2021-06-03 9:59 ` Heiner Kallweit
2021-06-04 7:22 ` Koba Ko
2021-06-04 8:23 ` Heiner Kallweit
2021-06-04 9:08 ` Koba Ko
2021-06-04 11:59 ` Heiner Kallweit
2021-06-07 4:34 ` Koba Ko
2021-06-07 10:43 ` Heiner Kallweit
2021-06-07 11:09 ` Koba Ko
2021-06-07 12:32 ` David Laight [this message]
2021-06-07 12:49 ` Andrew Lunn
2021-06-07 13:17 ` David Laight
2021-06-03 21:33 ` kernel test robot
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