From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: Dmitriy Cherkasov <dmitriy@oss-tech.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
peterz@infradead.org, tglx@linutronix.de, jason@lakedaemon.net,
marc.zyngier@arm.com, Arnd Bergmann <arnd@arndb.de>
Cc: yamada.masahiro@socionext.com, mmarek@suse.com,
albert@sifive.com, will.deacon@arm.com, boqun.feng@gmail.com,
oleg@redhat.com, mingo@redhat.com, gregkh@linuxfoundation.org,
jslaby@suse.com, davem@davemloft.net, mchehab@kernel.org,
hverkuil@xs4all.nl, rdunlap@infradead.org,
viro@zeniv.linux.org.uk, mhiramat@kernel.org, fweisbec@gmail.com,
mcgrof@kernel.org, dledford@redhat.com,
bart.vanassche@sandisk.com, sstabellini@kernel.org,
mpe@ellerman.id.au, rmk+kernel@armlinux.org.uk,
paul.gortmaker@windriver.com, nicolas.dichtel@6wind.com,
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schwidefsky@de.ibm.com, geert@linux-m68k.org,
akpm@linux-foundation.org, andriy.shevchenko@linux.intel.com,
jiri@mellanox.com, vgupta@synopsys.com, airlied@redhat.com,
jk@ozlabs.org, chris@chris-wilson.co.uk, Jason@zx2c4.com,
paulmck@linux.vnet.ibm.com, ncardwell@google.com,
linux-kernel@vger.kernel.org, linux-kbuild@vger.kernel.org,
patches@groups.riscv.org
Subject: Re: [PATCH v8 10/18] RISC-V: Init and Halt Code
Date: Sat, 16 Sep 2017 15:28:28 +0200 [thread overview]
Message-ID: <173e7b29-7a1d-ebe9-cdad-9ff90d3c485f@linaro.org> (raw)
In-Reply-To: <98372099-25e1-f340-f204-8e9a10d659f9@oss-tech.org>
On 16/09/2017 08:23, Dmitriy Cherkasov wrote:
> On 09/13/2017 11:15 AM, Daniel Lezcano wrote:
>>
>> All this code must go in the timer side and use the TIMER_OF_DECLARE
>> macro with the proper wrappers.
>
> Hi, thanks for the feedback.
>
> Agreed. I'll clean this up.
>
>>
>> Where is the request_per_cpu_interrupt()?
>>
>> What is this riscv_timer_interrupt() signature?
>
> This arch defines a separate exception type for local timer interrupts.
> Currently the interrupt controller driver checks the trap cause
> register, determines that it's a timer, and calls the handler directly.
> To make this go through the interrupt subsystem, this driver would need
> to be reworked.
>
>>
>> Where is get_cycles64() ?
>
> This is in asm/timex.h. Should this be split into a separate asm header
> ala arm64?
No, it is fine but may be it is get_cycles(), no get_cycles64(), right?
>> The timer driver should be self-contained and not spread across
>> different places, it is very difficult to review it.
>>
>> [ ... ]
>>
>
> Agreed, thanks again for reviewing it anyway :)
Ok, thanks.
-- Daniel
--
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next prev parent reply other threads:[~2017-09-16 13:28 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-12 21:56 RISC-V Linux Port v8 Palmer Dabbelt
2017-09-12 21:56 ` [PATCH v8 01/18] MAINTAINERS: Add RISC-V Palmer Dabbelt
2017-09-13 14:39 ` Joe Perches
2017-09-13 15:55 ` Palmer Dabbelt
2017-09-12 21:56 ` [PATCH v8 02/18] lib: Add shared copies of some GCC library routines Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 03/18] dt-bindings: interrupt-controller: RISC-V local interrupt controller docs Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 04/18] dt-bindings: interrupt-controller: RISC-V PLIC documentation Palmer Dabbelt
2017-09-15 14:34 ` Rob Herring
2017-09-15 16:24 ` Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 05/18] dt-bindings: RISC-V CPU Bindings Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 06/18] clocksource: New RISC-V SBI timer driver Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 07/18] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 08/18] irqchip: New RISC-V PLIC Driver Palmer Dabbelt
2017-09-14 11:04 ` [patches] " Jonathan Neuschäfer
2017-09-12 21:57 ` [PATCH v8 09/18] tty: New RISC-V SBI console driver Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 10/18] RISC-V: Init and Halt Code Palmer Dabbelt
2017-09-13 18:15 ` Daniel Lezcano
2017-09-16 6:23 ` Dmitriy Cherkasov
2017-09-16 13:28 ` Daniel Lezcano [this message]
2017-09-16 21:38 ` Dmitriy Cherkasov
2017-09-12 21:57 ` [PATCH v8 11/18] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 12/18] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 13/18] RISC-V: ELF and module implementation Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 14/18] RISC-V: Task implementation Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 15/18] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 16/18] RISC-V: Paging and MMU Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 17/18] RISC-V: User-facing API Palmer Dabbelt
2017-09-12 21:57 ` [PATCH v8 18/18] RISC-V: Build Infrastructure Palmer Dabbelt
2017-09-20 9:41 ` Masahiro Yamada
[not found] <CAK8P3a3fxTkRjXfHfW=8OoME0DNyU=DKNcaRPWwnaKqF-w1ccg@mail.gmail.com>
2017-09-13 17:01 ` [PATCH v8 10/18] RISC-V: Init and Halt Code Palmer Dabbelt
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