From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDB94C433DF for ; Mon, 6 Jul 2020 15:23:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A287420715 for ; Mon, 6 Jul 2020 15:23:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="K8CReBT+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729496AbgGFPXD (ORCPT ); Mon, 6 Jul 2020 11:23:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729267AbgGFPXD (ORCPT ); Mon, 6 Jul 2020 11:23:03 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B846BC061755; Mon, 6 Jul 2020 08:23:02 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id a6so41431091wrm.4; Mon, 06 Jul 2020 08:23:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:autocrypt:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=dAJu+62mabBIMXiEr5XrQ+JflLjgU2YNzNlqYsdRIdw=; b=K8CReBT+hyRzi4AsJJm6IxI7oN9PlZrJh6k8iEhCwql04KOGd4J2tgcpLyh5BTFsGW bho7i32ynNEfPaL0crkUZCX4DQmFTyKJP+kYISPzqF4b1I+n+EZrDAt1edbXy0EY3yF9 fFyg1iQ//e1zIWTLI4wxPo1wHhyzri29DvFgrM5aNgCu916TbMXNHSZhsoYzuDhVFQJX HOsKc2Owgldz7gqIAJ2/o+LILhwcOcowXLaJCs7D0KK+gmzt/qcK824IGbMXLuZn4ou3 F0eN8omc7ftHuHT8Y8K1cbVeZ1bzksNbj3NUHBuIwAbHJQALPS93Mv6iDhwJja2h+qI9 eONw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:autocrypt :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=dAJu+62mabBIMXiEr5XrQ+JflLjgU2YNzNlqYsdRIdw=; b=Di/kdE8GhGWbEdt3IQhNX05KtFMXrcceMYwDcaQ32ynrCetscq5ZixNVj+Eued8RzK eOSTqKylrcdgPTPfUy5k7rLC4IH+uRjS5GShJxC1csP5NLYEGkmgo6fEeD5iD5PadT7H et/Q6Y/DFOAxctTXHREhYhy8G+y14Jmzx4sj7ctb8slJRr9lXA39IycaCrzic+wcy0GC xxAS/0jQQJ2WdZ9+l77UIUhmbLGEk+am/xJWnnzN7t/E7goj+bekocuDr83dP+wX6kHB 1HI4spLy5wuXkQb6Gm0cQqEyCAPEt9VO82BpFIE7fPxPEuelgd49kmGB9Zkf76owCJof p+yw== X-Gm-Message-State: AOAM533dP4KVUAWggMuA0MbIxkxWoMYo5F/yb4eUAq+QvOZNB5sTRLsw ulOtBCVRdO7o1Svw8fJ8tfPW9EnxXcQ= X-Google-Smtp-Source: ABdhPJyzc/vfsGEPu9lm4bfH2I099ZfJD0Tr/1/wWc2+CcLPAElvGmIqHi6ER7htDlkPCnAwkOPtjA== X-Received: by 2002:adf:f452:: with SMTP id f18mr48964355wrp.78.1594048981485; Mon, 06 Jul 2020 08:23:01 -0700 (PDT) Received: from ziggy.stardust (81.172.57.81.dyn.user.ono.com. [81.172.57.81]) by smtp.gmail.com with ESMTPSA id g82sm22104920wma.37.2020.07.06.08.23.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jul 2020 08:23:00 -0700 (PDT) Subject: Re: [PATCH v6 09/10] iommu/mediatek: Modify MMU_CTRL register setting To: Chao Hao , Joerg Roedel , Rob Herring Cc: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wsd_upstream@mediatek.com, FY Yang , Yong Wu , TH Yang References: <20200703044127.27438-1-chao.hao@mediatek.com> <20200703044127.27438-10-chao.hao@mediatek.com> From: Matthias Brugger Autocrypt: addr=matthias.bgg@gmail.com; prefer-encrypt=mutual; keydata= mQINBFP1zgUBEAC21D6hk7//0kOmsUrE3eZ55kjc9DmFPKIz6l4NggqwQjBNRHIMh04BbCMY fL3eT7ZsYV5nur7zctmJ+vbszoOASXUpfq8M+S5hU2w7sBaVk5rpH9yW8CUWz2+ZpQXPJcFa OhLZuSKB1F5JcvLbETRjNzNU7B3TdS2+zkgQQdEyt7Ij2HXGLJ2w+yG2GuR9/iyCJRf10Okq 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/BoVz9CZTMEVAZVzbRKyYCLUf1wLhcHzugTiONz9fWMBLLskKvq7m1tlr61mNgY9nVwwClMU uE7i1H9r/2/UXLd+pY82zcXhFrfmKuCDmOkB5xPsOMVQJH8I0/lbqfLAqfsxSb/X1VKaP243 jzi+DzD9cvj2K6eD5j5kcKJJQactXqfJvF1Eb+OnxlB1BCLE8D1rNkPO5O742Mq3MgDmq19l +abzEL6QDAAxn9md8KwrA3RtucNh87cHlDXfUBKa7SRvBjTczDg+HEPNk2u3hrz1j3l2rliQ y1UfYx7Vk/TrdwUIJgKS8QAr8Lw9WuvY2hSqL9vEjx8VAkPWNWPwrQ== Message-ID: <17fe4a7b-8732-7bad-6aaa-1a20a4921c7b@gmail.com> Date: Mon, 6 Jul 2020 17:22:59 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20200703044127.27438-10-chao.hao@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/07/2020 06:41, Chao Hao wrote: > The MMU_CTRL register of MT8173 is different from other SoCs. > The in_order_wr_en is bit[9] which is zero by default. > Other SoCs have the vitcim_tlb_en feature mapped to bit[12]. > This bit is set to one by default. We need to preserve the bit > when setting F_MMU_TF_PROT_TO_PROGRAM_ADDR as otherwise the > bit will be cleared and IOMMU performance will drop. > > Cc: Matthias Brugger > Cc: Yong Wu > Signed-off-by: Chao Hao Reviewed-by: Matthias Brugger > --- > drivers/iommu/mtk_iommu.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index e71003037ffa..a816030d00f1 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -555,11 +555,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > return ret; > } > > - if (data->plat_data->m4u_plat == M4U_MT8173) > + if (data->plat_data->m4u_plat == M4U_MT8173) { > regval = F_MMU_PREFETCH_RT_REPLACE_MOD | > F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; > - else > - regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR; > + } else { > + regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); > + regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; > + } > writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); > > regval = F_L2_MULIT_HIT_EN | >