Re: DP83867 ethernet PHY regression

From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: Francesco Dolcini <francesco@dolcini.it>, Andrew Lunn <andrew@lunn.ch>
Cc: Praneeth Bajjuri <praneeth@ti.com>, Geet Modi <geet.modi@ti.com>,
	"David S. Miller" <davem@davemloft.net>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	Grygorii Strashko <grygorii.strashko@ti.com>,
	Dan Murphy <dmurphy@ti.com>
Subject: Re: DP83867 ethernet PHY regression
Date: Thu, 25 May 2023 10:18:49 +0200	[thread overview]
Message-ID: <1857120.tdWV9SEqCh@steina-w> (raw)
In-Reply-To: <07037ce6-8d1c-4a1d-9fdd-2cd9e68c4594@lunn.ch>

Hi,

Am Montag, 22. Mai 2023, 18:15:56 CEST schrieb Andrew Lunn:
> On Mon, May 22, 2023 at 05:35:33PM +0200, Francesco Dolcini wrote:
> > On Mon, May 22, 2023 at 05:15:56PM +0200, Andrew Lunn wrote:
> > > On Mon, May 22, 2023 at 04:58:46PM +0200, Francesco Dolcini wrote:
> > > > Hello all,
> > > > commit da9ef50f545f ("net: phy: dp83867: perform soft reset and retain
> > > > established link") introduces a regression on my TI AM62 based board.
> > > > 
> > > > I have a working DTS with Linux TI 5.10 downstream kernel branch,
> > > > while
> > > > testing the DTS with v6.4-rc in preparation of sending it to the
> > > > mailing
> > > > list I noticed that ethernet is working only on a cold poweron.
> > > 
> > > Do you have more details about how it does not work.
> > > 
> > > Please could you use:
> > > 
> > > mii-tool -vvv ethX
> > 
> > please see the attached files:
> > 
> > working_da9ef50f545f_reverted.txt
> > 
> >   this is on a v6.4-rc, with da9ef50f545f reverted
> > 
> > not_working.txt
> > 
> >   v6.4-rc not working
> > 
> > working.txt
> > 
> >   v6.4-rc working
> > 
> > It looks like, even on cold boot, it's not working in a reliable way.
> > Not sure the exact difference when it's working and when it's not.
> > 
> > Using SIOCGMIIPHY=0x8947
> > eth0: negotiated 1000baseT-FD flow-control, link ok
> > 
> >   registers for MII PHY 0:
> >     1140 796d 2000 a231 05e1 c5e1 006f 2001
> >     5806 0200 3800 0000 0000 4007 0000 3000
> >     5048 ac02 ec10 0004 2bc7 0000 0000 0040
> >     6150 4444 0002 0000 0000 0000 0282 0000
> >     
> >     1140 796d 2000 a231 05e1 c5e1 006d 2001
> >     5806 0200 3800 0000 0000 4007 0000 3000
> >     5048 af02 ec10 0000 2bc7 0000 0000 0040
> >     6150 4444 0002 0000 0000 0000 0282 0000
> 
> Register  6: 006f vs 006d
> Register 17: ac02 vs 1f02
> Register 19: 0004 vs 0000
> 
> Register 6 is MII_EXPANSION. Bit 1 is
> 
> #define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
> 
> So that is probably not relevant here.
> 
> Register 17 is MII_DP83867_PHYSTS, and bits 8 and 9 are not documented
> in the driver. Do you have the datasheet?

Bit 8 & 9 is indicating the MDI/MDIX resolution status for lines A/B and C/D.

> Register 19 is MII_DP83867_ISR. The interrupt bits are not documented
> in the driver either.

I guess that's the more interesting part. Bit 2 (0x4) indicates a xGMII 
(RGMII/SGMII) error interrupt.

Best regards,
Alexander

> This driver also uses C45 registers, which are not shown here. At some
> point, we might need to look at those. But first it would be good to
> understand what these differences mean.
> 
> 	Andrew

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