From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A28A4C2BB41 for ; Tue, 16 Aug 2022 10:36:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234756AbiHPKgJ (ORCPT ); Tue, 16 Aug 2022 06:36:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234864AbiHPKfb (ORCPT ); Tue, 16 Aug 2022 06:35:31 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 073F2D130; Tue, 16 Aug 2022 02:11:43 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oNsbl-0002oW-HD; Tue, 16 Aug 2022 11:11:33 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland , Samuel Holland Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Date: Tue, 16 Aug 2022 11:11:32 +0200 Message-ID: <1861548.g5d078U9FE@diego> In-Reply-To: <20220815050815.22340-7-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> <20220815050815.22340-7-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Montag, 15. August 2022, 07:08:09 CEST schrieb Samuel Holland: > D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as > one HiFi 4 DSP. The SoC is based on a design that additionally contained > a pair of Cortex A7's. For that reason, some peripherals are duplicated. > > This devicetree includes all of the peripherals that already have a > documented binding. > > Signed-off-by: Samuel Holland Tested-by: Heiko Stuebner