* [PATCH 1/9] drm/bridge: move ANA78xx driver to analogix subdirectory
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 8:47 ` Laurent Pinchart
2018-10-18 7:33 ` [PATCH 2/9] drm/bridge: split some definitions of ANX78xx to dedicated headers Icenowy Zheng
` (9 subsequent siblings)
10 siblings, 1 reply; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-sunxi, Icenowy Zheng
As ANA78xx chips are designed and produced by Analogix Semiconductor,
Inc, move their driver codes into analogix subdirectory.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/gpu/drm/bridge/Kconfig | 10 ----------
drivers/gpu/drm/bridge/Makefile | 4 ++--
drivers/gpu/drm/bridge/analogix/Kconfig | 10 ++++++++++
drivers/gpu/drm/bridge/analogix/Makefile | 1 +
.../gpu/drm/bridge/{ => analogix}/analogix-anx78xx.c | 0
.../gpu/drm/bridge/{ => analogix}/analogix-anx78xx.h | 0
6 files changed, 13 insertions(+), 12 deletions(-)
rename drivers/gpu/drm/bridge/{ => analogix}/analogix-anx78xx.c (100%)
rename drivers/gpu/drm/bridge/{ => analogix}/analogix-anx78xx.h (100%)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 9eeb8ef0b174..8a7ffb3256d8 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -15,16 +15,6 @@ config DRM_PANEL_BRIDGE
menu "Display Interface Bridges"
depends on DRM && DRM_BRIDGE
-config DRM_ANALOGIX_ANX78XX
- tristate "Analogix ANX78XX bridge"
- select DRM_KMS_HELPER
- select REGMAP_I2C
- ---help---
- ANX78XX is an ultra-low Full-HD SlimPort transmitter
- designed for portable devices. The ANX78XX transforms
- the HDMI output of an application processor to MyDP
- or DisplayPort.
-
config DRM_CDNS_DSI
tristate "Cadence DPI/DSI bridge"
select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 4934fcf5a6f8..a6c7dd7727ea 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
@@ -12,8 +11,9 @@ obj-$(CONFIG_DRM_SII9234) += sii9234.o
obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o
obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o
obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
-obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+
+obj-y += analogix/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
index 80f286fa3a69..27b37aa2ea77 100644
--- a/drivers/gpu/drm/bridge/analogix/Kconfig
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -1,3 +1,13 @@
config DRM_ANALOGIX_DP
tristate
depends on DRM
+
+config DRM_ANALOGIX_ANX78XX
+ tristate "Analogix ANX78XX bridge"
+ select DRM_KMS_HELPER
+ select REGMAP_I2C
+ ---help---
+ ANX78XX is an ultra-low Full-HD SlimPort transmitter
+ designed for portable devices. The ANX78XX transforms
+ the HDMI output of an application processor to MyDP
+ or DisplayPort.
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
index cd4010ba6890..eb41be845055 100644
--- a/drivers/gpu/drm/bridge/analogix/Makefile
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -1,2 +1,3 @@
analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
+obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
similarity index 100%
rename from drivers/gpu/drm/bridge/analogix-anx78xx.c
rename to drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.h b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h
similarity index 100%
rename from drivers/gpu/drm/bridge/analogix-anx78xx.h
rename to drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 1/9] drm/bridge: move ANA78xx driver to analogix subdirectory
2018-10-18 7:33 ` [PATCH 1/9] drm/bridge: move ANA78xx driver to analogix subdirectory Icenowy Zheng
@ 2018-10-18 8:47 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2018-10-18 8:47 UTC (permalink / raw)
To: Icenowy Zheng
Cc: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-sunxi
Hi Icenowy,
Thank you for the patch.
On Thursday, 18 October 2018 10:33:19 EEST Icenowy Zheng wrote:
> As ANA78xx chips are designed and produced by Analogix Semiconductor,
> Inc, move their driver codes into analogix subdirectory.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> drivers/gpu/drm/bridge/Kconfig | 10 ----------
> drivers/gpu/drm/bridge/Makefile | 4 ++--
> drivers/gpu/drm/bridge/analogix/Kconfig | 10 ++++++++++
> drivers/gpu/drm/bridge/analogix/Makefile | 1 +
> .../gpu/drm/bridge/{ => analogix}/analogix-anx78xx.c | 0
> .../gpu/drm/bridge/{ => analogix}/analogix-anx78xx.h | 0
> 6 files changed, 13 insertions(+), 12 deletions(-)
> rename drivers/gpu/drm/bridge/{ => analogix}/analogix-anx78xx.c (100%)
> rename drivers/gpu/drm/bridge/{ => analogix}/analogix-anx78xx.h (100%)
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 9eeb8ef0b174..8a7ffb3256d8 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -15,16 +15,6 @@ config DRM_PANEL_BRIDGE
> menu "Display Interface Bridges"
> depends on DRM && DRM_BRIDGE
>
> -config DRM_ANALOGIX_ANX78XX
> - tristate "Analogix ANX78XX bridge"
> - select DRM_KMS_HELPER
> - select REGMAP_I2C
> - ---help---
> - ANX78XX is an ultra-low Full-HD SlimPort transmitter
> - designed for portable devices. The ANX78XX transforms
> - the HDMI output of an application processor to MyDP
> - or DisplayPort.
> -
> config DRM_CDNS_DSI
> tristate "Cadence DPI/DSI bridge"
> select DRM_KMS_HELPER
> diff --git a/drivers/gpu/drm/bridge/Makefile
> b/drivers/gpu/drm/bridge/Makefile index 4934fcf5a6f8..a6c7dd7727ea 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -1,5 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
> obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
> obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
> @@ -12,8 +11,9 @@ obj-$(CONFIG_DRM_SII9234) += sii9234.o
> obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o
> obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o
> obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
> -obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
> obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
> obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
> obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
> +
> +obj-y += analogix/
> obj-y += synopsys/
> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig
> b/drivers/gpu/drm/bridge/analogix/Kconfig index 80f286fa3a69..27b37aa2ea77
> 100644
> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
> @@ -1,3 +1,13 @@
> config DRM_ANALOGIX_DP
> tristate
> depends on DRM
> +
> +config DRM_ANALOGIX_ANX78XX
> + tristate "Analogix ANX78XX bridge"
> + select DRM_KMS_HELPER
> + select REGMAP_I2C
> + ---help---
> + ANX78XX is an ultra-low Full-HD SlimPort transmitter
> + designed for portable devices. The ANX78XX transforms
> + the HDMI output of an application processor to MyDP
> + or DisplayPort.
> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile
> b/drivers/gpu/drm/bridge/analogix/Makefile index cd4010ba6890..eb41be845055
> 100644
> --- a/drivers/gpu/drm/bridge/analogix/Makefile
> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
> @@ -1,2 +1,3 @@
> analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o
> obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
> +obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
This makes sense to me. I would have tried to keep the Kconfig and Makefile
entries alphabetically sorted, but that's not a big deal. With or without the
sorting,
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c
> b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c similarity index 100%
> rename from drivers/gpu/drm/bridge/analogix-anx78xx.c
> rename to drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.h
> b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h similarity index 100%
> rename from drivers/gpu/drm/bridge/analogix-anx78xx.h
> rename to drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 2/9] drm/bridge: split some definitions of ANX78xx to dedicated headers
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
2018-10-18 7:33 ` [PATCH 1/9] drm/bridge: move ANA78xx driver to analogix subdirectory Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 7:33 ` [PATCH 3/9] drm/bridge: extract some Analogix I2C DP common code Icenowy Zheng
` (8 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-sunxi, Icenowy Zheng
Some definitions currently in analogix-anx78xx.h are not restricted to
the ANX78xx series, but also applicable to other DisplayPort
transmitters by Analogix.
Split out them to dedicated headers, and make analogix-anx78xx.h include
them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../drm/bridge/analogix/analogix-anx78xx.h | 464 +-----------------
.../drm/bridge/analogix/analogix-i2c-dptx.h | 248 ++++++++++
.../bridge/analogix/analogix-i2c-txcommon.h | 237 +++++++++
3 files changed, 490 insertions(+), 459 deletions(-)
create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h
index 38753c870137..8aa1eca306d3 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h
@@ -15,9 +15,12 @@
#ifndef __ANX78xx_H
#define __ANX78xx_H
-#define TX_P0 0x70
+#include "analogix-i2c-dptx.h"
+#include "analogix-i2c-txcommon.h"
+
+#define TX_P0 ANALOGIX_I2C_DPTX
#define TX_P1 0x7a
-#define TX_P2 0x72
+#define TX_P2 ANALOGIX_I2C_TXCOMMON
#define RX_P0 0x7e
#define RX_P1 0x80
@@ -225,463 +228,6 @@
#define SP_CLEAR_AVMUTE BIT(4)
#define SP_SET_AVMUTE BIT(0)
-/***************************************************************/
-/* Register definition of device address 0x70 */
-/***************************************************************/
-
-/* HDCP Status Register */
-#define SP_TX_HDCP_STATUS_REG 0x00
-#define SP_AUTH_FAIL BIT(5)
-#define SP_AUTHEN_PASS BIT(1)
-
-/* HDCP Control Register 0 */
-#define SP_HDCP_CTRL0_REG 0x01
-#define SP_RX_REPEATER BIT(6)
-#define SP_RE_AUTH BIT(5)
-#define SP_SW_AUTH_OK BIT(4)
-#define SP_HARD_AUTH_EN BIT(3)
-#define SP_HDCP_ENC_EN BIT(2)
-#define SP_BKSV_SRM_PASS BIT(1)
-#define SP_KSVLIST_VLD BIT(0)
-/* HDCP Function Enabled */
-#define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
-/* HDCP Receiver BSTATUS Register 0 */
-#define SP_HDCP_RX_BSTATUS0_REG 0x1b
-/* HDCP Receiver BSTATUS Register 1 */
-#define SP_HDCP_RX_BSTATUS1_REG 0x1c
-
-/* HDCP Embedded "Blue Screen" Content Registers */
-#define SP_HDCP_VID0_BLUE_SCREEN_REG 0x2c
-#define SP_HDCP_VID1_BLUE_SCREEN_REG 0x2d
-#define SP_HDCP_VID2_BLUE_SCREEN_REG 0x2e
-
-/* HDCP Wait R0 Timing Register */
-#define SP_HDCP_WAIT_R0_TIME_REG 0x40
-
-/* HDCP Link Integrity Check Timer Register */
-#define SP_HDCP_LINK_CHECK_TIMER_REG 0x41
-
-/* HDCP Repeater Ready Wait Timer Register */
-#define SP_HDCP_RPTR_RDY_WAIT_TIME_REG 0x42
-
-/* HDCP Auto Timer Register */
-#define SP_HDCP_AUTO_TIMER_REG 0x51
-
-/* HDCP Key Status Register */
-#define SP_HDCP_KEY_STATUS_REG 0x5e
-
-/* HDCP Key Command Register */
-#define SP_HDCP_KEY_COMMAND_REG 0x5f
-#define SP_DISABLE_SYNC_HDCP BIT(2)
-
-/* OTP Memory Key Protection Registers */
-#define SP_OTP_KEY_PROTECT1_REG 0x60
-#define SP_OTP_KEY_PROTECT2_REG 0x61
-#define SP_OTP_KEY_PROTECT3_REG 0x62
-#define SP_OTP_PSW1 0xa2
-#define SP_OTP_PSW2 0x7e
-#define SP_OTP_PSW3 0xc6
-
-/* DP System Control Registers */
-#define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1)
-/* Bits for DP System Control Register 2 */
-#define SP_CHA_STA BIT(2)
-/* Bits for DP System Control Register 3 */
-#define SP_HPD_STATUS BIT(6)
-#define SP_STRM_VALID BIT(2)
-/* Bits for DP System Control Register 4 */
-#define SP_ENHANCED_MODE BIT(3)
-
-/* DP Video Control Register */
-#define SP_DP_VIDEO_CTRL_REG 0x84
-#define SP_COLOR_F_MASK 0x06
-#define SP_COLOR_F_SHIFT 1
-#define SP_BPC_MASK 0xe0
-#define SP_BPC_SHIFT 5
-# define SP_BPC_6BITS 0x00
-# define SP_BPC_8BITS 0x01
-# define SP_BPC_10BITS 0x02
-# define SP_BPC_12BITS 0x03
-
-/* DP Audio Control Register */
-#define SP_DP_AUDIO_CTRL_REG 0x87
-#define SP_AUD_EN BIT(0)
-
-/* 10us Pulse Generate Timer Registers */
-#define SP_I2C_GEN_10US_TIMER0_REG 0x88
-#define SP_I2C_GEN_10US_TIMER1_REG 0x89
-
-/* Packet Send Control Register */
-#define SP_PACKET_SEND_CTRL_REG 0x90
-#define SP_AUD_IF_UP BIT(7)
-#define SP_AVI_IF_UD BIT(6)
-#define SP_MPEG_IF_UD BIT(5)
-#define SP_SPD_IF_UD BIT(4)
-#define SP_AUD_IF_EN BIT(3)
-#define SP_AVI_IF_EN BIT(2)
-#define SP_MPEG_IF_EN BIT(1)
-#define SP_SPD_IF_EN BIT(0)
-
-/* DP HDCP Control Register */
-#define SP_DP_HDCP_CTRL_REG 0x92
-#define SP_AUTO_EN BIT(7)
-#define SP_AUTO_START BIT(5)
-#define SP_LINK_POLLING BIT(1)
-
-/* DP Main Link Bandwidth Setting Register */
-#define SP_DP_MAIN_LINK_BW_SET_REG 0xa0
-#define SP_LINK_BW_SET_MASK 0x1f
-#define SP_INITIAL_SLIM_M_AUD_SEL BIT(5)
-
-/* DP Training Pattern Set Register */
-#define SP_DP_TRAINING_PATTERN_SET_REG 0xa2
-
-/* DP Lane 0 Link Training Control Register */
-#define SP_DP_LANE0_LT_CTRL_REG 0xa3
-#define SP_TX_SW_SET_MASK 0x1b
-#define SP_MAX_PRE_REACH BIT(5)
-#define SP_MAX_DRIVE_REACH BIT(4)
-#define SP_PRE_EMP_LEVEL1 BIT(3)
-#define SP_DRVIE_CURRENT_LEVEL1 BIT(0)
-
-/* DP Link Training Control Register */
-#define SP_DP_LT_CTRL_REG 0xa8
-#define SP_LT_ERROR_TYPE_MASK 0x70
-# define SP_LT_NO_ERROR 0x00
-# define SP_LT_AUX_WRITE_ERROR 0x01
-# define SP_LT_MAX_DRIVE_REACHED 0x02
-# define SP_LT_WRONG_LANE_COUNT_SET 0x03
-# define SP_LT_LOOP_SAME_5_TIME 0x04
-# define SP_LT_CR_FAIL_IN_EQ 0x05
-# define SP_LT_EQ_LOOP_5_TIME 0x06
-#define SP_LT_EN BIT(0)
-
-/* DP CEP Training Control Registers */
-#define SP_DP_CEP_TRAINING_CTRL0_REG 0xa9
-#define SP_DP_CEP_TRAINING_CTRL1_REG 0xaa
-
-/* DP Debug Register 1 */
-#define SP_DP_DEBUG1_REG 0xb0
-#define SP_DEBUG_PLL_LOCK BIT(4)
-#define SP_POLLING_EN BIT(1)
-
-/* DP Polling Control Register */
-#define SP_DP_POLLING_CTRL_REG 0xb4
-#define SP_AUTO_POLLING_DISABLE BIT(0)
-
-/* DP Link Debug Control Register */
-#define SP_DP_LINK_DEBUG_CTRL_REG 0xb8
-#define SP_M_VID_DEBUG BIT(5)
-#define SP_NEW_PRBS7 BIT(4)
-#define SP_INSERT_ER BIT(1)
-#define SP_PRBS31_EN BIT(0)
-
-/* AUX Misc control Register */
-#define SP_AUX_MISC_CTRL_REG 0xbf
-
-/* DP PLL control Register */
-#define SP_DP_PLL_CTRL_REG 0xc7
-#define SP_PLL_RST BIT(6)
-
-/* DP Analog Power Down Register */
-#define SP_DP_ANALOG_POWER_DOWN_REG 0xc8
-#define SP_CH0_PD BIT(0)
-
-/* DP Misc Control Register */
-#define SP_DP_MISC_CTRL_REG 0xcd
-#define SP_EQ_TRAINING_LOOP BIT(6)
-
-/* DP Extra I2C Device Address Register */
-#define SP_DP_EXTRA_I2C_DEV_ADDR_REG 0xce
-#define SP_I2C_STRETCH_DISABLE BIT(7)
-
-#define SP_I2C_EXTRA_ADDR 0x50
-
-/* DP Downspread Control Register 1 */
-#define SP_DP_DOWNSPREAD_CTRL1_REG 0xd0
-
-/* DP M Value Calculation Control Register */
-#define SP_DP_M_CALCULATION_CTRL_REG 0xd9
-#define SP_M_GEN_CLK_SEL BIT(0)
-
-/* AUX Channel Access Status Register */
-#define SP_AUX_CH_STATUS_REG 0xe0
-#define SP_AUX_STATUS 0x0f
-
-/* AUX Channel DEFER Control Register */
-#define SP_AUX_DEFER_CTRL_REG 0xe2
-#define SP_DEFER_CTRL_EN BIT(7)
-
-/* DP Buffer Data Count Register */
-#define SP_BUF_DATA_COUNT_REG 0xe4
-#define SP_BUF_DATA_COUNT_MASK 0x1f
-#define SP_BUF_CLR BIT(7)
-
-/* DP AUX Channel Control Register 1 */
-#define SP_DP_AUX_CH_CTRL1_REG 0xe5
-#define SP_AUX_TX_COMM_MASK 0x0f
-#define SP_AUX_LENGTH_MASK 0xf0
-#define SP_AUX_LENGTH_SHIFT 4
-
-/* DP AUX CH Address Register 0 */
-#define SP_AUX_ADDR_7_0_REG 0xe6
-
-/* DP AUX CH Address Register 1 */
-#define SP_AUX_ADDR_15_8_REG 0xe7
-
-/* DP AUX CH Address Register 2 */
-#define SP_AUX_ADDR_19_16_REG 0xe8
-#define SP_AUX_ADDR_19_16_MASK 0x0f
-
-/* DP AUX Channel Control Register 2 */
-#define SP_DP_AUX_CH_CTRL2_REG 0xe9
-#define SP_AUX_SEL_RXCM BIT(6)
-#define SP_AUX_CHSEL BIT(3)
-#define SP_AUX_PN_INV BIT(2)
-#define SP_ADDR_ONLY BIT(1)
-#define SP_AUX_EN BIT(0)
-
-/* DP Video Stream Control InfoFrame Register */
-#define SP_DP_3D_VSC_CTRL_REG 0xea
-#define SP_INFO_FRAME_VSC_EN BIT(0)
-
-/* DP Video Stream Data Byte 1 Register */
-#define SP_DP_VSC_DB1_REG 0xeb
-
-/* DP AUX Channel Control Register 3 */
-#define SP_DP_AUX_CH_CTRL3_REG 0xec
-#define SP_WAIT_COUNTER_7_0_MASK 0xff
-
-/* DP AUX Channel Control Register 4 */
-#define SP_DP_AUX_CH_CTRL4_REG 0xed
-
-/* DP AUX Buffer Data Registers */
-#define SP_DP_BUF_DATA0_REG 0xf0
-
-/***************************************************************/
-/* Register definition of device address 0x72 */
-/***************************************************************/
-
-/*
- * Core Register Definitions
- */
-
-/* Device ID Low Byte Register */
-#define SP_DEVICE_IDL_REG 0x02
-
-/* Device ID High Byte Register */
-#define SP_DEVICE_IDH_REG 0x03
-
-/* Device version register */
-#define SP_DEVICE_VERSION_REG 0x04
-
-/* Power Down Control Register */
-#define SP_POWERDOWN_CTRL_REG 0x05
-#define SP_REGISTER_PD BIT(7)
-#define SP_HDCP_PD BIT(5)
-#define SP_AUDIO_PD BIT(4)
-#define SP_VIDEO_PD BIT(3)
-#define SP_LINK_PD BIT(2)
-#define SP_TOTAL_PD BIT(1)
-
-/* Reset Control Register 1 */
-#define SP_RESET_CTRL1_REG 0x06
-#define SP_MISC_RST BIT(7)
-#define SP_VIDCAP_RST BIT(6)
-#define SP_VIDFIF_RST BIT(5)
-#define SP_AUDFIF_RST BIT(4)
-#define SP_AUDCAP_RST BIT(3)
-#define SP_HDCP_RST BIT(2)
-#define SP_SW_RST BIT(1)
-#define SP_HW_RST BIT(0)
-
-/* Reset Control Register 2 */
-#define SP_RESET_CTRL2_REG 0x07
-#define SP_AUX_RST BIT(2)
-#define SP_SERDES_FIFO_RST BIT(1)
-#define SP_I2C_REG_RST BIT(0)
-
-/* Video Control Register 1 */
-#define SP_VID_CTRL1_REG 0x08
-#define SP_VIDEO_EN BIT(7)
-#define SP_VIDEO_MUTE BIT(2)
-#define SP_DE_GEN BIT(1)
-#define SP_DEMUX BIT(0)
-
-/* Video Control Register 2 */
-#define SP_VID_CTRL2_REG 0x09
-#define SP_IN_COLOR_F_MASK 0x03
-#define SP_IN_YC_BIT_SEL BIT(2)
-#define SP_IN_BPC_MASK 0x70
-#define SP_IN_BPC_SHIFT 4
-# define SP_IN_BPC_12BIT 0x03
-# define SP_IN_BPC_10BIT 0x02
-# define SP_IN_BPC_8BIT 0x01
-# define SP_IN_BPC_6BIT 0x00
-#define SP_IN_D_RANGE BIT(7)
-
-/* Video Control Register 3 */
-#define SP_VID_CTRL3_REG 0x0a
-#define SP_HPD_OUT BIT(6)
-
-/* Video Control Register 5 */
-#define SP_VID_CTRL5_REG 0x0c
-#define SP_CSC_STD_SEL BIT(7)
-#define SP_XVYCC_RNG_LMT BIT(6)
-#define SP_RANGE_Y2R BIT(5)
-#define SP_CSPACE_Y2R BIT(4)
-#define SP_RGB_RNG_LMT BIT(3)
-#define SP_Y_RNG_LMT BIT(2)
-#define SP_RANGE_R2Y BIT(1)
-#define SP_CSPACE_R2Y BIT(0)
-
-/* Video Control Register 6 */
-#define SP_VID_CTRL6_REG 0x0d
-#define SP_TEST_PATTERN_EN BIT(7)
-#define SP_VIDEO_PROCESS_EN BIT(6)
-#define SP_VID_US_MODE BIT(3)
-#define SP_VID_DS_MODE BIT(2)
-#define SP_UP_SAMPLE BIT(1)
-#define SP_DOWN_SAMPLE BIT(0)
-
-/* Video Control Register 8 */
-#define SP_VID_CTRL8_REG 0x0f
-#define SP_VID_VRES_TH BIT(0)
-
-/* Total Line Status Low Byte Register */
-#define SP_TOTAL_LINE_STAL_REG 0x24
-
-/* Total Line Status High Byte Register */
-#define SP_TOTAL_LINE_STAH_REG 0x25
-
-/* Active Line Status Low Byte Register */
-#define SP_ACT_LINE_STAL_REG 0x26
-
-/* Active Line Status High Byte Register */
-#define SP_ACT_LINE_STAH_REG 0x27
-
-/* Vertical Front Porch Status Register */
-#define SP_V_F_PORCH_STA_REG 0x28
-
-/* Vertical SYNC Width Status Register */
-#define SP_V_SYNC_STA_REG 0x29
-
-/* Vertical Back Porch Status Register */
-#define SP_V_B_PORCH_STA_REG 0x2a
-
-/* Total Pixel Status Low Byte Register */
-#define SP_TOTAL_PIXEL_STAL_REG 0x2b
-
-/* Total Pixel Status High Byte Register */
-#define SP_TOTAL_PIXEL_STAH_REG 0x2c
-
-/* Active Pixel Status Low Byte Register */
-#define SP_ACT_PIXEL_STAL_REG 0x2d
-
-/* Active Pixel Status High Byte Register */
-#define SP_ACT_PIXEL_STAH_REG 0x2e
-
-/* Horizontal Front Porch Status Low Byte Register */
-#define SP_H_F_PORCH_STAL_REG 0x2f
-
-/* Horizontal Front Porch Statys High Byte Register */
-#define SP_H_F_PORCH_STAH_REG 0x30
-
-/* Horizontal SYNC Width Status Low Byte Register */
-#define SP_H_SYNC_STAL_REG 0x31
-
-/* Horizontal SYNC Width Status High Byte Register */
-#define SP_H_SYNC_STAH_REG 0x32
-
-/* Horizontal Back Porch Status Low Byte Register */
-#define SP_H_B_PORCH_STAL_REG 0x33
-
-/* Horizontal Back Porch Status High Byte Register */
-#define SP_H_B_PORCH_STAH_REG 0x34
-
-/* InfoFrame AVI Packet DB1 Register */
-#define SP_INFOFRAME_AVI_DB1_REG 0x70
-
-/* Bit Control Specific Register */
-#define SP_BIT_CTRL_SPECIFIC_REG 0x80
-#define SP_BIT_CTRL_SELECT_SHIFT 1
-#define SP_ENABLE_BIT_CTRL BIT(0)
-
-/* InfoFrame Audio Packet DB1 Register */
-#define SP_INFOFRAME_AUD_DB1_REG 0x83
-
-/* InfoFrame MPEG Packet DB1 Register */
-#define SP_INFOFRAME_MPEG_DB1_REG 0xb0
-
-/* Audio Channel Status Registers */
-#define SP_AUD_CH_STATUS_BASE 0xd0
-
-/* Audio Channel Num Register 5 */
-#define SP_I2S_CHANNEL_NUM_MASK 0xe0
-# define SP_I2S_CH_NUM_1 (0x00 << 5)
-# define SP_I2S_CH_NUM_2 (0x01 << 5)
-# define SP_I2S_CH_NUM_3 (0x02 << 5)
-# define SP_I2S_CH_NUM_4 (0x03 << 5)
-# define SP_I2S_CH_NUM_5 (0x04 << 5)
-# define SP_I2S_CH_NUM_6 (0x05 << 5)
-# define SP_I2S_CH_NUM_7 (0x06 << 5)
-# define SP_I2S_CH_NUM_8 (0x07 << 5)
-#define SP_EXT_VUCP BIT(2)
-#define SP_VBIT BIT(1)
-#define SP_AUDIO_LAYOUT BIT(0)
-
-/* Analog Debug Register 2 */
-#define SP_ANALOG_DEBUG2_REG 0xdd
-#define SP_FORCE_SW_OFF_BYPASS 0x20
-#define SP_XTAL_FRQ 0x1c
-# define SP_XTAL_FRQ_19M2 (0x00 << 2)
-# define SP_XTAL_FRQ_24M (0x01 << 2)
-# define SP_XTAL_FRQ_25M (0x02 << 2)
-# define SP_XTAL_FRQ_26M (0x03 << 2)
-# define SP_XTAL_FRQ_27M (0x04 << 2)
-# define SP_XTAL_FRQ_38M4 (0x05 << 2)
-# define SP_XTAL_FRQ_52M (0x06 << 2)
-#define SP_POWERON_TIME_1P5MS 0x03
-
-/* Analog Control 0 Register */
-#define SP_ANALOG_CTRL0_REG 0xe1
-
-/* Common Interrupt Status Register 1 */
-#define SP_COMMON_INT_STATUS_BASE (0xf1 - 1)
-#define SP_PLL_LOCK_CHG 0x40
-
-/* Common Interrupt Status Register 2 */
-#define SP_COMMON_INT_STATUS2 0xf2
-#define SP_HDCP_AUTH_CHG BIT(1)
-#define SP_HDCP_AUTH_DONE BIT(0)
-
-#define SP_HDCP_LINK_CHECK_FAIL BIT(0)
-
-/* Common Interrupt Status Register 4 */
-#define SP_COMMON_INT_STATUS4_REG 0xf4
-#define SP_HPD_IRQ BIT(6)
-#define SP_HPD_ESYNC_ERR BIT(4)
-#define SP_HPD_CHG BIT(2)
-#define SP_HPD_LOST BIT(1)
-#define SP_HPD_PLUG BIT(0)
-
-/* DP Interrupt Status Register */
-#define SP_DP_INT_STATUS1_REG 0xf7
-#define SP_TRAINING_FINISH BIT(5)
-#define SP_POLLING_ERR BIT(4)
-
-/* Common Interrupt Mask Register */
-#define SP_COMMON_INT_MASK_BASE (0xf8 - 1)
-
-#define SP_COMMON_INT_MASK4_REG 0xfb
-
-/* DP Interrupts Mask Register */
-#define SP_DP_INT_MASK1_REG 0xfe
-
-/* Interrupt Control Register */
-#define SP_INT_CTRL_REG 0xff
-
/***************************************************************/
/* Register definition of device address 0x7a */
/***************************************************************/
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
new file mode 100644
index 000000000000..bc0831b127bf
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright(c) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on analogix-anx78xx.h, which is:
+ * Copyright(c) 2016, Analogix Semiconductor. All rights reserved.
+ */
+
+#ifndef _ANALOGIX_I2C_DPTX_H_
+#define _ANALOGIX_I2C_DPTX_H_
+
+#define ANALOGIX_I2C_DPTX 0x70
+
+/***************************************************************/
+/* Register definition of device address 0x70 */
+/***************************************************************/
+
+/* HDCP Status Register */
+#define SP_TX_HDCP_STATUS_REG 0x00
+#define SP_AUTH_FAIL BIT(5)
+#define SP_AUTHEN_PASS BIT(1)
+
+/* HDCP Control Register 0 */
+#define SP_HDCP_CTRL0_REG 0x01
+#define SP_RX_REPEATER BIT(6)
+#define SP_RE_AUTH BIT(5)
+#define SP_SW_AUTH_OK BIT(4)
+#define SP_HARD_AUTH_EN BIT(3)
+#define SP_HDCP_ENC_EN BIT(2)
+#define SP_BKSV_SRM_PASS BIT(1)
+#define SP_KSVLIST_VLD BIT(0)
+/* HDCP Function Enabled */
+#define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* HDCP Receiver BSTATUS Register 0 */
+#define SP_HDCP_RX_BSTATUS0_REG 0x1b
+/* HDCP Receiver BSTATUS Register 1 */
+#define SP_HDCP_RX_BSTATUS1_REG 0x1c
+
+/* HDCP Embedded "Blue Screen" Content Registers */
+#define SP_HDCP_VID0_BLUE_SCREEN_REG 0x2c
+#define SP_HDCP_VID1_BLUE_SCREEN_REG 0x2d
+#define SP_HDCP_VID2_BLUE_SCREEN_REG 0x2e
+
+/* HDCP Wait R0 Timing Register */
+#define SP_HDCP_WAIT_R0_TIME_REG 0x40
+
+/* HDCP Link Integrity Check Timer Register */
+#define SP_HDCP_LINK_CHECK_TIMER_REG 0x41
+
+/* HDCP Repeater Ready Wait Timer Register */
+#define SP_HDCP_RPTR_RDY_WAIT_TIME_REG 0x42
+
+/* HDCP Auto Timer Register */
+#define SP_HDCP_AUTO_TIMER_REG 0x51
+
+/* HDCP Key Status Register */
+#define SP_HDCP_KEY_STATUS_REG 0x5e
+
+/* HDCP Key Command Register */
+#define SP_HDCP_KEY_COMMAND_REG 0x5f
+#define SP_DISABLE_SYNC_HDCP BIT(2)
+
+/* OTP Memory Key Protection Registers */
+#define SP_OTP_KEY_PROTECT1_REG 0x60
+#define SP_OTP_KEY_PROTECT2_REG 0x61
+#define SP_OTP_KEY_PROTECT3_REG 0x62
+#define SP_OTP_PSW1 0xa2
+#define SP_OTP_PSW2 0x7e
+#define SP_OTP_PSW3 0xc6
+
+/* DP System Control Registers */
+#define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1)
+/* Bits for DP System Control Register 2 */
+#define SP_CHA_STA BIT(2)
+/* Bits for DP System Control Register 3 */
+#define SP_HPD_STATUS BIT(6)
+#define SP_STRM_VALID BIT(2)
+/* Bits for DP System Control Register 4 */
+#define SP_ENHANCED_MODE BIT(3)
+
+/* DP Video Control Register */
+#define SP_DP_VIDEO_CTRL_REG 0x84
+#define SP_COLOR_F_MASK 0x06
+#define SP_COLOR_F_SHIFT 1
+#define SP_BPC_MASK 0xe0
+#define SP_BPC_SHIFT 5
+# define SP_BPC_6BITS 0x00
+# define SP_BPC_8BITS 0x01
+# define SP_BPC_10BITS 0x02
+# define SP_BPC_12BITS 0x03
+
+/* DP Audio Control Register */
+#define SP_DP_AUDIO_CTRL_REG 0x87
+#define SP_AUD_EN BIT(0)
+
+/* 10us Pulse Generate Timer Registers */
+#define SP_I2C_GEN_10US_TIMER0_REG 0x88
+#define SP_I2C_GEN_10US_TIMER1_REG 0x89
+
+/* Packet Send Control Register */
+#define SP_PACKET_SEND_CTRL_REG 0x90
+#define SP_AUD_IF_UP BIT(7)
+#define SP_AVI_IF_UD BIT(6)
+#define SP_MPEG_IF_UD BIT(5)
+#define SP_SPD_IF_UD BIT(4)
+#define SP_AUD_IF_EN BIT(3)
+#define SP_AVI_IF_EN BIT(2)
+#define SP_MPEG_IF_EN BIT(1)
+#define SP_SPD_IF_EN BIT(0)
+
+/* DP HDCP Control Register */
+#define SP_DP_HDCP_CTRL_REG 0x92
+#define SP_AUTO_EN BIT(7)
+#define SP_AUTO_START BIT(5)
+#define SP_LINK_POLLING BIT(1)
+
+/* DP Main Link Bandwidth Setting Register */
+#define SP_DP_MAIN_LINK_BW_SET_REG 0xa0
+#define SP_LINK_BW_SET_MASK 0x1f
+#define SP_INITIAL_SLIM_M_AUD_SEL BIT(5)
+
+/* DP Training Pattern Set Register */
+#define SP_DP_TRAINING_PATTERN_SET_REG 0xa2
+
+/* DP Lane 0 Link Training Control Register */
+#define SP_DP_LANE0_LT_CTRL_REG 0xa3
+#define SP_TX_SW_SET_MASK 0x1b
+#define SP_MAX_PRE_REACH BIT(5)
+#define SP_MAX_DRIVE_REACH BIT(4)
+#define SP_PRE_EMP_LEVEL1 BIT(3)
+#define SP_DRVIE_CURRENT_LEVEL1 BIT(0)
+
+/* DP Link Training Control Register */
+#define SP_DP_LT_CTRL_REG 0xa8
+#define SP_LT_ERROR_TYPE_MASK 0x70
+# define SP_LT_NO_ERROR 0x00
+# define SP_LT_AUX_WRITE_ERROR 0x01
+# define SP_LT_MAX_DRIVE_REACHED 0x02
+# define SP_LT_WRONG_LANE_COUNT_SET 0x03
+# define SP_LT_LOOP_SAME_5_TIME 0x04
+# define SP_LT_CR_FAIL_IN_EQ 0x05
+# define SP_LT_EQ_LOOP_5_TIME 0x06
+#define SP_LT_EN BIT(0)
+
+/* DP CEP Training Control Registers */
+#define SP_DP_CEP_TRAINING_CTRL0_REG 0xa9
+#define SP_DP_CEP_TRAINING_CTRL1_REG 0xaa
+
+/* DP Debug Register 1 */
+#define SP_DP_DEBUG1_REG 0xb0
+#define SP_DEBUG_PLL_LOCK BIT(4)
+#define SP_POLLING_EN BIT(1)
+
+/* DP Polling Control Register */
+#define SP_DP_POLLING_CTRL_REG 0xb4
+#define SP_AUTO_POLLING_DISABLE BIT(0)
+
+/* DP Link Debug Control Register */
+#define SP_DP_LINK_DEBUG_CTRL_REG 0xb8
+#define SP_M_VID_DEBUG BIT(5)
+#define SP_NEW_PRBS7 BIT(4)
+#define SP_INSERT_ER BIT(1)
+#define SP_PRBS31_EN BIT(0)
+
+/* AUX Misc control Register */
+#define SP_AUX_MISC_CTRL_REG 0xbf
+
+/* DP PLL control Register */
+#define SP_DP_PLL_CTRL_REG 0xc7
+#define SP_PLL_RST BIT(6)
+
+/* DP Analog Power Down Register */
+#define SP_DP_ANALOG_POWER_DOWN_REG 0xc8
+#define SP_CH0_PD BIT(0)
+
+/* DP Misc Control Register */
+#define SP_DP_MISC_CTRL_REG 0xcd
+#define SP_EQ_TRAINING_LOOP BIT(6)
+
+/* DP Extra I2C Device Address Register */
+#define SP_DP_EXTRA_I2C_DEV_ADDR_REG 0xce
+#define SP_I2C_STRETCH_DISABLE BIT(7)
+
+#define SP_I2C_EXTRA_ADDR 0x50
+
+/* DP Downspread Control Register 1 */
+#define SP_DP_DOWNSPREAD_CTRL1_REG 0xd0
+
+/* DP M Value Calculation Control Register */
+#define SP_DP_M_CALCULATION_CTRL_REG 0xd9
+#define SP_M_GEN_CLK_SEL BIT(0)
+
+/* AUX Channel Access Status Register */
+#define SP_AUX_CH_STATUS_REG 0xe0
+#define SP_AUX_STATUS 0x0f
+
+/* AUX Channel DEFER Control Register */
+#define SP_AUX_DEFER_CTRL_REG 0xe2
+#define SP_DEFER_CTRL_EN BIT(7)
+
+/* DP Buffer Data Count Register */
+#define SP_BUF_DATA_COUNT_REG 0xe4
+#define SP_BUF_DATA_COUNT_MASK 0x1f
+#define SP_BUF_CLR BIT(7)
+
+/* DP AUX Channel Control Register 1 */
+#define SP_DP_AUX_CH_CTRL1_REG 0xe5
+#define SP_AUX_TX_COMM_MASK 0x0f
+#define SP_AUX_LENGTH_MASK 0xf0
+#define SP_AUX_LENGTH_SHIFT 4
+
+/* DP AUX CH Address Register 0 */
+#define SP_AUX_ADDR_7_0_REG 0xe6
+
+/* DP AUX CH Address Register 1 */
+#define SP_AUX_ADDR_15_8_REG 0xe7
+
+/* DP AUX CH Address Register 2 */
+#define SP_AUX_ADDR_19_16_REG 0xe8
+#define SP_AUX_ADDR_19_16_MASK 0x0f
+
+/* DP AUX Channel Control Register 2 */
+#define SP_DP_AUX_CH_CTRL2_REG 0xe9
+#define SP_AUX_SEL_RXCM BIT(6)
+#define SP_AUX_CHSEL BIT(3)
+#define SP_AUX_PN_INV BIT(2)
+#define SP_ADDR_ONLY BIT(1)
+#define SP_AUX_EN BIT(0)
+
+/* DP Video Stream Control InfoFrame Register */
+#define SP_DP_3D_VSC_CTRL_REG 0xea
+#define SP_INFO_FRAME_VSC_EN BIT(0)
+
+/* DP Video Stream Data Byte 1 Register */
+#define SP_DP_VSC_DB1_REG 0xeb
+
+/* DP AUX Channel Control Register 3 */
+#define SP_DP_AUX_CH_CTRL3_REG 0xec
+#define SP_WAIT_COUNTER_7_0_MASK 0xff
+
+/* DP AUX Channel Control Register 4 */
+#define SP_DP_AUX_CH_CTRL4_REG 0xed
+
+/* DP AUX Buffer Data Registers */
+#define SP_DP_BUF_DATA0_REG 0xf0
+
+#endif
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h b/drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h
new file mode 100644
index 000000000000..7d683573e970
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright(c) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on analogix-anx78xx.h, which is:
+ * Copyright(c) 2016, Analogix Semiconductor. All rights reserved.
+ */
+
+#ifndef _ANALOGIX_I2C_TXCOMMON_H_
+#define _ANALOGIX_I2C_TXCOMMON_H_
+
+#define ANALOGIX_I2C_TXCOMMON 0x72
+
+/***************************************************************/
+/* Register definition of device address 0x72 */
+/***************************************************************/
+
+/*
+ * Core Register Definitions
+ */
+
+/* Device ID Low Byte Register */
+#define SP_DEVICE_IDL_REG 0x02
+
+/* Device ID High Byte Register */
+#define SP_DEVICE_IDH_REG 0x03
+
+/* Device version register */
+#define SP_DEVICE_VERSION_REG 0x04
+
+/* Power Down Control Register */
+#define SP_POWERDOWN_CTRL_REG 0x05
+#define SP_REGISTER_PD BIT(7)
+#define SP_HDCP_PD BIT(5)
+#define SP_AUDIO_PD BIT(4)
+#define SP_VIDEO_PD BIT(3)
+#define SP_LINK_PD BIT(2)
+#define SP_TOTAL_PD BIT(1)
+
+/* Reset Control Register 1 */
+#define SP_RESET_CTRL1_REG 0x06
+#define SP_MISC_RST BIT(7)
+#define SP_VIDCAP_RST BIT(6)
+#define SP_VIDFIF_RST BIT(5)
+#define SP_AUDFIF_RST BIT(4)
+#define SP_AUDCAP_RST BIT(3)
+#define SP_HDCP_RST BIT(2)
+#define SP_SW_RST BIT(1)
+#define SP_HW_RST BIT(0)
+
+/* Reset Control Register 2 */
+#define SP_RESET_CTRL2_REG 0x07
+#define SP_AUX_RST BIT(2)
+#define SP_SERDES_FIFO_RST BIT(1)
+#define SP_I2C_REG_RST BIT(0)
+
+/* Video Control Register 1 */
+#define SP_VID_CTRL1_REG 0x08
+#define SP_VIDEO_EN BIT(7)
+#define SP_VIDEO_MUTE BIT(2)
+#define SP_DE_GEN BIT(1)
+#define SP_DEMUX BIT(0)
+
+/* Video Control Register 2 */
+#define SP_VID_CTRL2_REG 0x09
+#define SP_IN_COLOR_F_MASK 0x03
+#define SP_IN_YC_BIT_SEL BIT(2)
+#define SP_IN_BPC_MASK 0x70
+#define SP_IN_BPC_SHIFT 4
+# define SP_IN_BPC_12BIT 0x03
+# define SP_IN_BPC_10BIT 0x02
+# define SP_IN_BPC_8BIT 0x01
+# define SP_IN_BPC_6BIT 0x00
+#define SP_IN_D_RANGE BIT(7)
+
+/* Video Control Register 3 */
+#define SP_VID_CTRL3_REG 0x0a
+#define SP_HPD_OUT BIT(6)
+
+/* Video Control Register 5 */
+#define SP_VID_CTRL5_REG 0x0c
+#define SP_CSC_STD_SEL BIT(7)
+#define SP_XVYCC_RNG_LMT BIT(6)
+#define SP_RANGE_Y2R BIT(5)
+#define SP_CSPACE_Y2R BIT(4)
+#define SP_RGB_RNG_LMT BIT(3)
+#define SP_Y_RNG_LMT BIT(2)
+#define SP_RANGE_R2Y BIT(1)
+#define SP_CSPACE_R2Y BIT(0)
+
+/* Video Control Register 6 */
+#define SP_VID_CTRL6_REG 0x0d
+#define SP_TEST_PATTERN_EN BIT(7)
+#define SP_VIDEO_PROCESS_EN BIT(6)
+#define SP_VID_US_MODE BIT(3)
+#define SP_VID_DS_MODE BIT(2)
+#define SP_UP_SAMPLE BIT(1)
+#define SP_DOWN_SAMPLE BIT(0)
+
+/* Video Control Register 8 */
+#define SP_VID_CTRL8_REG 0x0f
+#define SP_VID_VRES_TH BIT(0)
+
+/* Total Line Status Low Byte Register */
+#define SP_TOTAL_LINE_STAL_REG 0x24
+
+/* Total Line Status High Byte Register */
+#define SP_TOTAL_LINE_STAH_REG 0x25
+
+/* Active Line Status Low Byte Register */
+#define SP_ACT_LINE_STAL_REG 0x26
+
+/* Active Line Status High Byte Register */
+#define SP_ACT_LINE_STAH_REG 0x27
+
+/* Vertical Front Porch Status Register */
+#define SP_V_F_PORCH_STA_REG 0x28
+
+/* Vertical SYNC Width Status Register */
+#define SP_V_SYNC_STA_REG 0x29
+
+/* Vertical Back Porch Status Register */
+#define SP_V_B_PORCH_STA_REG 0x2a
+
+/* Total Pixel Status Low Byte Register */
+#define SP_TOTAL_PIXEL_STAL_REG 0x2b
+
+/* Total Pixel Status High Byte Register */
+#define SP_TOTAL_PIXEL_STAH_REG 0x2c
+
+/* Active Pixel Status Low Byte Register */
+#define SP_ACT_PIXEL_STAL_REG 0x2d
+
+/* Active Pixel Status High Byte Register */
+#define SP_ACT_PIXEL_STAH_REG 0x2e
+
+/* Horizontal Front Porch Status Low Byte Register */
+#define SP_H_F_PORCH_STAL_REG 0x2f
+
+/* Horizontal Front Porch Statys High Byte Register */
+#define SP_H_F_PORCH_STAH_REG 0x30
+
+/* Horizontal SYNC Width Status Low Byte Register */
+#define SP_H_SYNC_STAL_REG 0x31
+
+/* Horizontal SYNC Width Status High Byte Register */
+#define SP_H_SYNC_STAH_REG 0x32
+
+/* Horizontal Back Porch Status Low Byte Register */
+#define SP_H_B_PORCH_STAL_REG 0x33
+
+/* Horizontal Back Porch Status High Byte Register */
+#define SP_H_B_PORCH_STAH_REG 0x34
+
+/* InfoFrame AVI Packet DB1 Register */
+#define SP_INFOFRAME_AVI_DB1_REG 0x70
+
+/* Bit Control Specific Register */
+#define SP_BIT_CTRL_SPECIFIC_REG 0x80
+#define SP_BIT_CTRL_SELECT_SHIFT 1
+#define SP_ENABLE_BIT_CTRL BIT(0)
+
+/* InfoFrame Audio Packet DB1 Register */
+#define SP_INFOFRAME_AUD_DB1_REG 0x83
+
+/* InfoFrame MPEG Packet DB1 Register */
+#define SP_INFOFRAME_MPEG_DB1_REG 0xb0
+
+/* Audio Channel Status Registers */
+#define SP_AUD_CH_STATUS_BASE 0xd0
+
+/* Audio Channel Num Register 5 */
+#define SP_I2S_CHANNEL_NUM_MASK 0xe0
+# define SP_I2S_CH_NUM_1 (0x00 << 5)
+# define SP_I2S_CH_NUM_2 (0x01 << 5)
+# define SP_I2S_CH_NUM_3 (0x02 << 5)
+# define SP_I2S_CH_NUM_4 (0x03 << 5)
+# define SP_I2S_CH_NUM_5 (0x04 << 5)
+# define SP_I2S_CH_NUM_6 (0x05 << 5)
+# define SP_I2S_CH_NUM_7 (0x06 << 5)
+# define SP_I2S_CH_NUM_8 (0x07 << 5)
+#define SP_EXT_VUCP BIT(2)
+#define SP_VBIT BIT(1)
+#define SP_AUDIO_LAYOUT BIT(0)
+
+/* Analog Debug Register 2 */
+#define SP_ANALOG_DEBUG2_REG 0xdd
+#define SP_FORCE_SW_OFF_BYPASS 0x20
+#define SP_XTAL_FRQ 0x1c
+# define SP_XTAL_FRQ_19M2 (0x00 << 2)
+# define SP_XTAL_FRQ_24M (0x01 << 2)
+# define SP_XTAL_FRQ_25M (0x02 << 2)
+# define SP_XTAL_FRQ_26M (0x03 << 2)
+# define SP_XTAL_FRQ_27M (0x04 << 2)
+# define SP_XTAL_FRQ_38M4 (0x05 << 2)
+# define SP_XTAL_FRQ_52M (0x06 << 2)
+#define SP_POWERON_TIME_1P5MS 0x03
+
+/* Analog Control 0 Register */
+#define SP_ANALOG_CTRL0_REG 0xe1
+
+/* Common Interrupt Status Register 1 */
+#define SP_COMMON_INT_STATUS_BASE (0xf1 - 1)
+#define SP_PLL_LOCK_CHG 0x40
+
+/* Common Interrupt Status Register 2 */
+#define SP_COMMON_INT_STATUS2 0xf2
+#define SP_HDCP_AUTH_CHG BIT(1)
+#define SP_HDCP_AUTH_DONE BIT(0)
+
+#define SP_HDCP_LINK_CHECK_FAIL BIT(0)
+
+/* Common Interrupt Status Register 4 */
+#define SP_COMMON_INT_STATUS4_REG 0xf4
+#define SP_HPD_IRQ BIT(6)
+#define SP_HPD_ESYNC_ERR BIT(4)
+#define SP_HPD_CHG BIT(2)
+#define SP_HPD_LOST BIT(1)
+#define SP_HPD_PLUG BIT(0)
+
+/* DP Interrupt Status Register */
+#define SP_DP_INT_STATUS1_REG 0xf7
+#define SP_TRAINING_FINISH BIT(5)
+#define SP_POLLING_ERR BIT(4)
+
+/* Common Interrupt Mask Register */
+#define SP_COMMON_INT_MASK_BASE (0xf8 - 1)
+
+#define SP_COMMON_INT_MASK4_REG 0xfb
+
+/* DP Interrupts Mask Register */
+#define SP_DP_INT_MASK1_REG 0xfe
+
+/* Interrupt Control Register */
+#define SP_INT_CTRL_REG 0xff
+
+#endif /* _ANALOGIX_I2C_TXCOMMON_H_ */
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 3/9] drm/bridge: extract some Analogix I2C DP common code
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
2018-10-18 7:33 ` [PATCH 1/9] drm/bridge: move ANA78xx driver to analogix subdirectory Icenowy Zheng
2018-10-18 7:33 ` [PATCH 2/9] drm/bridge: split some definitions of ANX78xx to dedicated headers Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 7:33 ` [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding Icenowy Zheng
` (7 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-sunxi, Icenowy Zheng
Some code can be shared within different DP bridges by Analogix.
Extract them to a new module.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/gpu/drm/bridge/analogix/Kconfig | 4 +
drivers/gpu/drm/bridge/analogix/Makefile | 2 +
.../drm/bridge/analogix/analogix-anx78xx.c | 146 +--------------
.../drm/bridge/analogix/analogix-i2c-dptx.c | 169 ++++++++++++++++++
.../drm/bridge/analogix/analogix-i2c-dptx.h | 2 +
5 files changed, 178 insertions(+), 145 deletions(-)
create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
index 27b37aa2ea77..eb893b465dd8 100644
--- a/drivers/gpu/drm/bridge/analogix/Kconfig
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -2,8 +2,12 @@ config DRM_ANALOGIX_DP
tristate
depends on DRM
+config DRM_ANALOGIX_DP_I2C
+ tristate
+
config DRM_ANALOGIX_ANX78XX
tristate "Analogix ANX78XX bridge"
+ select DRM_ANALOGIX_DP_I2C
select DRM_KMS_HELPER
select REGMAP_I2C
---help---
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
index eb41be845055..c37e2ded8ce3 100644
--- a/drivers/gpu/drm/bridge/analogix/Makefile
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -1,3 +1,5 @@
analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o
+analogix_dp_i2c-objs := analogix-i2c-dptx.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
+obj-$(CONFIG_DRM_ANALOGIX_DP_I2C) += analogix_dp_i2c.o
obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
index f8433c93f463..bf8291d0ddd0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
@@ -45,8 +45,6 @@
#define I2C_IDX_RX_P1 4
#define XTAL_CLK 270 /* 27M */
-#define AUX_CH_BUFFER_SIZE 16
-#define AUX_WAIT_TIMEOUT_MS 15
static const u8 anx78xx_i2c_addresses[] = {
[I2C_IDX_TX_P0] = TX_P0,
@@ -109,153 +107,11 @@ static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
return regmap_update_bits(map, reg, mask, 0);
}
-static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx)
-{
- unsigned int value;
- int err;
-
- err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
- &value);
- if (err < 0)
- return false;
-
- return (value & SP_AUX_EN) == 0;
-}
-
-static int anx78xx_aux_wait(struct anx78xx *anx78xx)
-{
- unsigned long timeout;
- unsigned int status;
- int err;
-
- timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
-
- while (!anx78xx_aux_op_finished(anx78xx)) {
- if (time_after(jiffies, timeout)) {
- if (!anx78xx_aux_op_finished(anx78xx)) {
- DRM_ERROR("Timed out waiting AUX to finish\n");
- return -ETIMEDOUT;
- }
-
- break;
- }
-
- usleep_range(1000, 2000);
- }
-
- /* Read the AUX channel access status */
- err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG,
- &status);
- if (err < 0) {
- DRM_ERROR("Failed to read from AUX channel: %d\n", err);
- return err;
- }
-
- if (status & SP_AUX_STATUS) {
- DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
- status);
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr)
-{
- int err;
-
- err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG,
- addr & 0xff);
- if (err)
- return err;
-
- err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG,
- (addr & 0xff00) >> 8);
- if (err)
- return err;
-
- /*
- * DP AUX CH Address Register #2, only update bits[3:0]
- * [7:4] RESERVED
- * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
- */
- err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
- SP_AUX_ADDR_19_16_REG,
- SP_AUX_ADDR_19_16_MASK,
- (addr & 0xf0000) >> 16);
-
- if (err)
- return err;
-
- return 0;
-}
-
static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
{
struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
- u8 ctrl1 = msg->request;
- u8 ctrl2 = SP_AUX_EN;
- u8 *buffer = msg->buffer;
- int err;
-
- /* The DP AUX transmit and receive buffer has 16 bytes. */
- if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
- return -E2BIG;
-
- /* Zero-sized messages specify address-only transactions. */
- if (msg->size < 1)
- ctrl2 |= SP_ADDR_ONLY;
- else /* For non-zero-sized set the length field. */
- ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
-
- if ((msg->request & DP_AUX_I2C_READ) == 0) {
- /* When WRITE | MOT write values to data buffer */
- err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0],
- SP_DP_BUF_DATA0_REG, buffer,
- msg->size);
- if (err)
- return err;
- }
-
- /* Write address and request */
- err = anx78xx_aux_address(anx78xx, msg->address);
- if (err)
- return err;
-
- err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG,
- ctrl1);
- if (err)
- return err;
-
- /* Start transaction */
- err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
- SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY |
- SP_AUX_EN, ctrl2);
- if (err)
- return err;
-
- err = anx78xx_aux_wait(anx78xx);
- if (err)
- return err;
-
- msg->reply = DP_AUX_I2C_REPLY_ACK;
-
- if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
- /* Read values from data buffer */
- err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0],
- SP_DP_BUF_DATA0_REG, buffer,
- msg->size);
- if (err)
- return err;
- }
-
- err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
- SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
- if (err)
- return err;
-
- return msg->size;
+ return anx_aux_transfer(anx78xx->map[I2C_IDX_TX_P0], msg);
}
static int anx78xx_set_hpd(struct anx78xx *anx78xx)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c
new file mode 100644
index 000000000000..9cb30962032e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on analogix-anx78xx.c, which is:
+ * Copyright(c) 2016, Analogix Semiconductor. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#include <drm/drm.h>
+#include <drm/drmP.h>
+#include <drm/drm_dp_helper.h>
+
+#include "analogix-i2c-dptx.h"
+
+#define AUX_WAIT_TIMEOUT_MS 15
+#define AUX_CH_BUFFER_SIZE 16
+
+static int anx_clear_bits(struct regmap *map, u8 reg, u8 mask)
+{
+ return regmap_update_bits(map, reg, mask, 0);
+}
+
+static bool anx_aux_op_finished(struct regmap *map_dptx)
+{
+ unsigned int value;
+ int err;
+
+ err = regmap_read(map_dptx, SP_DP_AUX_CH_CTRL2_REG, &value);
+ if (err < 0)
+ return false;
+
+ return (value & SP_AUX_EN) == 0;
+}
+
+static int anx_aux_wait(struct regmap *map_dptx)
+{
+ unsigned long timeout;
+ unsigned int status;
+ int err;
+
+ timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
+
+ while (!anx_aux_op_finished(map_dptx)) {
+ if (time_after(jiffies, timeout)) {
+ if (!anx_aux_op_finished(map_dptx)) {
+ DRM_ERROR("Timed out waiting AUX to finish\n");
+ return -ETIMEDOUT;
+ }
+
+ break;
+ }
+
+ usleep_range(1000, 2000);
+ }
+
+ /* Read the AUX channel access status */
+ err = regmap_read(map_dptx, SP_AUX_CH_STATUS_REG, &status);
+ if (err < 0) {
+ DRM_ERROR("Failed to read from AUX channel: %d\n", err);
+ return err;
+ }
+
+ if (status & SP_AUX_STATUS) {
+ DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
+ status);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int anx_aux_address(struct regmap *map_dptx, unsigned int addr)
+{
+ int err;
+
+ err = regmap_write(map_dptx, SP_AUX_ADDR_7_0_REG, addr & 0xff);
+ if (err)
+ return err;
+
+ err = regmap_write(map_dptx, SP_AUX_ADDR_15_8_REG,
+ (addr & 0xff00) >> 8);
+ if (err)
+ return err;
+
+ /*
+ * DP AUX CH Address Register #2, only update bits[3:0]
+ * [7:4] RESERVED
+ * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
+ */
+ err = regmap_update_bits(map_dptx, SP_AUX_ADDR_19_16_REG,
+ SP_AUX_ADDR_19_16_MASK,
+ (addr & 0xf0000) >> 16);
+
+ if (err)
+ return err;
+
+ return 0;
+}
+
+ssize_t anx_aux_transfer(struct regmap *map_dptx, struct drm_dp_aux_msg *msg)
+{
+ u8 ctrl1 = msg->request;
+ u8 ctrl2 = SP_AUX_EN;
+ u8 *buffer = msg->buffer;
+ int err;
+
+ /* The DP AUX transmit and receive buffer has 16 bytes. */
+ if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
+ return -E2BIG;
+
+ /* Zero-sized messages specify address-only transactions. */
+ if (msg->size < 1)
+ ctrl2 |= SP_ADDR_ONLY;
+ else /* For non-zero-sized set the length field. */
+ ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
+
+ if ((msg->request & DP_AUX_I2C_READ) == 0) {
+ /* When WRITE | MOT write values to data buffer */
+ err = regmap_bulk_write(map_dptx,
+ SP_DP_BUF_DATA0_REG, buffer,
+ msg->size);
+ if (err)
+ return err;
+ }
+
+ /* Write address and request */
+ err = anx_aux_address(map_dptx, msg->address);
+ if (err)
+ return err;
+
+ err = regmap_write(map_dptx, SP_DP_AUX_CH_CTRL1_REG, ctrl1);
+ if (err)
+ return err;
+
+ /* Start transaction */
+ err = regmap_update_bits(map_dptx, SP_DP_AUX_CH_CTRL2_REG,
+ SP_ADDR_ONLY | SP_AUX_EN, ctrl2);
+ if (err)
+ return err;
+
+ err = anx_aux_wait(map_dptx);
+ if (err)
+ return err;
+
+ msg->reply = DP_AUX_I2C_REPLY_ACK;
+
+ if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
+ /* Read values from data buffer */
+ err = regmap_bulk_read(map_dptx,
+ SP_DP_BUF_DATA0_REG, buffer,
+ msg->size);
+ if (err)
+ return err;
+ }
+
+ err = anx_clear_bits(map_dptx, SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
+ if (err)
+ return err;
+
+ return msg->size;
+}
+EXPORT_SYMBOL(anx_aux_transfer);
+
+MODULE_DESCRIPTION("Analogix DisplayPort Transmitter common code");
+MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
index bc0831b127bf..c2ca854613a0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
@@ -245,4 +245,6 @@
/* DP AUX Buffer Data Registers */
#define SP_DP_BUF_DATA0_REG 0xf0
+ssize_t anx_aux_transfer(struct regmap *map_dptx, struct drm_dp_aux_msg *msg);
+
#endif
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
` (2 preceding siblings ...)
2018-10-18 7:33 ` [PATCH 3/9] drm/bridge: extract some Analogix I2C DP common code Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 8:53 ` Laurent Pinchart
2018-10-18 7:33 ` [PATCH 5/9] drm/bridge: Add Analogix anx6345 support Icenowy Zheng
` (6 subsequent siblings)
10 siblings, 1 reply; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-sunxi, Icenowy Zheng
The ANX6345 is an ultra-low power DisplayPort/eDP transmitter designed
for portable devices.
Add a binding document for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../bindings/display/bridge/anx6345.txt | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/anx6345.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/anx6345.txt b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
new file mode 100644
index 000000000000..0689d4eb5f65
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
@@ -0,0 +1,39 @@
+Analogix ANX6345 eDP Transmitter
+--------------------------------
+
+The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for
+portable devices.
+
+Required properties:
+
+ - compatible : "analogix,anx6345"
+ - reg : I2C address of the device
+ - reset-gpios : Which GPIO to use for reset
+
+Optional properties:
+
+ - dvdd12-supply : Regulator for 1.2V digital core power.
+ - dvdd25-supply : Regulator for 2.5V digital core power.
+ - panel-supply : Regulator for the power of the panel.
+ - edid : verbatim EDID data block describing attached
+ panel, only used when the panel has no EDID info.
+ - Video port for RGB input, using the DT bindings defined in [1].
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+anx6345: anx6345@38 {
+ compatible = "analogix,anx6345";
+ reg = <0x38>;
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ panel-supply = <®_dc1sw>;
+ dvdd25-supply = <®_dldo2>;
+ dvdd12-supply = <®_fldo1>;
+
+ port {
+ anx6345_in: endpoint {
+ remote-endpoint = <&tcon0_out_anx6345>;
+ };
+ };
+};
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding
2018-10-18 7:33 ` [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding Icenowy Zheng
@ 2018-10-18 8:53 ` Laurent Pinchart
2018-10-18 10:00 ` Icenowy Zheng
0 siblings, 1 reply; 32+ messages in thread
From: Laurent Pinchart @ 2018-10-18 8:53 UTC (permalink / raw)
To: Icenowy Zheng
Cc: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-sunxi
Hi Icenowy,
Thank you for the patch.
On Thursday, 18 October 2018 10:33:22 EEST Icenowy Zheng wrote:
> The ANX6345 is an ultra-low power DisplayPort/eDP transmitter designed
> for portable devices.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> .../bindings/display/bridge/anx6345.txt | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/anx6345.txt
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> b/Documentation/devicetree/bindings/display/bridge/anx6345.txt new file
> mode 100644
> index 000000000000..0689d4eb5f65
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> @@ -0,0 +1,39 @@
> +Analogix ANX6345 eDP Transmitter
> +--------------------------------
> +
> +The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for
> +portable devices.
> +
> +Required properties:
> +
> + - compatible : "analogix,anx6345"
> + - reg : I2C address of the device
> + - reset-gpios : Which GPIO to use for reset
> +
> +Optional properties:
> +
> + - dvdd12-supply : Regulator for 1.2V digital core power.
> + - dvdd25-supply : Regulator for 2.5V digital core power.
Shouldn't these to supplies be mandatory ?
> + - panel-supply : Regulator for the power of the panel.
Shouldn't the panel supply for specified in the DT node of the panel ?
> + - edid : verbatim EDID data block describing attached
> + panel, only used when the panel has no EDID info.
This should also be specified in the panel DT node.
> + - Video port for RGB input, using the DT bindings defined in [1].
I think you should also add a port for the output.
> +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> +Example:
> +
> +anx6345: anx6345@38 {
> + compatible = "analogix,anx6345";
> + reg = <0x38>;
> + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
> + panel-supply = <®_dc1sw>;
> + dvdd25-supply = <®_dldo2>;
> + dvdd12-supply = <®_fldo1>;
> +
> + port {
> + anx6345_in: endpoint {
> + remote-endpoint = <&tcon0_out_anx6345>;
> + };
> + };
> +};
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding
2018-10-18 8:53 ` Laurent Pinchart
@ 2018-10-18 10:00 ` Icenowy Zheng
2018-10-18 11:23 ` Laurent Pinchart
0 siblings, 1 reply; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 10:00 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Archit Taneja, Andrzej Hajda, David Airlie,
linux-sunxi, linux-kernel, dri-devel, Maxime Ripard,
Chen-Yu Tsai, Rob Herring, linux-arm-kernel
在 2018-10-18四的 11:53 +0300，Laurent Pinchart写道：
> Hi Icenowy,
>
> Thank you for the patch.
>
> On Thursday, 18 October 2018 10:33:22 EEST Icenowy Zheng wrote:
> > The ANX6345 is an ultra-low power DisplayPort/eDP transmitter
> > designed
> > for portable devices.
> >
> > Add a binding document for it.
> >
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > ---
> > .../bindings/display/bridge/anx6345.txt | 39
> > +++++++++++++++++++
> > 1 file changed, 39 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/bridge/anx6345.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > b/Documentation/devicetree/bindings/display/bridge/anx6345.txt new
> > file
> > mode 100644
> > index 000000000000..0689d4eb5f65
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > @@ -0,0 +1,39 @@
> > +Analogix ANX6345 eDP Transmitter
> > +--------------------------------
> > +
> > +The ANX6345 is an ultra-low power Full-HD eDP transmitter designed
> > for
> > +portable devices.
> > +
> > +Required properties:
> > +
> > + - compatible : "analogix,anx6345"
> > + - reg : I2C address of the device
> > + - reset-gpios : Which GPIO to use for reset
> > +
> > +Optional properties:
> > +
> > + - dvdd12-supply : Regulator for 1.2V digital core power.
> > + - dvdd25-supply : Regulator for 2.5V digital core power.
>
> Shouldn't these to supplies be mandatory ?
Yes they should.
>
> > + - panel-supply : Regulator for the power of the panel.
>
> Shouldn't the panel supply for specified in the DT node of the panel
> ?
However, eDP panel can be probed, may vary on the same device, and we
don't have a generic binding for it...
>
> > + - edid : verbatim EDID data block describing
> > attached
> > + panel, only used when the panel has no EDID
> > info.
>
> This should also be specified in the panel DT node.
>
> > + - Video port for RGB input, using the DT bindings defined in [1].
>
> I think you should also add a port for the output.
What will it point to?
>
> > +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
> > +
> > +Example:
> > +
> > +anx6345: anx6345@38 {
> > + compatible = "analogix,anx6345";
> > + reg = <0x38>;
> > + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
> > + panel-supply = <®_dc1sw>;
> > + dvdd25-supply = <®_dldo2>;
> > + dvdd12-supply = <®_fldo1>;
> > +
> > + port {
> > + anx6345_in: endpoint {
> > + remote-endpoint = <&tcon0_out_anx6345>;
> > + };
> > + };
> > +};
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding
2018-10-18 10:00 ` Icenowy Zheng
@ 2018-10-18 11:23 ` Laurent Pinchart
2018-10-18 12:40 ` Icenowy Zheng
0 siblings, 1 reply; 32+ messages in thread
From: Laurent Pinchart @ 2018-10-18 11:23 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, Archit Taneja, Andrzej Hajda, David Airlie,
linux-sunxi, linux-kernel, dri-devel, Maxime Ripard,
Chen-Yu Tsai, Rob Herring, linux-arm-kernel
Hi Icenowy,
On Thursday, 18 October 2018 13:00:05 EEST Icenowy Zheng wrote:
> 在 2018-10-18四的 11:53 +0300，Laurent Pinchart写道：
> > On Thursday, 18 October 2018 10:33:22 EEST Icenowy Zheng wrote:
> >> The ANX6345 is an ultra-low power DisplayPort/eDP transmitter
> >> designed
> >> for portable devices.
> >>
> >> Add a binding document for it.
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> ---
> >>
> >> .../bindings/display/bridge/anx6345.txt | 39 +++++++++++++++++++
> >>
> >> 1 file changed, 39 insertions(+)
> >> create mode 100644
> >>
> >> Documentation/devicetree/bindings/display/bridge/anx6345.txt
> >>
> >> diff --git
> >> a/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> >> b/Documentation/devicetree/bindings/display/bridge/anx6345.txt new
> >> file
> >> mode 100644
> >> index 000000000000..0689d4eb5f65
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> >> @@ -0,0 +1,39 @@
> >> +Analogix ANX6345 eDP Transmitter
> >> +--------------------------------
> >> +
> >> +The ANX6345 is an ultra-low power Full-HD eDP transmitter designed
> >> for
> >> +portable devices.
> >> +
> >> +Required properties:
> >> +
> >> + - compatible : "analogix,anx6345"
> >> + - reg : I2C address of the device
> >> + - reset-gpios : Which GPIO to use for reset
> >> +
> >> +Optional properties:
> >> +
> >> + - dvdd12-supply : Regulator for 1.2V digital core power.
> >> + - dvdd25-supply : Regulator for 2.5V digital core power.
> >
> > Shouldn't these to supplies be mandatory ?
>
> Yes they should.
>
> >> + - panel-supply : Regulator for the power of the panel.
> >
> > Shouldn't the panel supply for specified in the DT node of the panel
> > ?
>
> However, eDP panel can be probed, may vary on the same device, and we
> don't have a generic binding for it...
Shouldn't we fix that ? :-)
> >> + - edid : verbatim EDID data block describing
> >> attached
> >> + panel, only used when the panel has no EDID
> >> info.
> >
> > This should also be specified in the panel DT node.
> >
> > > + - Video port for RGB input, using the DT bindings defined in [1].
> >
> > I think you should also add a port for the output.
>
> What will it point to?
The panel DT node ?
> >> +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
> >> +
> >> +Example:
> >> +
> >> +anx6345: anx6345@38 {
> >> + compatible = "analogix,anx6345";
> >> + reg = <0x38>;
> >> + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
> >> + panel-supply = <®_dc1sw>;
> >> + dvdd25-supply = <®_dldo2>;
> >> + dvdd12-supply = <®_fldo1>;
> >> +
> >> + port {
> >> + anx6345_in: endpoint {
> >> + remote-endpoint = <&tcon0_out_anx6345>;
> >> + };
> >> + };
> >> +};
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding
2018-10-18 11:23 ` Laurent Pinchart
@ 2018-10-18 12:40 ` Icenowy Zheng
2018-10-25 18:30 ` Rob Herring
0 siblings, 1 reply; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 12:40 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Archit Taneja, David Airlie, linux-kernel, dri-devel,
Andrzej Hajda, linux-sunxi, Rob Herring, Maxime Ripard,
Chen-Yu Tsai, linux-arm-kernel
在 2018-10-18四的 14:23 +0300，Laurent Pinchart写道：
> Hi Icenowy,
>
> On Thursday, 18 October 2018 13:00:05 EEST Icenowy Zheng wrote:
> > 在 2018-10-18四的 11:53 +0300，Laurent Pinchart写道：
> > > On Thursday, 18 October 2018 10:33:22 EEST Icenowy Zheng wrote:
> > > > The ANX6345 is an ultra-low power DisplayPort/eDP transmitter
> > > > designed
> > > > for portable devices.
> > > >
> > > > Add a binding document for it.
> > > >
> > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > > ---
> > > >
> > > > .../bindings/display/bridge/anx6345.txt | 39
> > > > +++++++++++++++++++
> > > >
> > > > 1 file changed, 39 insertions(+)
> > > > create mode 100644
> > > >
> > > > Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > > > b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > > > new
> > > > file
> > > > mode 100644
> > > > index 000000000000..0689d4eb5f65
> > > > --- /dev/null
> > > > +++
> > > > b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > > > @@ -0,0 +1,39 @@
> > > > +Analogix ANX6345 eDP Transmitter
> > > > +--------------------------------
> > > > +
> > > > +The ANX6345 is an ultra-low power Full-HD eDP transmitter
> > > > designed
> > > > for
> > > > +portable devices.
> > > > +
> > > > +Required properties:
> > > > +
> > > > + - compatible : "analogix,anx6345"
> > > > + - reg : I2C address of the device
> > > > + - reset-gpios : Which GPIO to use for reset
> > > > +
> > > > +Optional properties:
> > > > +
> > > > + - dvdd12-supply : Regulator for 1.2V digital core
> > > > power.
> > > > + - dvdd25-supply : Regulator for 2.5V digital core
> > > > power.
> > >
> > > Shouldn't these to supplies be mandatory ?
> >
> > Yes they should.
> >
> > > > + - panel-supply : Regulator for the power of
> > > > the panel.
> > >
> > > Shouldn't the panel supply for specified in the DT node of the
> > > panel
> > > ?
> >
> > However, eDP panel can be probed, may vary on the same device, and
> > we
> > don't have a generic binding for it...
>
> Shouldn't we fix that ? :-)
Maybe we should create a connector binding instead of a panel binding?
>
> > > > + - edid : verbatim EDID data block
> > > > describing
> > > > attached
> > > > + panel, only used when the panel has
> > > > no EDID
> > > > info.
> > >
> > > This should also be specified in the panel DT node.
> > >
> > > > + - Video port for RGB input, using the DT bindings defined in
> > > > [1].
> > >
> > > I think you should also add a port for the output.
> >
> > What will it point to?
>
> The panel DT node ?
>
> > > > +[1]: Documentation/devicetree/bindings/media/video-
> > > > interfaces.txt
> > > > +
> > > > +Example:
> > > > +
> > > > +anx6345: anx6345@38 {
> > > > + compatible = "analogix,anx6345";
> > > > + reg = <0x38>;
> > > > + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
> > > > + panel-supply = <®_dc1sw>;
> > > > + dvdd25-supply = <®_dldo2>;
> > > > + dvdd12-supply = <®_fldo1>;
> > > > +
> > > > + port {
> > > > + anx6345_in: endpoint {
> > > > + remote-endpoint = <&tcon0_out_anx6345>;
> > > > + };
> > > > + };
> > > > +};
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding
2018-10-18 12:40 ` Icenowy Zheng
@ 2018-10-25 18:30 ` Rob Herring
2018-10-26 0:08 ` Icenowy Zheng
0 siblings, 1 reply; 32+ messages in thread
From: Rob Herring @ 2018-10-25 18:30 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Laurent Pinchart, devicetree, Archit Taneja, David Airlie,
linux-kernel, dri-devel, Andrzej Hajda, linux-sunxi,
Maxime Ripard, Chen-Yu Tsai, linux-arm-kernel
On Thu, Oct 18, 2018 at 08:40:11PM +0800, Icenowy Zheng wrote:
> 在 2018-10-18四的 14:23 +0300，Laurent Pinchart写道：
> > Hi Icenowy,
> >
> > On Thursday, 18 October 2018 13:00:05 EEST Icenowy Zheng wrote:
> > > 在 2018-10-18四的 11:53 +0300，Laurent Pinchart写道：
> > > > On Thursday, 18 October 2018 10:33:22 EEST Icenowy Zheng wrote:
> > > > > The ANX6345 is an ultra-low power DisplayPort/eDP transmitter
> > > > > designed
> > > > > for portable devices.
> > > > >
> > > > > Add a binding document for it.
> > > > >
> > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > > > ---
> > > > >
> > > > > .../bindings/display/bridge/anx6345.txt | 39
> > > > > +++++++++++++++++++
> > > > >
> > > > > 1 file changed, 39 insertions(+)
> > > > > create mode 100644
> > > > >
> > > > > Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > > > > b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > > > > new
> > > > > file
> > > > > mode 100644
> > > > > index 000000000000..0689d4eb5f65
> > > > > --- /dev/null
> > > > > +++
> > > > > b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
> > > > > @@ -0,0 +1,39 @@
> > > > > +Analogix ANX6345 eDP Transmitter
> > > > > +--------------------------------
> > > > > +
> > > > > +The ANX6345 is an ultra-low power Full-HD eDP transmitter
> > > > > designed
> > > > > for
> > > > > +portable devices.
> > > > > +
> > > > > +Required properties:
> > > > > +
> > > > > + - compatible : "analogix,anx6345"
> > > > > + - reg : I2C address of the device
> > > > > + - reset-gpios : Which GPIO to use for reset
> > > > > +
> > > > > +Optional properties:
> > > > > +
> > > > > + - dvdd12-supply : Regulator for 1.2V digital core
> > > > > power.
> > > > > + - dvdd25-supply : Regulator for 2.5V digital core
> > > > > power.
> > > >
> > > > Shouldn't these to supplies be mandatory ?
> > >
> > > Yes they should.
> > >
> > > > > + - panel-supply : Regulator for the power of
> > > > > the panel.
> > > >
> > > > Shouldn't the panel supply for specified in the DT node of the
> > > > panel
> > > > ?
> > >
> > > However, eDP panel can be probed, may vary on the same device, and
> > > we
> > > don't have a generic binding for it...
> >
> > Shouldn't we fix that ? :-)
>
> Maybe we should create a connector binding instead of a panel binding?
There's not any such thing as a standard eDP connector, is there?
Otherwise, that's just creating a generic panel binding in disguise.
Maybe if eDP interface is standardized enough in terms of power control,
control lines, EDID at least sometimes present, etc., then we could have
some sort of generic eDP panel/connector binding.
Rob
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding
2018-10-25 18:30 ` Rob Herring
@ 2018-10-26 0:08 ` Icenowy Zheng
0 siblings, 0 replies; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-26 0:08 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring
Cc: devicetree, Archit Taneja, David Airlie, linux-kernel, dri-devel,
Andrzej Hajda, linux-sunxi, Laurent Pinchart, Maxime Ripard,
Chen-Yu Tsai
于 2018年10月26日 GMT+08:00 上午2:30:03, Rob Herring <robh@kernel.org> 写到:
>On Thu, Oct 18, 2018 at 08:40:11PM +0800, Icenowy Zheng wrote:
>> 在 2018-10-18四的 14:23 +0300，Laurent Pinchart写道：
>> > Hi Icenowy,
>> >
>> > On Thursday, 18 October 2018 13:00:05 EEST Icenowy Zheng wrote:
>> > > 在 2018-10-18四的 11:53 +0300，Laurent Pinchart写道：
>> > > > On Thursday, 18 October 2018 10:33:22 EEST Icenowy Zheng wrote:
>> > > > > The ANX6345 is an ultra-low power DisplayPort/eDP transmitter
>> > > > > designed
>> > > > > for portable devices.
>> > > > >
>> > > > > Add a binding document for it.
>> > > > >
>> > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> > > > > ---
>> > > > >
>> > > > > .../bindings/display/bridge/anx6345.txt | 39
>> > > > > +++++++++++++++++++
>> > > > >
>> > > > > 1 file changed, 39 insertions(+)
>> > > > > create mode 100644
>> > > > >
>> > > > > Documentation/devicetree/bindings/display/bridge/anx6345.txt
>> > > > >
>> > > > > diff --git
>> > > > >
>a/Documentation/devicetree/bindings/display/bridge/anx6345.txt
>> > > > >
>b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
>> > > > > new
>> > > > > file
>> > > > > mode 100644
>> > > > > index 000000000000..0689d4eb5f65
>> > > > > --- /dev/null
>> > > > > +++
>> > > > >
>b/Documentation/devicetree/bindings/display/bridge/anx6345.txt
>> > > > > @@ -0,0 +1,39 @@
>> > > > > +Analogix ANX6345 eDP Transmitter
>> > > > > +--------------------------------
>> > > > > +
>> > > > > +The ANX6345 is an ultra-low power Full-HD eDP transmitter
>> > > > > designed
>> > > > > for
>> > > > > +portable devices.
>> > > > > +
>> > > > > +Required properties:
>> > > > > +
>> > > > > + - compatible : "analogix,anx6345"
>> > > > > + - reg : I2C address of the device
>> > > > > + - reset-gpios : Which GPIO to use for reset
>> > > > > +
>> > > > > +Optional properties:
>> > > > > +
>> > > > > + - dvdd12-supply : Regulator for 1.2V digital core
>> > > > > power.
>> > > > > + - dvdd25-supply : Regulator for 2.5V digital core
>> > > > > power.
>> > > >
>> > > > Shouldn't these to supplies be mandatory ?
>> > >
>> > > Yes they should.
>> > >
>> > > > > + - panel-supply : Regulator for the power of
>> > > > > the panel.
>> > > >
>> > > > Shouldn't the panel supply for specified in the DT node of the
>> > > > panel
>> > > > ?
>> > >
>> > > However, eDP panel can be probed, may vary on the same device,
>and
>> > > we
>> > > don't have a generic binding for it...
>> >
>> > Shouldn't we fix that ? :-)
>>
>> Maybe we should create a connector binding instead of a panel
>binding?
>
>There's not any such thing as a standard eDP connector, is there?
>Otherwise, that's just creating a generic panel binding in disguise.
>Maybe if eDP interface is standardized enough in terms of power
>control,
>control lines, EDID at least sometimes present, etc., then we could
eDP has the same display signal set with DP, including AUX which
carries DPCD and EDID (if present).
But I don't know whether other lines are standardized, including power, backlight, etc.
>have
>some sort of generic eDP panel/connector binding.
>
>Rob
>
>_______________________________________________
>linux-arm-kernel mailing list
>linux-arm-kernel@lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 5/9] drm/bridge: Add Analogix anx6345 support
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
` (3 preceding siblings ...)
2018-10-18 7:33 ` [PATCH 4/9] dt-bindings: Add ANX6345 DP/eDP transmitter binding Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 7:33 ` [PATCH 6/9] arm64: allwinner: a64: add pinmux for RGB666 LCD Icenowy Zheng
` (5 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-sunxi, Icenowy Zheng
The ANX6345 is an ultra-low power DisplayPower/eDP transmitter designed
for portable devices. This driver adds initial support for RGB to eDP
mode, without HPD and interrupts, but with possibility to inject EDID.
This is a configuration usually seen in eDP applications.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/gpu/drm/bridge/analogix/Kconfig | 11 +
drivers/gpu/drm/bridge/analogix/Makefile | 1 +
.../drm/bridge/analogix/analogix-anx6345.c | 862 ++++++++++++++++++
.../drm/bridge/analogix/analogix-i2c-dptx.c | 2 +-
.../drm/bridge/analogix/analogix-i2c-dptx.h | 8 +
.../bridge/analogix/analogix-i2c-txcommon.h | 3 +
6 files changed, 886 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
index eb893b465dd8..784ddca83b47 100644
--- a/drivers/gpu/drm/bridge/analogix/Kconfig
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -15,3 +15,14 @@ config DRM_ANALOGIX_ANX78XX
designed for portable devices. The ANX78XX transforms
the HDMI output of an application processor to MyDP
or DisplayPort.
+
+config DRM_ANALOGIX_ANX6345
+ tristate "Analogix ANX6345 bridge"
+ select DRM_ANALOGIX_DP_I2C
+ select DRM_KMS_HELPER
+ select REGMAP_I2C
+ help
+ ANX6345 is an ultra-low Full-HD DisplayPort/eDP
+ transmitter designed for portable devices. The
+ ANX6345 transforms the LVTTL RGB output of an
+ application processor to eDP or DisplayPort.
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
index c37e2ded8ce3..3af9feab6e17 100644
--- a/drivers/gpu/drm/bridge/analogix/Makefile
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -3,3 +3,4 @@ analogix_dp_i2c-objs := analogix-i2c-dptx.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
obj-$(CONFIG_DRM_ANALOGIX_DP_I2C) += analogix_dp_i2c.o
obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
+obj-$(CONFIG_DRM_ANALOGIX_ANX6345) += analogix-anx6345.o
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
new file mode 100644
index 000000000000..81676407aa6d
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
@@ -0,0 +1,862 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) Icenowy Zheng <icenowy@aosc.io>
+ * Based on analogix-anx6345.c, which is:
+ * Copyright(c) 2016, Analogix Semiconductor.
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_edid.h>
+
+#include "analogix-i2c-dptx.h"
+#include "analogix-i2c-txcommon.h"
+
+#define I2C_NUM_ADDRESSES 2
+#define I2C_IDX_DPTX 0
+#define I2C_IDX_TXCOM 1
+
+#define XTAL_CLK 270 /* 27M */
+
+#define POLL_DELAY 50000 /* us */
+#define POLL_TIMEOUT 5000000 /* us */
+
+static const u8 anx6345_i2c_addresses[] = {
+ [I2C_IDX_DPTX] = ANALOGIX_I2C_DPTX,
+ [I2C_IDX_TXCOM] = ANALOGIX_I2C_TXCOMMON,
+};
+
+struct anx6345_platform_data {
+ struct regulator *dvdd12;
+ struct regulator *dvdd25;
+ struct regulator *vcc_panel;
+ struct gpio_desc *gpiod_reset;
+};
+
+struct anx6345 {
+ struct drm_dp_aux aux;
+ struct drm_bridge bridge;
+ struct i2c_client *client;
+ struct edid *edid;
+ struct drm_connector connector;
+ struct drm_dp_link link;
+ struct anx6345_platform_data pdata;
+ struct mutex lock;
+
+ /*
+ * I2C Slave addresses of ANX6345 are mapped as DPTX and SYS
+ */
+ struct i2c_client *i2c_clients[I2C_NUM_ADDRESSES];
+ struct regmap *map[I2C_NUM_ADDRESSES];
+
+ u16 chipid;
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+ bool powered;
+};
+
+static inline struct anx6345 *connector_to_anx6345(struct drm_connector *c)
+{
+ return container_of(c, struct anx6345, connector);
+}
+
+static inline struct anx6345 *bridge_to_anx6345(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct anx6345, bridge);
+}
+
+static int anx6345_set_bits(struct regmap *map, u8 reg, u8 mask)
+{
+ return regmap_update_bits(map, reg, mask, mask);
+}
+
+static int anx6345_clear_bits(struct regmap *map, u8 reg, u8 mask)
+{
+ return regmap_update_bits(map, reg, mask, 0);
+}
+
+static ssize_t anx6345_aux_transfer(struct drm_dp_aux *aux,
+ struct drm_dp_aux_msg *msg)
+{
+ struct anx6345 *anx6345 = container_of(aux, struct anx6345, aux);
+
+ return anx_aux_transfer(anx6345->map[I2C_IDX_DPTX], msg);
+}
+
+static int anx6345_dp_link_training(struct anx6345 *anx6345)
+{
+ unsigned int value;
+ u8 dp_bw;
+ int err;
+
+ err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],
+ SP_POWERDOWN_CTRL_REG,
+ SP_TOTAL_PD);
+ if (err)
+ return err;
+
+ err = drm_dp_dpcd_readb(&anx6345->aux, DP_MAX_LINK_RATE, &dp_bw);
+ if (err < 0)
+ return err;
+
+ switch (dp_bw) {
+ case DP_LINK_BW_1_62:
+ case DP_LINK_BW_2_7:
+ break;
+
+ default:
+ DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
+ return -EINVAL;
+ }
+
+ err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG,
+ SP_VIDEO_MUTE);
+ if (err)
+ return err;
+
+ err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],
+ SP_VID_CTRL1_REG, SP_VIDEO_EN);
+ if (err)
+ return err;
+
+ /* Get DPCD info */
+ err = drm_dp_dpcd_read(&anx6345->aux, DP_DPCD_REV,
+ &anx6345->dpcd, DP_RECEIVER_CAP_SIZE);
+ if (err < 0) {
+ DRM_ERROR("Failed to read DPCD: %d\n", err);
+ return err;
+ }
+
+ /* Clear channel x SERDES power down */
+ err = anx6345_clear_bits(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
+ if (err)
+ return err;
+
+ /* Check link capabilities */
+ err = drm_dp_link_probe(&anx6345->aux, &anx6345->link);
+ if (err < 0) {
+ DRM_ERROR("Failed to probe link capabilities: %d\n", err);
+ return err;
+ }
+
+ /* Power up the sink */
+ err = drm_dp_link_power_up(&anx6345->aux, &anx6345->link);
+ if (err < 0) {
+ DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
+ return err;
+ }
+
+ /* Possibly enable downspread on the sink */
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_DOWNSPREAD_CTRL1_REG, 0);
+ if (err)
+ return err;
+
+ if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
+ DRM_DEBUG("Enable downspread on the sink\n");
+ /* 4000PPM */
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_DOWNSPREAD_CTRL1_REG, 8);
+ if (err)
+ return err;
+
+ err = drm_dp_dpcd_writeb(&anx6345->aux, DP_DOWNSPREAD_CTRL,
+ DP_SPREAD_AMP_0_5);
+ if (err < 0)
+ return err;
+ } else {
+ err = drm_dp_dpcd_writeb(&anx6345->aux, DP_DOWNSPREAD_CTRL, 0);
+ if (err < 0)
+ return err;
+ }
+
+ /* Set the lane count and the link rate on the sink */
+ if (drm_dp_enhanced_frame_cap(anx6345->dpcd))
+ err = anx6345_set_bits(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_SYSTEM_CTRL_BASE + 4,
+ SP_ENHANCED_MODE);
+ else
+ err = anx6345_clear_bits(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_SYSTEM_CTRL_BASE + 4,
+ SP_ENHANCED_MODE);
+ if (err)
+ return err;
+
+ value = drm_dp_link_rate_to_bw_code(anx6345->link.rate);
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_MAIN_LINK_BW_SET_REG, value);
+ if (err)
+ return err;
+
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_LANE_COUNT_SET_REG, anx6345->link.num_lanes);
+ if (err)
+ return err;
+
+ err = drm_dp_link_configure(&anx6345->aux, &anx6345->link);
+ if (err < 0) {
+ DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
+ return err;
+ }
+
+ /* Start training on the source */
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX], SP_DP_LT_CTRL_REG,
+ SP_LT_EN);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_LT_CTRL_REG,
+ value, !(value & SP_DP_LT_INPROGRESS),
+ POLL_DELAY, POLL_TIMEOUT);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int anx6345_tx_initialization(struct anx6345 *anx6345)
+{
+ int err, i;
+
+ /* FIXME: hardcode color depth now */
+ err = regmap_write(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL2_REG,
+ SP_IN_BPC_6BIT << SP_IN_BPC_SHIFT);
+ if (err)
+ return err;
+
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX], SP_DP_PLL_CTRL_REG, 0);
+ if (err)
+ return err;
+
+ err = regmap_write(anx6345->map[I2C_IDX_TXCOM],
+ SP_ANALOG_DEBUG1_REG, 0);
+ if (err)
+ return err;
+
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_LINK_DEBUG_CTRL_REG,
+ SP_NEW_PRBS7 | SP_M_VID_DEBUG);
+ if (err)
+ return err;
+
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_ANALOG_POWER_DOWN_REG, 0);
+ if (err)
+ return err;
+
+ /* Force HPD */
+ err = anx6345_set_bits(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_SYSTEM_CTRL_BASE + 3,
+ SP_HPD_FORCE | SP_HPD_CTRL);
+ if (err)
+ return err;
+
+ for (i = 0; i < 4; i++) {
+ /* 4 lanes */
+ err = regmap_write(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_LANE0_LT_CTRL_REG + i, 0);
+ if (err)
+ return err;
+ }
+
+ /* Reset AUX */
+ err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM],
+ SP_RESET_CTRL2_REG, SP_AUX_RST);
+ if (err)
+ return err;
+
+ err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],
+ SP_RESET_CTRL2_REG, SP_AUX_RST);
+ if (err)
+ return err;
+
+ err = anx6345_dp_link_training(anx6345);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static void anx6345_poweron(struct anx6345 *anx6345)
+{
+ struct anx6345_platform_data *pdata = &anx6345->pdata;
+ int err;
+
+ if (WARN_ON(anx6345->powered))
+ return;
+
+ if (pdata->dvdd12) {
+ err = regulator_enable(pdata->dvdd12);
+ if (err) {
+ DRM_ERROR("Failed to enable DVDD12 regulator: %d\n",
+ err);
+ return;
+ }
+
+ usleep_range(1000, 2000);
+ }
+
+ if (pdata->dvdd25) {
+ err = regulator_enable(pdata->dvdd25);
+ if (err) {
+ DRM_ERROR("Failed to enable DVDD25 regulator: %d\n",
+ err);
+ return;
+ }
+
+ usleep_range(5000, 10000);
+ }
+
+ if (pdata->vcc_panel) {
+ err = regulator_enable(pdata->vcc_panel);
+ if (err) {
+ DRM_ERROR("Failed to enable panel regulator: %d\n",
+ err);
+ return;
+ }
+ }
+
+ gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
+ usleep_range(1000, 2000);
+
+ gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
+
+ /* Power on registers module */
+ anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG,
+ SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
+ anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG,
+ SP_REGISTER_PD | SP_TOTAL_PD);
+
+ anx6345->powered = true;
+}
+
+static void anx6345_poweroff(struct anx6345 *anx6345)
+{
+ struct anx6345_platform_data *pdata = &anx6345->pdata;
+ int err;
+
+ if (WARN_ON(!anx6345->powered))
+ return;
+
+ gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
+ usleep_range(1000, 2000);
+
+ if (pdata->vcc_panel) {
+ err = regulator_disable(pdata->vcc_panel);
+ if (err) {
+ DRM_ERROR("Failed to disable panel regulator: %d\n",
+ err);
+ return;
+ }
+ }
+
+ if (pdata->dvdd25) {
+ err = regulator_disable(pdata->dvdd25);
+ if (err) {
+ DRM_ERROR("Failed to disable DVDD25 regulator: %d\n",
+ err);
+ return;
+ }
+
+ usleep_range(5000, 10000);
+ }
+
+ if (pdata->dvdd12) {
+ err = regulator_disable(pdata->dvdd12);
+ if (err) {
+ DRM_ERROR("Failed to disable DVDD12 regulator: %d\n",
+ err);
+ return;
+ }
+
+ usleep_range(1000, 2000);
+ }
+
+ anx6345->powered = false;
+}
+
+static int anx6345_start(struct anx6345 *anx6345)
+{
+ int err;
+
+ if (!anx6345->powered)
+ anx6345_poweron(anx6345);
+
+ /* Power on needed modules */
+ err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],
+ SP_POWERDOWN_CTRL_REG,
+ SP_VIDEO_PD | SP_LINK_PD);
+
+ err = anx6345_tx_initialization(anx6345);
+ if (err) {
+ DRM_ERROR("Failed transmitter initialization: %d\n", err);
+ goto err_poweroff;
+ }
+
+ /*
+ * This delay seems to help keep the hardware in a good state. Without
+ * it, there are times where it fails silently.
+ */
+ usleep_range(10000, 15000);
+
+ return 0;
+
+err_poweroff:
+ DRM_ERROR("Failed DisplayPort transmitter initialization: %d\n", err);
+ anx6345_poweroff(anx6345);
+
+ return err;
+}
+
+static int anx6345_init_pdata(struct anx6345 *anx6345)
+{
+ struct anx6345_platform_data *pdata = &anx6345->pdata;
+ struct device *dev = &anx6345->client->dev;
+
+ /* 1.2V digital core power regulator */
+ pdata->dvdd12 = devm_regulator_get(dev, "dvdd12");
+ if (IS_ERR(pdata->dvdd12)) {
+ DRM_ERROR("DVDD12 regulator not found\n");
+ return PTR_ERR(pdata->dvdd12);
+ }
+
+ /* 2.5V digital core power regulator */
+ pdata->dvdd25 = devm_regulator_get(dev, "dvdd25");
+ if (IS_ERR(pdata->dvdd25)) {
+ DRM_ERROR("DVDD25 regulator not found\n");
+ return PTR_ERR(pdata->dvdd25);
+ }
+
+ /* panel power regulator */
+ pdata->vcc_panel = devm_regulator_get(dev, "panel");
+ if (IS_ERR(pdata->vcc_panel)) {
+ DRM_ERROR("panel regulator not found\n");
+ return PTR_ERR(pdata->vcc_panel);
+ }
+
+ /* GPIO for chip reset */
+ pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+
+ return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
+}
+
+static int anx6345_config_dp_output(struct anx6345 *anx6345)
+{
+ int err;
+
+ err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG,
+ SP_VIDEO_MUTE);
+ if (err)
+ return err;
+
+ /* Enable DP output */
+ err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG,
+ SP_VIDEO_EN);
+ if (err)
+ return err;
+
+ /* Force stream valid */
+ err = anx6345_set_bits(anx6345->map[I2C_IDX_DPTX],
+ SP_DP_SYSTEM_CTRL_BASE + 3,
+ SP_STRM_FORCE | SP_STRM_CTRL);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int anx6345_get_downstream_info(struct anx6345 *anx6345)
+{
+ u8 value;
+ int err;
+
+ err = drm_dp_dpcd_readb(&anx6345->aux, DP_SINK_COUNT, &value);
+ if (err < 0) {
+ DRM_ERROR("Get sink count failed %d\n", err);
+ return err;
+ }
+
+ if (!DP_GET_SINK_COUNT(value)) {
+ DRM_ERROR("Downstream disconnected\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int anx6345_probe_edid_from_of(struct anx6345 *anx6345)
+{
+ const u8 *edidp;
+ int len;
+
+ if (!anx6345->bridge.of_node)
+ return -ENODEV;
+
+ edidp = of_get_property(anx6345->bridge.of_node, "edid", &len);
+ if (!edidp || len != EDID_LENGTH)
+ return -EINVAL;
+
+ anx6345->edid = devm_kmemdup(&anx6345->client->dev, edidp,
+ len, GFP_KERNEL);
+
+ if (!anx6345->edid)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int anx6345_get_modes(struct drm_connector *connector)
+{
+ struct anx6345 *anx6345 = connector_to_anx6345(connector);
+ int err, num_modes = 0;
+
+ if (WARN_ON(!anx6345->powered))
+ return 0;
+
+ if (anx6345->edid)
+ return drm_add_edid_modes(connector, anx6345->edid);
+
+ mutex_lock(&anx6345->lock);
+
+ err = anx6345_get_downstream_info(anx6345);
+ if (err) {
+ DRM_ERROR("Failed to get downstream info: %d\n", err);
+ goto unlock;
+ }
+
+ anx6345->edid = drm_get_edid(connector, &anx6345->aux.ddc);
+ if (!anx6345->edid)
+ DRM_ERROR("Failed to read EDID from panel\n");
+
+ if (!anx6345->edid) {
+ err = anx6345_probe_edid_from_of(anx6345);
+ if (err) {
+ DRM_ERROR("Failed to probe EDID from device tree\n");
+ goto unlock;
+ }
+ }
+
+ err = drm_connector_update_edid_property(connector,
+ anx6345->edid);
+ if (err) {
+ DRM_ERROR("Failed to update EDID property: %d\n", err);
+ goto unlock;
+ }
+
+ num_modes = drm_add_edid_modes(connector, anx6345->edid);
+
+unlock:
+ mutex_unlock(&anx6345->lock);
+
+ return num_modes;
+}
+
+static const struct drm_connector_helper_funcs anx6345_connector_helper_funcs = {
+ .get_modes = anx6345_get_modes,
+};
+
+static enum drm_connector_status anx6345_detect(struct drm_connector *connector,
+ bool force)
+{
+ return connector_status_connected;
+}
+
+static const struct drm_connector_funcs anx6345_connector_funcs = {
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = anx6345_detect,
+ .destroy = drm_connector_cleanup,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int anx6345_bridge_attach(struct drm_bridge *bridge)
+{
+ struct anx6345 *anx6345 = bridge_to_anx6345(bridge);
+ int err;
+
+ if (!bridge->encoder) {
+ DRM_ERROR("Parent encoder object not found");
+ return -ENODEV;
+ }
+
+ /* Register aux channel */
+ anx6345->aux.name = "DP-AUX";
+ anx6345->aux.dev = &anx6345->client->dev;
+ anx6345->aux.transfer = anx6345_aux_transfer;
+
+ err = drm_dp_aux_register(&anx6345->aux);
+ if (err < 0) {
+ DRM_ERROR("Failed to register aux channel: %d\n", err);
+ return err;
+ }
+
+ err = drm_connector_init(bridge->dev, &anx6345->connector,
+ &anx6345_connector_funcs,
+ DRM_MODE_CONNECTOR_eDP);
+ if (err) {
+ DRM_ERROR("Failed to initialize connector: %d\n", err);
+ return err;
+ }
+
+ drm_connector_helper_add(&anx6345->connector,
+ &anx6345_connector_helper_funcs);
+
+ err = drm_connector_register(&anx6345->connector);
+ if (err) {
+ DRM_ERROR("Failed to register connector: %d\n", err);
+ return err;
+ }
+
+ anx6345->connector.polled = DRM_CONNECTOR_POLL_HPD;
+
+ err = drm_connector_attach_encoder(&anx6345->connector,
+ bridge->encoder);
+ if (err) {
+ DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static bool anx6345_bridge_mode_fixup(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ return false;
+
+ /* Max 1200p at 5.4 Ghz, one lane */
+ if (mode->clock > 154000)
+ return false;
+
+ return true;
+}
+
+static void anx6345_bridge_disable(struct drm_bridge *bridge)
+{
+ struct anx6345 *anx6345 = bridge_to_anx6345(bridge);
+
+ /* Power off all modules except configuration registers access */
+ anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG,
+ SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
+}
+
+static void anx6345_bridge_mode_set(struct drm_bridge *bridge,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct anx6345 *anx6345 = bridge_to_anx6345(bridge);
+
+ if (WARN_ON(!anx6345->powered))
+ return;
+}
+
+static void anx6345_bridge_enable(struct drm_bridge *bridge)
+{
+ struct anx6345 *anx6345 = bridge_to_anx6345(bridge);
+ int err;
+
+ err = anx6345_start(anx6345);
+ if (err) {
+ DRM_ERROR("Failed to initialize: %d\n", err);
+ return;
+ }
+
+ err = anx6345_config_dp_output(anx6345);
+ if (err)
+ DRM_ERROR("Failed to enable DP output: %d\n", err);
+}
+
+static const struct drm_bridge_funcs anx6345_bridge_funcs = {
+ .attach = anx6345_bridge_attach,
+ .mode_fixup = anx6345_bridge_mode_fixup,
+ .disable = anx6345_bridge_disable,
+ .mode_set = anx6345_bridge_mode_set,
+ .enable = anx6345_bridge_enable,
+};
+
+static void unregister_i2c_dummy_clients(struct anx6345 *anx6345)
+{
+ unsigned int i;
+
+ for (i = 1; i < ARRAY_SIZE(anx6345->i2c_clients); i++)
+ if (anx6345->i2c_clients[i] &&
+ anx6345->i2c_clients[i]->addr != anx6345->client->addr)
+ i2c_unregister_device(anx6345->i2c_clients[i]);
+}
+
+static const struct regmap_config anx6345_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0xff,
+};
+
+static const u16 anx6345_chipid_list[] = {
+ 0x6345,
+};
+
+static int anx6345_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct anx6345 *anx6345;
+ struct anx6345_platform_data *pdata;
+ unsigned int i, idl, idh, version;
+ bool found = false;
+ int err;
+
+ anx6345 = devm_kzalloc(&client->dev, sizeof(*anx6345), GFP_KERNEL);
+ if (!anx6345)
+ return -ENOMEM;
+
+ pdata = &anx6345->pdata;
+
+ mutex_init(&anx6345->lock);
+
+#if IS_ENABLED(CONFIG_OF)
+ anx6345->bridge.of_node = client->dev.of_node;
+#endif
+
+ anx6345->client = client;
+ i2c_set_clientdata(client, anx6345);
+
+ err = anx6345_init_pdata(anx6345);
+ if (err) {
+ DRM_ERROR("Failed to initialize pdata: %d\n", err);
+ return err;
+ }
+
+ /* Map slave addresses of ANX6345 */
+ for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
+ if (anx6345_i2c_addresses[i] >> 1 != client->addr)
+ anx6345->i2c_clients[i] = i2c_new_dummy(client->adapter,
+ anx6345_i2c_addresses[i] >> 1);
+ else
+ anx6345->i2c_clients[i] = client;
+
+ if (!anx6345->i2c_clients[i]) {
+ err = -ENOMEM;
+ DRM_ERROR("Failed to reserve I2C bus %02x\n",
+ anx6345_i2c_addresses[i]);
+ goto err_unregister_i2c;
+ }
+
+ anx6345->map[i] = devm_regmap_init_i2c(anx6345->i2c_clients[i],
+ &anx6345_regmap_config);
+ if (IS_ERR(anx6345->map[i])) {
+ err = PTR_ERR(anx6345->map[i]);
+ DRM_ERROR("Failed regmap initialization %02x\n",
+ anx6345_i2c_addresses[i]);
+ goto err_unregister_i2c;
+ }
+ }
+
+ /* Look for supported chip ID */
+ anx6345_poweron(anx6345);
+
+ err = regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_IDL_REG,
+ &idl);
+ if (err)
+ goto err_poweroff;
+
+ err = regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_IDH_REG,
+ &idh);
+ if (err)
+ goto err_poweroff;
+
+ anx6345->chipid = (u8)idl | ((u8)idh << 8);
+
+ err = regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_VERSION_REG,
+ &version);
+ if (err)
+ goto err_poweroff;
+
+ for (i = 0; i < ARRAY_SIZE(anx6345_chipid_list); i++) {
+ if (anx6345->chipid == anx6345_chipid_list[i]) {
+ DRM_INFO("Found ANX%x (ver. %d) eDP Transmitter\n",
+ anx6345->chipid, version);
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
+ anx6345->chipid, version);
+ err = -ENODEV;
+ goto err_poweroff;
+ }
+
+ anx6345->bridge.funcs = &anx6345_bridge_funcs;
+
+ drm_bridge_add(&anx6345->bridge);
+
+ return 0;
+
+err_poweroff:
+ anx6345_poweroff(anx6345);
+
+err_unregister_i2c:
+ unregister_i2c_dummy_clients(anx6345);
+ return err;
+}
+
+static int anx6345_i2c_remove(struct i2c_client *client)
+{
+ struct anx6345 *anx6345 = i2c_get_clientdata(client);
+
+ drm_bridge_remove(&anx6345->bridge);
+
+ unregister_i2c_dummy_clients(anx6345);
+
+ kfree(anx6345->edid);
+
+ return 0;
+}
+
+static const struct i2c_device_id anx6345_id[] = {
+ { "anx6345", 0 },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(i2c, anx6345_id);
+
+#if IS_ENABLED(CONFIG_OF)
+static const struct of_device_id anx6345_match_table[] = {
+ { .compatible = "analogix,anx6345", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, anx6345_match_table);
+#endif
+
+static struct i2c_driver anx6345_driver = {
+ .driver = {
+ .name = "anx6345",
+ .of_match_table = of_match_ptr(anx6345_match_table),
+ },
+ .probe = anx6345_i2c_probe,
+ .remove = anx6345_i2c_remove,
+ .id_table = anx6345_id,
+};
+module_i2c_driver(anx6345_driver);
+
+MODULE_DESCRIPTION("ANX6345 eDP Transmitter driver");
+MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c
index 9cb30962032e..53b0e73d6a24 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c
@@ -117,7 +117,7 @@ ssize_t anx_aux_transfer(struct regmap *map_dptx, struct drm_dp_aux_msg *msg)
else /* For non-zero-sized set the length field. */
ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
- if ((msg->request & DP_AUX_I2C_READ) == 0) {
+ if ((msg->size > 0) && ((msg->request & DP_AUX_I2C_READ) == 0)) {
/* When WRITE | MOT write values to data buffer */
err = regmap_bulk_write(map_dptx,
SP_DP_BUF_DATA0_REG, buffer,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
index c2ca854613a0..b29a0b3bc23c 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
@@ -75,7 +75,11 @@
#define SP_CHA_STA BIT(2)
/* Bits for DP System Control Register 3 */
#define SP_HPD_STATUS BIT(6)
+#define SP_HPD_FORCE BIT(5)
+#define SP_HPD_CTRL BIT(4)
#define SP_STRM_VALID BIT(2)
+#define SP_STRM_FORCE BIT(1)
+#define SP_STRM_CTRL BIT(0)
/* Bits for DP System Control Register 4 */
#define SP_ENHANCED_MODE BIT(3)
@@ -120,6 +124,9 @@
#define SP_LINK_BW_SET_MASK 0x1f
#define SP_INITIAL_SLIM_M_AUD_SEL BIT(5)
+/* DP Lane Count Setting Register */
+#define SP_DP_LANE_COUNT_SET_REG 0xa1
+
/* DP Training Pattern Set Register */
#define SP_DP_TRAINING_PATTERN_SET_REG 0xa2
@@ -133,6 +140,7 @@
/* DP Link Training Control Register */
#define SP_DP_LT_CTRL_REG 0xa8
+#define SP_DP_LT_INPROGRESS 0x80
#define SP_LT_ERROR_TYPE_MASK 0x70
# define SP_LT_NO_ERROR 0x00
# define SP_LT_AUX_WRITE_ERROR 0x01
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h b/drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h
index 7d683573e970..480c98a225b1 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h
@@ -183,6 +183,9 @@
#define SP_VBIT BIT(1)
#define SP_AUDIO_LAYOUT BIT(0)
+/* Analog Debug Register 1 */
+#define SP_ANALOG_DEBUG1_REG 0xdc
+
/* Analog Debug Register 2 */
#define SP_ANALOG_DEBUG2_REG 0xdd
#define SP_FORCE_SW_OFF_BYPASS 0x20
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 6/9] arm64: allwinner: a64: add pinmux for RGB666 LCD
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
` (4 preceding siblings ...)
2018-10-18 7:33 ` [PATCH 5/9] drm/bridge: Add Analogix anx6345 support Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 7:33 ` [PATCH 7/9] arm64: allwinner: a64: enable ANX6345 bridge on Pinebook Icenowy Zheng
` (4 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-sunxi, Icenowy Zheng
Allwinner A64's TCON0 can output RGB666 LCD signal.
Add its pinmux.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index f3a66f888205..9806cbf6cc64 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -518,6 +518,15 @@
function = "i2c1";
};
+ lcd_rgb666_pins: lcd-rgb666 {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD6", "PD7", "PD8", "PD9",
+ "PD10", "PD11", "PD12", "PD13",
+ "PD14", "PD15", "PD16", "PD17",
+ "PD18", "PD19", "PD20", "PD21";
+ function = "lcd0";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 7/9] arm64: allwinner: a64: enable ANX6345 bridge on Pinebook
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
` (5 preceding siblings ...)
2018-10-18 7:33 ` [PATCH 6/9] arm64: allwinner: a64: add pinmux for RGB666 LCD Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 15:17 ` Vasily Khoruzhick
2018-10-18 7:33 ` [PATCH 8/9] arm64: allwinner: a64: enable ANX6345 bridge on TERES-I Icenowy Zheng
` (3 subsequent siblings)
10 siblings, 1 reply; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-sunxi, Icenowy Zheng
Pinebook has an ANX6345 bridge connected to the RGB666 LCD output, and
the I2C controlling signals are connected to R_I2C bus.
Enable it in the device tree, and add a usable EDID from the panel's
datasheet (at least 14" Pinebook used a panel without EDID).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../dts/allwinner/sun50i-a64-pinebook.dts | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 77fac84797e9..d7c14d0d61f9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -66,6 +66,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
phys = <&usbphy 0>;
phy-names = "usb";
@@ -76,6 +80,10 @@
status = "okay";
};
+&mixer0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -127,6 +135,27 @@
status = "okay";
};
+&r_i2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins_a>;
+ status = "okay";
+
+ anx6345: anx6345@38 {
+ compatible = "analogix,anx6345";
+ reg = <0x38>;
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ panel-supply = <®_dc1sw>;
+ dvdd25-supply = <®_dldo2>;
+ dvdd12-supply = <®_fldo1>;
+
+ port {
+ anx6345_in: endpoint {
+ remote-endpoint = <&tcon0_out_anx6345>;
+ };
+ };
+ };
+};
+
&r_rsb {
status = "okay";
@@ -267,6 +296,20 @@
vcc-hdmi-supply = <®_dldo1>;
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+
+ status = "okay";
+};
+
+&tcon0_out {
+ tcon0_out_anx6345: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&anx6345_in>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 7/9] arm64: allwinner: a64: enable ANX6345 bridge on Pinebook
2018-10-18 7:33 ` [PATCH 7/9] arm64: allwinner: a64: enable ANX6345 bridge on Pinebook Icenowy Zheng
@ 2018-10-18 15:17 ` Vasily Khoruzhick
2018-10-19 5:50 ` Icenowy Zheng
0 siblings, 1 reply; 32+ messages in thread
From: Vasily Khoruzhick @ 2018-10-18 15:17 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Icenowy Zheng, David Airlie, Rob Herring, Maxime Ripard,
Chen-Yu Tsai, Archit Taneja, Andrzej Hajda, Laurent Pinchart,
devicetree, linux-kernel, dri-devel, linux-sunxi
Hi Icenowy,
On Thursday, October 18, 2018 12:33:25 AM PDT Icenowy Zheng wrote:
> Pinebook has an ANX6345 bridge connected to the RGB666 LCD output, and
> the I2C controlling signals are connected to R_I2C bus.
>
> Enable it in the device tree, and add a usable EDID from the panel's
> datasheet (at least 14" Pinebook used a panel without EDID).
There's no EDID in dts and 14" Pinebook uses a panel with EDID. Is it leftover
of old comment?
Regards,
Vasily
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> .../dts/allwinner/sun50i-a64-pinebook.dts | 43 +++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index
> 77fac84797e9..d7c14d0d61f9 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
> @@ -66,6 +66,10 @@
> };
> };
>
> +&de {
> + status = "okay";
> +};
> +
> &ehci0 {
> phys = <&usbphy 0>;
> phy-names = "usb";
> @@ -76,6 +80,10 @@
> status = "okay";
> };
>
> +&mixer0 {
> + status = "okay";
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins>;
> @@ -127,6 +135,27 @@
> status = "okay";
> };
>
> +&r_i2c {
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_i2c_pins_a>;
> + status = "okay";
> +
> + anx6345: anx6345@38 {
> + compatible = "analogix,anx6345";
> + reg = <0x38>;
> + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
> + panel-supply = <®_dc1sw>;
> + dvdd25-supply = <®_dldo2>;
> + dvdd12-supply = <®_fldo1>;
> +
> + port {
> + anx6345_in: endpoint {
> + remote-endpoint = <&tcon0_out_anx6345>;
> + };
> + };
> + };
> +};
> +
> &r_rsb {
> status = "okay";
>
> @@ -267,6 +296,20 @@
> vcc-hdmi-supply = <®_dldo1>;
> };
>
> +&tcon0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_rgb666_pins>;
> +
> + status = "okay";
> +};
> +
> +&tcon0_out {
> + tcon0_out_anx6345: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&anx6345_in>;
> + };
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_pb_pins>;
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 7/9] arm64: allwinner: a64: enable ANX6345 bridge on Pinebook
2018-10-18 15:17 ` Vasily Khoruzhick
@ 2018-10-19 5:50 ` Icenowy Zheng
0 siblings, 0 replies; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-19 5:50 UTC (permalink / raw)
To: Vasily Khoruzhick, linux-arm-kernel
Cc: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart, devicetree,
linux-kernel, dri-devel, linux-sunxi
于 2018年10月18日 GMT+08:00 下午11:17:35, Vasily Khoruzhick <anarsoul@gmail.com> 写到:
>Hi Icenowy,
>
>On Thursday, October 18, 2018 12:33:25 AM PDT Icenowy Zheng wrote:
>> Pinebook has an ANX6345 bridge connected to the RGB666 LCD output,
>and
>> the I2C controlling signals are connected to R_I2C bus.
>>
>> Enable it in the device tree, and add a usable EDID from the panel's
>> datasheet (at least 14" Pinebook used a panel without EDID).
>
>There's no EDID in dts and 14" Pinebook uses a panel with EDID. Is it
>leftover
>of old comment?
Yes, it is.
>
>Regards,
>Vasily
>
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> .../dts/allwinner/sun50i-a64-pinebook.dts | 43
>+++++++++++++++++++
>> 1 file changed, 43 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>> b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index
>> 77fac84797e9..d7c14d0d61f9 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>> @@ -66,6 +66,10 @@
>> };
>> };
>>
>> +&de {
>> + status = "okay";
>> +};
>> +
>> &ehci0 {
>> phys = <&usbphy 0>;
>> phy-names = "usb";
>> @@ -76,6 +80,10 @@
>> status = "okay";
>> };
>>
>> +&mixer0 {
>> + status = "okay";
>> +};
>> +
>> &mmc0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&mmc0_pins>;
>> @@ -127,6 +135,27 @@
>> status = "okay";
>> };
>>
>> +&r_i2c {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&r_i2c_pins_a>;
>> + status = "okay";
>> +
>> + anx6345: anx6345@38 {
>> + compatible = "analogix,anx6345";
>> + reg = <0x38>;
>> + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
>> + panel-supply = <®_dc1sw>;
>> + dvdd25-supply = <®_dldo2>;
>> + dvdd12-supply = <®_fldo1>;
>> +
>> + port {
>> + anx6345_in: endpoint {
>> + remote-endpoint = <&tcon0_out_anx6345>;
>> + };
>> + };
>> + };
>> +};
>> +
>> &r_rsb {
>> status = "okay";
>>
>> @@ -267,6 +296,20 @@
>> vcc-hdmi-supply = <®_dldo1>;
>> };
>>
>> +&tcon0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&lcd_rgb666_pins>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&tcon0_out {
>> + tcon0_out_anx6345: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&anx6345_in>;
>> + };
>> +};
>> +
>> &uart0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&uart0_pb_pins>;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 8/9] arm64: allwinner: a64: enable ANX6345 bridge on TERES-I
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
` (6 preceding siblings ...)
2018-10-18 7:33 ` [PATCH 7/9] arm64: allwinner: a64: enable ANX6345 bridge on Pinebook Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 7:33 ` [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check Icenowy Zheng
` (2 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-sunxi, Icenowy Zheng
TERES-I has an ANX6345 bridge connected to the RGB666 LCD output, and
the I2C controlling signals are connected to I2C0 bus.
Enable it in the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../boot/dts/allwinner/sun50i-a64-teres-i.dts | 40 +++++++++++++++++--
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
index c455b24dd079..bc1d0d6c0672 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
@@ -72,20 +72,38 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
-/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline)
- * driver for this chip at the moment, the bootloader initializes it.
- * However it can be accessed with the i2c-dev driver from user space.
- */
&i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
+
+ anx6345: anx6345@38 {
+ compatible = "analogix,anx6345";
+ reg = <0x38>;
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ dvdd25-supply = <®_dldo2>;
+ dvdd12-supply = <®_dldo3>;
+
+ port {
+ anx6345_in: endpoint {
+ remote-endpoint = <&tcon0_out_anx6345>;
+ };
+ };
+ };
+};
+
+&mixer0 {
+ status = "okay";
};
&mmc0 {
@@ -258,6 +276,20 @@
vcc-hdmi-supply = <®_dldo1>;
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+
+ status = "okay";
+};
+
+&tcon0_out {
+ tcon0_out_anx6345: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&anx6345_in>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
` (7 preceding siblings ...)
2018-10-18 7:33 ` [PATCH 8/9] arm64: allwinner: a64: enable ANX6345 bridge on TERES-I Icenowy Zheng
@ 2018-10-18 7:33 ` Icenowy Zheng
2018-10-18 8:55 ` Laurent Pinchart
2018-10-29 2:20 ` [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Vasily Khoruzhick
2019-02-04 12:22 ` Torsten Duwe
10 siblings, 1 reply; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 7:33 UTC (permalink / raw)
To: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-sunxi
From: Chen-Yu Tsai <wens@csie.org>
The panels shipped with Allwinner devices are very "generic", i.e.
they do not have model numbers or reliable sources of information
for the timings (that we know of) other than the fex files shipped
on them. The dot clock frequency provided in the fex files have all
been rounded to the nearest MHz, as that is the unit used in them.
We were using the simple panel "urt,umsh-8596md-t" as a substitute
for the A13 Q8 tablets in the absence of a specific model for what
may be many different but otherwise timing compatible panels. This
was usable without any visual artifacts or side effects, until the
dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
rgb: Validate the clock rate").
The reason this check fails is because the dotclock frequency for
this model is 33.26 MHz, which is not achievable with our dot clock
hardware, and the rate returned by clk_round_rate deviates slightly,
causing the driver to reject the display mode.
The LCD panels have some tolerance on the dot clock frequency, even
if it's not specified in their datasheets.
This patch adds a 5% tolerence to the dot clock check.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index bf068da6b12e..23bdc449eacc 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -92,13 +92,14 @@ static enum drm_mode_status sun4i_rgb_mode_valid(struct drm_encoder *crtc,
DRM_DEBUG_DRIVER("Vertical parameters OK\n");
+ /* Check against a 5% tolerance for the dot clock */
tcon->dclk_min_div = 6;
tcon->dclk_max_div = 127;
rounded_rate = clk_round_rate(tcon->dclk, rate);
- if (rounded_rate < rate)
+ if (rounded_rate < rate * 19 / 20 )
return MODE_CLOCK_LOW;
- if (rounded_rate > rate)
+ if (rounded_rate > rate * 21 / 20)
return MODE_CLOCK_HIGH;
DRM_DEBUG_DRIVER("Clock rate OK\n");
--
2.18.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 7:33 ` [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check Icenowy Zheng
@ 2018-10-18 8:55 ` Laurent Pinchart
2018-10-18 9:18 ` Daniel Vetter
0 siblings, 1 reply; 32+ messages in thread
From: Laurent Pinchart @ 2018-10-18 8:55 UTC (permalink / raw)
To: Icenowy Zheng
Cc: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-sunxi
Hi Icenowy,
Thank you for the patch.
On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The panels shipped with Allwinner devices are very "generic", i.e.
> they do not have model numbers or reliable sources of information
> for the timings (that we know of) other than the fex files shipped
> on them. The dot clock frequency provided in the fex files have all
> been rounded to the nearest MHz, as that is the unit used in them.
>
> We were using the simple panel "urt,umsh-8596md-t" as a substitute
> for the A13 Q8 tablets in the absence of a specific model for what
> may be many different but otherwise timing compatible panels. This
> was usable without any visual artifacts or side effects, until the
> dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> rgb: Validate the clock rate").
>
> The reason this check fails is because the dotclock frequency for
> this model is 33.26 MHz, which is not achievable with our dot clock
> hardware, and the rate returned by clk_round_rate deviates slightly,
> causing the driver to reject the display mode.
>
> The LCD panels have some tolerance on the dot clock frequency, even
> if it's not specified in their datasheets.
>
> This patch adds a 5% tolerence to the dot clock check.
Why do you think this shouldn't be merged ?
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> drivers/gpu/drm/sun4i/sun4i_rgb.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c
> b/drivers/gpu/drm/sun4i/sun4i_rgb.c index bf068da6b12e..23bdc449eacc 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
> @@ -92,13 +92,14 @@ static enum drm_mode_status sun4i_rgb_mode_valid(struct
> drm_encoder *crtc,
>
> DRM_DEBUG_DRIVER("Vertical parameters OK\n");
>
> + /* Check against a 5% tolerance for the dot clock */
> tcon->dclk_min_div = 6;
> tcon->dclk_max_div = 127;
> rounded_rate = clk_round_rate(tcon->dclk, rate);
> - if (rounded_rate < rate)
> + if (rounded_rate < rate * 19 / 20 )
> return MODE_CLOCK_LOW;
>
> - if (rounded_rate > rate)
> + if (rounded_rate > rate * 21 / 20)
> return MODE_CLOCK_HIGH;
>
> DRM_DEBUG_DRIVER("Clock rate OK\n");
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 8:55 ` Laurent Pinchart
@ 2018-10-18 9:18 ` Daniel Vetter
2018-10-18 9:42 ` Maxime Ripard
0 siblings, 1 reply; 32+ messages in thread
From: Daniel Vetter @ 2018-10-18 9:18 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Icenowy Zheng, devicetree, Dave Airlie, linux-sunxi,
Linux Kernel Mailing List, dri-devel, Maxime Ripard,
Chen-Yu Tsai, Rob Herring, Linux ARM
On Thu, Oct 18, 2018 at 10:55 AM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> Hi Icenowy,
>
> Thank you for the patch.
>
> On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng wrote:
> > From: Chen-Yu Tsai <wens@csie.org>
> >
> > The panels shipped with Allwinner devices are very "generic", i.e.
> > they do not have model numbers or reliable sources of information
> > for the timings (that we know of) other than the fex files shipped
> > on them. The dot clock frequency provided in the fex files have all
> > been rounded to the nearest MHz, as that is the unit used in them.
> >
> > We were using the simple panel "urt,umsh-8596md-t" as a substitute
> > for the A13 Q8 tablets in the absence of a specific model for what
> > may be many different but otherwise timing compatible panels. This
> > was usable without any visual artifacts or side effects, until the
> > dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> > rgb: Validate the clock rate").
> >
> > The reason this check fails is because the dotclock frequency for
> > this model is 33.26 MHz, which is not achievable with our dot clock
> > hardware, and the rate returned by clk_round_rate deviates slightly,
> > causing the driver to reject the display mode.
> >
> > The LCD panels have some tolerance on the dot clock frequency, even
> > if it's not specified in their datasheets.
> >
> > This patch adds a 5% tolerence to the dot clock check.
>
> Why do you think this shouldn't be merged ?
It pisses of a lot of people who really insist upon accurate timing. I
think a better fix would be to have a dotclock range in drm_panel, and
some magic to figure out which one of these we can actually do. Then
tell userspace that this is the mode is should request. That way
userspace knows what the actual dotclock/refresh rate is, and the
panel still works.
-Daniel
>
> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> > ---
> > drivers/gpu/drm/sun4i/sun4i_rgb.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c
> > b/drivers/gpu/drm/sun4i/sun4i_rgb.c index bf068da6b12e..23bdc449eacc 100644
> > --- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
> > +++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
> > @@ -92,13 +92,14 @@ static enum drm_mode_status sun4i_rgb_mode_valid(struct
> > drm_encoder *crtc,
> >
> > DRM_DEBUG_DRIVER("Vertical parameters OK\n");
> >
> > + /* Check against a 5% tolerance for the dot clock */
> > tcon->dclk_min_div = 6;
> > tcon->dclk_max_div = 127;
> > rounded_rate = clk_round_rate(tcon->dclk, rate);
> > - if (rounded_rate < rate)
> > + if (rounded_rate < rate * 19 / 20 )
> > return MODE_CLOCK_LOW;
> >
> > - if (rounded_rate > rate)
> > + if (rounded_rate > rate * 21 / 20)
> > return MODE_CLOCK_HIGH;
> >
> > DRM_DEBUG_DRIVER("Clock rate OK\n");
>
> --
> Regards,
>
> Laurent Pinchart
>
>
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 9:18 ` Daniel Vetter
@ 2018-10-18 9:42 ` Maxime Ripard
2018-10-18 11:31 ` Laurent Pinchart
0 siblings, 1 reply; 32+ messages in thread
From: Maxime Ripard @ 2018-10-18 9:42 UTC (permalink / raw)
To: Daniel Vetter
Cc: Laurent Pinchart, Icenowy Zheng, devicetree, Dave Airlie,
linux-sunxi, Linux Kernel Mailing List, dri-devel, Chen-Yu Tsai,
Rob Herring, Linux ARM
[-- Attachment #1: Type: text/plain, Size: 2686 bytes --]
On Thu, Oct 18, 2018 at 11:18:06AM +0200, Daniel Vetter wrote:
> On Thu, Oct 18, 2018 at 10:55 AM Laurent Pinchart
> <laurent.pinchart@ideasonboard.com> wrote:
> >
> > Hi Icenowy,
> >
> > Thank you for the patch.
> >
> > On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng wrote:
> > > From: Chen-Yu Tsai <wens@csie.org>
> > >
> > > The panels shipped with Allwinner devices are very "generic", i.e.
> > > they do not have model numbers or reliable sources of information
> > > for the timings (that we know of) other than the fex files shipped
> > > on them. The dot clock frequency provided in the fex files have all
> > > been rounded to the nearest MHz, as that is the unit used in them.
> > >
> > > We were using the simple panel "urt,umsh-8596md-t" as a substitute
> > > for the A13 Q8 tablets in the absence of a specific model for what
> > > may be many different but otherwise timing compatible panels. This
> > > was usable without any visual artifacts or side effects, until the
> > > dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> > > rgb: Validate the clock rate").
> > >
> > > The reason this check fails is because the dotclock frequency for
> > > this model is 33.26 MHz, which is not achievable with our dot clock
> > > hardware, and the rate returned by clk_round_rate deviates slightly,
> > > causing the driver to reject the display mode.
> > >
> > > The LCD panels have some tolerance on the dot clock frequency, even
> > > if it's not specified in their datasheets.
> > >
> > > This patch adds a 5% tolerence to the dot clock check.
> >
> > Why do you think this shouldn't be merged ?
>
> It pisses of a lot of people who really insist upon accurate timing.
It's not just about accurate timings. That 5% is a made-up limit, that
never have really been confirmed by looking at the typical tolerancies
of panels.
And while being to relaxed might make some panels work that are not
working currently, it might also break some panels that currently work
and won't now, and ideally, we should really be able to let those
panels work if they can, and filter out resolutions if they can't.
> I think a better fix would be to have a dotclock range in drm_panel,
> and some magic to figure out which one of these we can actually
> do. Then tell userspace that this is the mode is should
> request. That way userspace knows what the actual dotclock/refresh
> rate is, and the panel still works.
It's not just about panels, but also bridges with EDID where the
tolerancy is not exposed.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 9:42 ` Maxime Ripard
@ 2018-10-18 11:31 ` Laurent Pinchart
2018-10-18 12:18 ` Maxime Ripard
2019-02-03 1:32 ` Vasily Khoruzhick
0 siblings, 2 replies; 32+ messages in thread
From: Laurent Pinchart @ 2018-10-18 11:31 UTC (permalink / raw)
To: Maxime Ripard
Cc: Daniel Vetter, Icenowy Zheng, devicetree, Dave Airlie,
linux-sunxi, Linux Kernel Mailing List, dri-devel, Chen-Yu Tsai,
Rob Herring, Linux ARM
Hello,
On Thursday, 18 October 2018 12:42:58 EEST Maxime Ripard wrote:
> On Thu, Oct 18, 2018 at 11:18:06AM +0200, Daniel Vetter wrote:
> > On Thu, Oct 18, 2018 at 10:55 AM Laurent Pinchart wrote:
> >> On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng wrote:
> >>> From: Chen-Yu Tsai <wens@csie.org>
> >>>
> >>> The panels shipped with Allwinner devices are very "generic", i.e.
> >>> they do not have model numbers or reliable sources of information
> >>> for the timings (that we know of) other than the fex files shipped
> >>> on them. The dot clock frequency provided in the fex files have all
> >>> been rounded to the nearest MHz, as that is the unit used in them.
> >>>
> >>> We were using the simple panel "urt,umsh-8596md-t" as a substitute
> >>> for the A13 Q8 tablets in the absence of a specific model for what
> >>> may be many different but otherwise timing compatible panels. This
> >>> was usable without any visual artifacts or side effects, until the
> >>> dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> >>> rgb: Validate the clock rate").
> >>>
> >>> The reason this check fails is because the dotclock frequency for
> >>> this model is 33.26 MHz, which is not achievable with our dot clock
> >>> hardware, and the rate returned by clk_round_rate deviates slightly,
> >>> causing the driver to reject the display mode.
> >>>
> >>> The LCD panels have some tolerance on the dot clock frequency, even
> >>> if it's not specified in their datasheets.
> >>>
> >>> This patch adds a 5% tolerence to the dot clock check.
> >>
> >> Why do you think this shouldn't be merged ?
> >
> > It pisses of a lot of people who really insist upon accurate timing.
>
> It's not just about accurate timings. That 5% is a made-up limit, that
> never have really been confirmed by looking at the typical tolerancies
> of panels.
>
> And while being to relaxed might make some panels work that are not
> working currently, it might also break some panels that currently work
> and won't now, and ideally, we should really be able to let those
> panels work if they can, and filter out resolutions if they can't.
>
> > I think a better fix would be to have a dotclock range in drm_panel,
> > and some magic to figure out which one of these we can actually
> > do. Then tell userspace that this is the mode is should
> > request. That way userspace knows what the actual dotclock/refresh
> > rate is, and the panel still works.
>
> It's not just about panels, but also bridges with EDID where the
> tolerancy is not exposed.
Given that the tolerance is a property of the panel or bridge, I agree with
Daniel that it should be implemented there, or at least in cooperation with
drm_panel and drm_bridge.
Semi-related information, I think the CEA and VESA standards allow a 0.5%
clock tolerance. What is the maximum clock frequency deviation required for
this platform ?
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 11:31 ` Laurent Pinchart
@ 2018-10-18 12:18 ` Maxime Ripard
2018-10-18 12:50 ` Icenowy Zheng
2018-10-18 13:57 ` Laurent Pinchart
2019-02-03 1:32 ` Vasily Khoruzhick
1 sibling, 2 replies; 32+ messages in thread
From: Maxime Ripard @ 2018-10-18 12:18 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Daniel Vetter, Icenowy Zheng, devicetree, Dave Airlie,
linux-sunxi, Linux Kernel Mailing List, dri-devel, Chen-Yu Tsai,
Rob Herring, Linux ARM
On Thu, Oct 18, 2018 at 02:31:01PM +0300, Laurent Pinchart wrote:
> Hello,
>
> On Thursday, 18 October 2018 12:42:58 EEST Maxime Ripard wrote:
> > On Thu, Oct 18, 2018 at 11:18:06AM +0200, Daniel Vetter wrote:
> > > On Thu, Oct 18, 2018 at 10:55 AM Laurent Pinchart wrote:
> > >> On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng wrote:
> > >>> From: Chen-Yu Tsai <wens@csie.org>
> > >>>
> > >>> The panels shipped with Allwinner devices are very "generic", i.e.
> > >>> they do not have model numbers or reliable sources of information
> > >>> for the timings (that we know of) other than the fex files shipped
> > >>> on them. The dot clock frequency provided in the fex files have all
> > >>> been rounded to the nearest MHz, as that is the unit used in them.
> > >>>
> > >>> We were using the simple panel "urt,umsh-8596md-t" as a substitute
> > >>> for the A13 Q8 tablets in the absence of a specific model for what
> > >>> may be many different but otherwise timing compatible panels. This
> > >>> was usable without any visual artifacts or side effects, until the
> > >>> dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> > >>> rgb: Validate the clock rate").
> > >>>
> > >>> The reason this check fails is because the dotclock frequency for
> > >>> this model is 33.26 MHz, which is not achievable with our dot clock
> > >>> hardware, and the rate returned by clk_round_rate deviates slightly,
> > >>> causing the driver to reject the display mode.
> > >>>
> > >>> The LCD panels have some tolerance on the dot clock frequency, even
> > >>> if it's not specified in their datasheets.
> > >>>
> > >>> This patch adds a 5% tolerence to the dot clock check.
> > >>
> > >> Why do you think this shouldn't be merged ?
> > >
> > > It pisses of a lot of people who really insist upon accurate timing.
> >
> > It's not just about accurate timings. That 5% is a made-up limit, that
> > never have really been confirmed by looking at the typical tolerancies
> > of panels.
> >
> > And while being to relaxed might make some panels work that are not
> > working currently, it might also break some panels that currently work
> > and won't now, and ideally, we should really be able to let those
> > panels work if they can, and filter out resolutions if they can't.
> >
> > > I think a better fix would be to have a dotclock range in drm_panel,
> > > and some magic to figure out which one of these we can actually
> > > do. Then tell userspace that this is the mode is should
> > > request. That way userspace knows what the actual dotclock/refresh
> > > rate is, and the panel still works.
> >
> > It's not just about panels, but also bridges with EDID where the
> > tolerancy is not exposed.
>
> Given that the tolerance is a property of the panel or bridge, I agree with
> Daniel that it should be implemented there, or at least in cooperation with
> drm_panel and drm_bridge.
How are we supposed to deal with panels without any documentation then?
> Semi-related information, I think the CEA and VESA standards allow a 0.5%
> clock tolerance. What is the maximum clock frequency deviation required for
> this platform ?
Looks like it does indeed. That's definetely good to know.
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 12:18 ` Maxime Ripard
@ 2018-10-18 12:50 ` Icenowy Zheng
2018-10-18 13:07 ` Maxime Ripard
2018-10-18 13:57 ` Laurent Pinchart
1 sibling, 1 reply; 32+ messages in thread
From: Icenowy Zheng @ 2018-10-18 12:50 UTC (permalink / raw)
To: Maxime Ripard, Laurent Pinchart
Cc: devicetree, Dave Airlie, Linux Kernel Mailing List, dri-devel,
linux-sunxi, Rob Herring, Daniel Vetter, Chen-Yu Tsai, Linux ARM
在 2018-10-18四的 14:18 +0200，Maxime Ripard写道：
> On Thu, Oct 18, 2018 at 02:31:01PM +0300, Laurent Pinchart wrote:
> > Hello,
> >
> > On Thursday, 18 October 2018 12:42:58 EEST Maxime Ripard wrote:
> > > On Thu, Oct 18, 2018 at 11:18:06AM +0200, Daniel Vetter wrote:
> > > > On Thu, Oct 18, 2018 at 10:55 AM Laurent Pinchart wrote:
> > > > > On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng
> > > > > wrote:
> > > > > > From: Chen-Yu Tsai <wens@csie.org>
> > > > > >
> > > > > > The panels shipped with Allwinner devices are very
> > > > > > "generic", i.e.
> > > > > > they do not have model numbers or reliable sources of
> > > > > > information
> > > > > > for the timings (that we know of) other than the fex files
> > > > > > shipped
> > > > > > on them. The dot clock frequency provided in the fex files
> > > > > > have all
> > > > > > been rounded to the nearest MHz, as that is the unit used
> > > > > > in them.
> > > > > >
> > > > > > We were using the simple panel "urt,umsh-8596md-t" as a
> > > > > > substitute
> > > > > > for the A13 Q8 tablets in the absence of a specific model
> > > > > > for what
> > > > > > may be many different but otherwise timing compatible
> > > > > > panels. This
> > > > > > was usable without any visual artifacts or side effects,
> > > > > > until the
> > > > > > dot clock rate check was added in commit bb43d40d7c83
> > > > > > ("drm/sun4i:
> > > > > > rgb: Validate the clock rate").
> > > > > >
> > > > > > The reason this check fails is because the dotclock
> > > > > > frequency for
> > > > > > this model is 33.26 MHz, which is not achievable with our
> > > > > > dot clock
> > > > > > hardware, and the rate returned by clk_round_rate deviates
> > > > > > slightly,
> > > > > > causing the driver to reject the display mode.
> > > > > >
> > > > > > The LCD panels have some tolerance on the dot clock
> > > > > > frequency, even
> > > > > > if it's not specified in their datasheets.
> > > > > >
> > > > > > This patch adds a 5% tolerence to the dot clock check.
> > > > >
> > > > > Why do you think this shouldn't be merged ?
> > > >
> > > > It pisses of a lot of people who really insist upon accurate
> > > > timing.
> > >
> > > It's not just about accurate timings. That 5% is a made-up limit,
> > > that
> > > never have really been confirmed by looking at the typical
> > > tolerancies
> > > of panels.
> > >
> > > And while being to relaxed might make some panels work that are
> > > not
> > > working currently, it might also break some panels that currently
> > > work
> > > and won't now, and ideally, we should really be able to let those
> > > panels work if they can, and filter out resolutions if they
> > > can't.
> > >
> > > > I think a better fix would be to have a dotclock range in
> > > > drm_panel,
> > > > and some magic to figure out which one of these we can actually
> > > > do. Then tell userspace that this is the mode is should
> > > > request. That way userspace knows what the actual
> > > > dotclock/refresh
> > > > rate is, and the panel still works.
> > >
> > > It's not just about panels, but also bridges with EDID where the
> > > tolerancy is not exposed.
> >
> > Given that the tolerance is a property of the panel or bridge, I
> > agree with
> > Daniel that it should be implemented there, or at least in
> > cooperation with
> > drm_panel and drm_bridge.
>
> How are we supposed to deal with panels without any documentation
> then?
>
> > Semi-related information, I think the CEA and VESA standards allow
> > a 0.5%
> > clock tolerance. What is the maximum clock frequency deviation
> > required for
> > this platform ?
>
> Looks like it does indeed. That's definetely good to know.
Then maybe we can choose to allow 0.5% error when a bridge is attached?
>
> Thanks!
> Maxime
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 12:50 ` Icenowy Zheng
@ 2018-10-18 13:07 ` Maxime Ripard
0 siblings, 0 replies; 32+ messages in thread
From: Maxime Ripard @ 2018-10-18 13:07 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Laurent Pinchart, devicetree, Dave Airlie,
Linux Kernel Mailing List, dri-devel, linux-sunxi, Rob Herring,
Daniel Vetter, Chen-Yu Tsai, Linux ARM
On Thu, Oct 18, 2018 at 08:50:15PM +0800, Icenowy Zheng wrote:
> 在 2018-10-18四的 14:18 +0200，Maxime Ripard写道：
> > On Thu, Oct 18, 2018 at 02:31:01PM +0300, Laurent Pinchart wrote:
> > > Hello,
> > >
> > > On Thursday, 18 October 2018 12:42:58 EEST Maxime Ripard wrote:
> > > > On Thu, Oct 18, 2018 at 11:18:06AM +0200, Daniel Vetter wrote:
> > > > > On Thu, Oct 18, 2018 at 10:55 AM Laurent Pinchart wrote:
> > > > > > On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng
> > > > > > wrote:
> > > > > > > From: Chen-Yu Tsai <wens@csie.org>
> > > > > > >
> > > > > > > The panels shipped with Allwinner devices are very
> > > > > > > "generic", i.e.
> > > > > > > they do not have model numbers or reliable sources of
> > > > > > > information
> > > > > > > for the timings (that we know of) other than the fex files
> > > > > > > shipped
> > > > > > > on them. The dot clock frequency provided in the fex files
> > > > > > > have all
> > > > > > > been rounded to the nearest MHz, as that is the unit used
> > > > > > > in them.
> > > > > > >
> > > > > > > We were using the simple panel "urt,umsh-8596md-t" as a
> > > > > > > substitute
> > > > > > > for the A13 Q8 tablets in the absence of a specific model
> > > > > > > for what
> > > > > > > may be many different but otherwise timing compatible
> > > > > > > panels. This
> > > > > > > was usable without any visual artifacts or side effects,
> > > > > > > until the
> > > > > > > dot clock rate check was added in commit bb43d40d7c83
> > > > > > > ("drm/sun4i:
> > > > > > > rgb: Validate the clock rate").
> > > > > > >
> > > > > > > The reason this check fails is because the dotclock
> > > > > > > frequency for
> > > > > > > this model is 33.26 MHz, which is not achievable with our
> > > > > > > dot clock
> > > > > > > hardware, and the rate returned by clk_round_rate deviates
> > > > > > > slightly,
> > > > > > > causing the driver to reject the display mode.
> > > > > > >
> > > > > > > The LCD panels have some tolerance on the dot clock
> > > > > > > frequency, even
> > > > > > > if it's not specified in their datasheets.
> > > > > > >
> > > > > > > This patch adds a 5% tolerence to the dot clock check.
> > > > > >
> > > > > > Why do you think this shouldn't be merged ?
> > > > >
> > > > > It pisses of a lot of people who really insist upon accurate
> > > > > timing.
> > > >
> > > > It's not just about accurate timings. That 5% is a made-up limit,
> > > > that
> > > > never have really been confirmed by looking at the typical
> > > > tolerancies
> > > > of panels.
> > > >
> > > > And while being to relaxed might make some panels work that are
> > > > not
> > > > working currently, it might also break some panels that currently
> > > > work
> > > > and won't now, and ideally, we should really be able to let those
> > > > panels work if they can, and filter out resolutions if they
> > > > can't.
> > > >
> > > > > I think a better fix would be to have a dotclock range in
> > > > > drm_panel,
> > > > > and some magic to figure out which one of these we can actually
> > > > > do. Then tell userspace that this is the mode is should
> > > > > request. That way userspace knows what the actual
> > > > > dotclock/refresh
> > > > > rate is, and the panel still works.
> > > >
> > > > It's not just about panels, but also bridges with EDID where the
> > > > tolerancy is not exposed.
> > >
> > > Given that the tolerance is a property of the panel or bridge, I
> > > agree with
> > > Daniel that it should be implemented there, or at least in
> > > cooperation with
> > > drm_panel and drm_bridge.
> >
> > How are we supposed to deal with panels without any documentation
> > then?
> >
> > > Semi-related information, I think the CEA and VESA standards allow
> > > a 0.5%
> > > clock tolerance. What is the maximum clock frequency deviation
> > > required for
> > > this platform ?
> >
> > Looks like it does indeed. That's definetely good to know.
>
> Then maybe we can choose to allow 0.5% error when a bridge is attached?
It doesn't fix the panel case, but that sounds reasonable yes
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 12:18 ` Maxime Ripard
2018-10-18 12:50 ` Icenowy Zheng
@ 2018-10-18 13:57 ` Laurent Pinchart
1 sibling, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2018-10-18 13:57 UTC (permalink / raw)
To: Maxime Ripard
Cc: Daniel Vetter, Icenowy Zheng, devicetree, Dave Airlie,
linux-sunxi, Linux Kernel Mailing List, dri-devel, Chen-Yu Tsai,
Rob Herring, Linux ARM
Hi Maxime,
On Thursday, 18 October 2018 15:18:19 EEST Maxime Ripard wrote:
> On Thu, Oct 18, 2018 at 02:31:01PM +0300, Laurent Pinchart wrote:
> > On Thursday, 18 October 2018 12:42:58 EEST Maxime Ripard wrote:
> >> On Thu, Oct 18, 2018 at 11:18:06AM +0200, Daniel Vetter wrote:
> >>> On Thu, Oct 18, 2018 at 10:55 AM Laurent Pinchart wrote:
> >>>> On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng wrote:
> >>>>> From: Chen-Yu Tsai <wens@csie.org>
> >>>>>
> >>>>> The panels shipped with Allwinner devices are very "generic", i.e.
> >>>>> they do not have model numbers or reliable sources of information
> >>>>> for the timings (that we know of) other than the fex files shipped
> >>>>> on them. The dot clock frequency provided in the fex files have all
> >>>>> been rounded to the nearest MHz, as that is the unit used in them.
> >>>>>
> >>>>> We were using the simple panel "urt,umsh-8596md-t" as a substitute
> >>>>> for the A13 Q8 tablets in the absence of a specific model for what
> >>>>> may be many different but otherwise timing compatible panels. This
> >>>>> was usable without any visual artifacts or side effects, until the
> >>>>> dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> >>>>> rgb: Validate the clock rate").
> >>>>>
> >>>>> The reason this check fails is because the dotclock frequency for
> >>>>> this model is 33.26 MHz, which is not achievable with our dot clock
> >>>>> hardware, and the rate returned by clk_round_rate deviates slightly,
> >>>>> causing the driver to reject the display mode.
> >>>>>
> >>>>> The LCD panels have some tolerance on the dot clock frequency, even
> >>>>> if it's not specified in their datasheets.
> >>>>>
> >>>>> This patch adds a 5% tolerence to the dot clock check.
> >>>>
> >>>> Why do you think this shouldn't be merged ?
> >>>
> >>> It pisses of a lot of people who really insist upon accurate timing.
> >>
> >> It's not just about accurate timings. That 5% is a made-up limit, that
> >> never have really been confirmed by looking at the typical tolerancies
> >> of panels.
> >>
> >> And while being to relaxed might make some panels work that are not
> >> working currently, it might also break some panels that currently work
> >> and won't now, and ideally, we should really be able to let those
> >> panels work if they can, and filter out resolutions if they can't.
> >>
> >>> I think a better fix would be to have a dotclock range in drm_panel,
> >>> and some magic to figure out which one of these we can actually
> >>> do. Then tell userspace that this is the mode is should
> >>> request. That way userspace knows what the actual dotclock/refresh
> >>> rate is, and the panel still works.
> >>
> >> It's not just about panels, but also bridges with EDID where the
> >> tolerancy is not exposed.
> >
> > Given that the tolerance is a property of the panel or bridge, I agree
> > with Daniel that it should be implemented there, or at least in
> > cooperation with drm_panel and drm_bridge.
>
> How are we supposed to deal with panels without any documentation then?
We can only guess, but if the guess comes from the panel driver, it will at
least not affect all panels and bridges, like this patch does.
> > Semi-related information, I think the CEA and VESA standards allow a 0.5%
> > clock tolerance. What is the maximum clock frequency deviation required
> > for this platform ?
>
> Looks like it does indeed. That's definetely good to know.
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
2018-10-18 11:31 ` Laurent Pinchart
2018-10-18 12:18 ` Maxime Ripard
@ 2019-02-03 1:32 ` Vasily Khoruzhick
1 sibling, 0 replies; 32+ messages in thread
From: Vasily Khoruzhick @ 2019-02-03 1:32 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Maxime Ripard, devicetree, Dave Airlie,
Linux Kernel Mailing List, dri-devel, linux-sunxi, Rob Herring,
Daniel Vetter, Chen-Yu Tsai, Linux ARM, Icenowy Zheng
On Thu, Oct 18, 2018 at 4:31 AM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> Given that the tolerance is a property of the panel or bridge, I agree with
> Daniel that it should be implemented there, or at least in cooperation with
> drm_panel and drm_bridge.
Clock tolerance is not specified in ANX6345 datasheet.
> Semi-related information, I think the CEA and VESA standards allow a 0.5%
> clock tolerance. What is the maximum clock frequency deviation required for
> this platform ?
This particular platform requires ~1% deviation.
E.g. on Pinebook with 768p panel: requested clock: 73.0 MHz, real
clock: 72.296296 MHz (0.96%)
on Pinebook with 1080p panel: requested clock: 138.5 MHz, real clock:
138.461538 MHz (0.03%)
So unfortunately 0.5% is not enough.
Regards,
Vasily
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
` (8 preceding siblings ...)
2018-10-18 7:33 ` [PATCH 9/9] [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check Icenowy Zheng
@ 2018-10-29 2:20 ` Vasily Khoruzhick
2019-02-04 12:22 ` Torsten Duwe
10 siblings, 0 replies; 32+ messages in thread
From: Vasily Khoruzhick @ 2018-10-29 2:20 UTC (permalink / raw)
To: Icenowy Zheng
Cc: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart, devicetree,
linux-kernel, dri-devel, linux-sunxi, arm-linux
On Thu, Oct 18, 2018 at 12:35 AM Icenowy Zheng <icenowy@aosc.io> wrote:
>
> This patchset brings the support for Analogix ANX6345 RGB-(e)DP bridge,
> which is used by some Allwinner A64 laptops, such as Pinebook and Olimex
> TERES-I.
>
> It reuses some definitions from the ANX78xx driver that already exists
> in the kernel tree, but the driver code itself is rewritten, because the
> big difference between ANX6345 and ANX78xx.
>
> This patchset also enables the bridge on Pinebook and TERES-I, and a
> temporary workaround patch (do not merge) for the dot clock accuracy
> problem of sun4i-drm.
>
> This patchset assumes some fixes ([1], [2] and [3]) are already
> applied, without them the patchset cannot be tested on the A64 devices
> mentioned above.
For whole series:
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
>
> [1] https://patchwork.kernel.org/patch/10628827/
> [2] https://patchwork.kernel.org/patch/10628825/
> [3] https://patchwork.kernel.org/patch/10646791/
>
> Chen-Yu Tsai (1):
> [DO NOT MERGE] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency
> check
>
> Icenowy Zheng (8):
> drm/bridge: move ANA78xx driver to analogix subdirectory
> drm/bridge: split some definitions of ANX78xx to dedicated headers
> drm/bridge: extract some Analogix I2C DP common code
> dt-bindings: Add ANX6345 DP/eDP transmitter binding
> drm/bridge: Add Analogix anx6345 support
> arm64: allwinner: a64: add pinmux for RGB666 LCD
> arm64: allwinner: a64: enable ANX6345 bridge on Pinebook
> arm64: allwinner: a64: enable ANX6345 bridge on TERES-I
>
> .../bindings/display/bridge/anx6345.txt | 39 +
> .../dts/allwinner/sun50i-a64-pinebook.dts | 43 +
> .../boot/dts/allwinner/sun50i-a64-teres-i.dts | 40 +-
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +
> drivers/gpu/drm/bridge/Kconfig | 10 -
> drivers/gpu/drm/bridge/Makefile | 4 +-
> drivers/gpu/drm/bridge/analogix-anx78xx.h | 719 ---------------
> drivers/gpu/drm/bridge/analogix/Kconfig | 25 +
> drivers/gpu/drm/bridge/analogix/Makefile | 4 +
> .../drm/bridge/analogix/analogix-anx6345.c | 862 ++++++++++++++++++
> .../bridge/{ => analogix}/analogix-anx78xx.c | 146 +--
> .../drm/bridge/analogix/analogix-anx78xx.h | 265 ++++++
> .../drm/bridge/analogix/analogix-i2c-dptx.c | 169 ++++
> .../drm/bridge/analogix/analogix-i2c-dptx.h | 258 ++++++
> .../bridge/analogix/analogix-i2c-txcommon.h | 240 +++++
> drivers/gpu/drm/sun4i/sun4i_rgb.c | 5 +-
> 16 files changed, 1956 insertions(+), 882 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/anx6345.txt
> delete mode 100644 drivers/gpu/drm/bridge/analogix-anx78xx.h
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> rename drivers/gpu/drm/bridge/{ => analogix}/analogix-anx78xx.c (90%)
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h
>
> --
> 2.18.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support
2018-10-18 7:33 [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Icenowy Zheng
` (9 preceding siblings ...)
2018-10-29 2:20 ` [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support Vasily Khoruzhick
@ 2019-02-04 12:22 ` Torsten Duwe
2019-02-04 20:21 ` Vasily Khoruzhick
10 siblings, 1 reply; 32+ messages in thread
From: Torsten Duwe @ 2019-02-04 12:22 UTC (permalink / raw)
To: Icenowy Zheng
Cc: David Airlie, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Archit Taneja, Andrzej Hajda, Laurent Pinchart, dri-devel,
devicetree, linux-kernel, linux-arm-kernel, linux-sunxi
On Thu, Oct 18, 2018 at 03:33:18PM +0800, Icenowy Zheng wrote:
> This patchset brings the support for Analogix ANX6345 RGB-(e)DP bridge,
> which is used by some Allwinner A64 laptops, such as Pinebook and Olimex
> TERES-I.
>
So what's the status here? I'm working on the Teres-I and I find myself
recreating the chunks in this patchset almost verbatim (only DT so far),
one by one, so there must be something right about them ;-)
Whose turn is it?
Torsten
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 0/9] Analogix ANX6345 RGB-(e)DP bridge support
2019-02-04 12:22 ` Torsten Duwe
@ 2019-02-04 20:21 ` Vasily Khoruzhick
[not found] ` <20190203185501.8958-6-anarsoul@gmail.com>
0 siblings, 1 reply; 32+ messages in thread
From: Vasily Khoruzhick @ 2019-02-04 20:21 UTC (permalink / raw)
To: Torsten Duwe
Cc: Icenowy Zheng, devicetree, Archit Taneja, Andrzej Hajda,
David Airlie, linux-sunxi, linux-kernel, dri-devel,
Maxime Ripard, Chen-Yu Tsai, Rob Herring, Laurent Pinchart,
arm-linux
On Mon, Feb 4, 2019 at 4:22 AM Torsten Duwe <duwe@lst.de> wrote:
>
> On Thu, Oct 18, 2018 at 03:33:18PM +0800, Icenowy Zheng wrote:
> > This patchset brings the support for Analogix ANX6345 RGB-(e)DP bridge,
> > which is used by some Allwinner A64 laptops, such as Pinebook and Olimex
> > TERES-I.
> >
>
> So what's the status here? I'm working on the Teres-I and I find myself
> recreating the chunks in this patchset almost verbatim (only DT so far),
> one by one, so there must be something right about them ;-)
>
> Whose turn is it?
I've sent v2 yesterday, however I tested it only on Pinebook.
>
> Torsten
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread