[PATCH V2 0/5] Add driver support for Data Capture and Compare Engine(DCC) for SM8150

[PATCH V2 0/5] Add driver support for Data Capture and Compare Engine(DCC) for SM8150

[Souradeep Chowdhury]

DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.In case of a system
crash or manual software triggers by the user the DCC hardware stores the value at the register
addresses which can be used for debugging purposes.The DCC driver provides the user with sysfs
interface to configure the register addresses.The options that the DCC hardware provides include
reading from registers,writing to registers,first reading and then writing to registers and looping
through the values of the same register.

In certain cases a register write needs to be executed for accessing the rest of the registers,
also the user might want to record the changing values of a register with time for which he has the
option to use the loop feature.

The options mentioned above are exposed to the user by sysfs files once the driver is probed.The
details and usage of this sysfs files are documented in Documentation/ABI/testing/sysfs-driver-dcc.

As an example let us consider a couple of debug scenarios where DCC has been proved to be effective
for debugging purposes:-

i)TimeStamp Related Issue

On SC7180, there was a coresight timestamp issue where it would occasionally be all 0 instead of proper
timestamp values.

Proper timestamp:
Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e

Zero timestamp:
Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2

Now this is a non-fatal issue and doesn't need a system reset, but still needs
to be rootcaused and fixed for those who do care about coresight etm traces.
Since this is a timestamp issue, we would be looking for any timestamp related
clocks and such.

o we get all the clk register details from IP documentation and configure it
via DCC config syfs node. Before that we set the current linked list.

/* Set the current linked list */
echo 3 > /sys/bus/platform/devices/10a2000.dcc/curr_list

/* Program the linked list with the addresses */
echo 0x10c004 > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c008 > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c00c > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c010 > /sys/bus/platform/devices/10a2000.dcc/config
..... and so on for other timestamp related clk registers

/* Other way of specifying is in "addr len" pair, in below case it
specifies to capture 4 words starting 0x10C004 */

echo 0x10C004 4 > /sys/bus/platform/devices/10a2000.dcc/config

/* Enable DCC */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/enable

/* Run the timestamp test for working case */

/* Send SW trigger */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger

/* Read SRAM */
cat /dev/dcc_sram > dcc_sram1.bin

/* Run the timestamp test for non-working case */

/* Send SW trigger */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger

/* Read SRAM */
cat /dev/dcc_sram > dcc_sram2.bin

Get the parser from [1] and checkout the latest branch.

/* Parse the SRAM bin */
python dcc_parser.py -s dcc_sram1.bin --v2 -o output/
python dcc_parser.py -s dcc_sram2.bin --v2 -o output/

Sample parsed output of dcc_sram1.bin:

<hwioDump version="1">
        <timestamp>03/14/21</timestamp>
	        <generator>Linux DCC Parser</generator>
		        <chip name="None" version="None">
				<register address="0x0010c004" value="0x80000000" />
				<register address="0x0010c008" value="0x00000008" />
				<register address="0x0010c00c" value="0x80004220" />
				<register address="0x0010c010" value="0x80000000" />
			</chip>
	<next_ll_offset>next_ll_offset : 0x1c </next_ll_offset>
</hwioDump>

ii)NOC register errors

A particular class of registers called NOC which are functional registers was reporting
errors while logging the values.To trace these errors the DCC has been used effectively.
The steps followed were similar to the ones mentioned above.
In addition to NOC registers a few other dependent registers were configured in DCC to
monitor it's values during a crash. A look at the dependent register values revealed that
the crash was happening due to a secured access to one of these dependent registers.
All these debugging activity and finding the root cause was achieved using DCC.

DCC parser is available at the following open source location

https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser

Souradeep Chowdhury (5):
  dt-bindings: Added the yaml bindings for DCC
  soc: qcom: dcc:Add driver support for Data Capture and Compare
    unit(DCC)
  DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver
  MAINTAINERS:Add the entry for DCC(Data Capture and Compare) driver
    support
  arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support
    node

 Documentation/ABI/testing/sysfs-driver-dcc         |  114 ++
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      |   49 +
 MAINTAINERS                                        |    8 +
 arch/arm64/boot/dts/qcom/sm8150.dtsi               |    7 +
 drivers/soc/qcom/Kconfig                           |    8 +
 drivers/soc/qcom/Makefile                          |    1 +
 drivers/soc/qcom/dcc.c                             | 1549 ++++++++++++++++++++
 7 files changed, 1736 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
 create mode 100644 drivers/soc/qcom/dcc.c

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V2 1/5] dt-bindings: Added the yaml bindings for DCC

[Souradeep Chowdhury]

Documentation for Data Capture and Compare(DCC) device tree bindings
in yaml format.

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
new file mode 100644
index 0000000..c6e0a9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Data Capture and Compare
+
+maintainers:
+  - Souradeep Chowdhury <schowdhu@codeaurora.org>
+
+description: |
+    DCC (Data Capture and Compare) is a DMA engine which is used to save
+    configuration data or system memory contents during catastrophic failure
+    or SW trigger.DCC is used to capture and store data for debugging purpose
+
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,sm8150-dcc
+      - const: qcom,dcc
+
+  reg:
+    items:
+      - description: DCC base register region
+      - description: DCC RAM base register region
+
+  reg-names:
+    items:
+      - const: dcc
+      - const: dcc-ram
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+additionalProperties: false
+
+examples:
+  - |
+    dcc@10a2000{
+                compatible = "qcom,sm8150-dcc","qcom,dcc";
+                reg = <0x010a2000  0x1000>,
+                      <0x010ad000  0x2000>;
+                reg-names = "dcc", "dcc-ram";
+    };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V2 2/5] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)

[Souradeep Chowdhury]

The DCC is a DMA Engine designed to capture and store data
during system crash or software triggers.The DCC operates
based on user inputs via the sysfs interface.The user gives
addresses as inputs and these addresses are stored in the
form of linkedlists.In case of a system crash or a manual
software trigger by the user through the sysfs interface,
the dcc captures and stores the values at these addresses.
This patch contains the driver which has all the methods
pertaining to the sysfs interface, auxiliary functions to
support all the four fundamental operations of dcc namely
read, write, first read then write and loop.The probe method
here instantiates all the resources necessary for dcc to
operate mainly the dedicated dcc sram where it stores the
values.The DCC driver can be used for debugging purposes
without going for a reboot since it can perform manual
triggers.

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 drivers/soc/qcom/Kconfig  |    8 +
 drivers/soc/qcom/Makefile |    1 +
 drivers/soc/qcom/dcc.c    | 1549 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1558 insertions(+)
 create mode 100644 drivers/soc/qcom/dcc.c

diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 79b568f..8819e0b 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -69,6 +69,14 @@ config QCOM_LLCC
 	  SDM845. This provides interfaces to clients that use the LLCC.
 	  Say yes here to enable LLCC slice driver.

+config QCOM_DCC
+	tristate "Qualcomm Technologies, Inc. Data Capture and Compare engine driver"
+	depends on ARCH_QCOM || COMPILE_TEST
+	help
+	  This option enables driver for Data Capture and Compare engine. DCC
+	  driver provides interface to configure DCC block and read back
+	  captured data from DCC's internal SRAM.
+
 config QCOM_KRYO_L2_ACCESSORS
 	bool
 	depends on ARCH_QCOM && ARM64 || COMPILE_TEST
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index ad675a6..1b00870 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
 obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
 obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
+obj-$(CONFIG_QCOM_DCC) += dcc.o
diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c
new file mode 100644
index 0000000..a55d8ca7
--- /dev/null
+++ b/drivers/soc/qcom/dcc.c
@@ -0,0 +1,1549 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/cdev.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+
+#define TIMEOUT_US		100
+
+#define dcc_writel(drvdata, val, off)					\
+	writel((val), drvdata->base + dcc_offset_conv(drvdata, off))
+#define dcc_readl(drvdata, off)						\
+	readl(drvdata->base + dcc_offset_conv(drvdata, off))
+
+#define dcc_sram_readl(drvdata, off)					\
+	readl(drvdata->ram_base + off)
+
+#define DCC_SRAM_NODE "dcc_sram"
+
+/* DCC registers */
+#define DCC_HW_INFO			0x04
+#define DCC_LL_NUM_INFO			0x10
+#define DCC_STATUS			0x1C
+#define DCC_LL_LOCK(m)			(0x34 + 0x80 * m)
+#define DCC_LL_CFG(m)			(0x38 + 0x80 * m)
+#define DCC_LL_BASE(m)			(0x3c + 0x80 * m)
+#define DCC_FD_BASE(m)			(0x40 + 0x80 * m)
+#define DCC_LL_TIMEOUT(m)		(0x44 + 0x80 * m)
+#define DCC_LL_INT_ENABLE(m)		(0x4C + 0x80 * m)
+#define DCC_LL_INT_STATUS(m)		(0x50 + 0x80 * m)
+#define DCC_LL_SW_TRIGGER(m)		(0x60 + 0x80 * m)
+#define DCC_LL_BUS_ACCESS_STATUS(m)	(0x64 + 0x80 * m)
+
+#define DCC_MAP_LEVEL1			0x18
+#define DCC_MAP_LEVEL2			0x34
+#define DCC_MAP_LEVEL3			0x4C
+
+#define DCC_MAP_OFFSET1			0x10
+#define DCC_MAP_OFFSET2			0x18
+#define DCC_MAP_OFFSET3			0x1C
+#define DCC_MAP_OFFSET4			0x8
+
+#define DCC_FIX_LOOP_OFFSET		16
+#define DCC_VER_INFO_BIT		9
+
+#define DCC_READ			0
+#define DCC_WRITE			1
+#define DCC_LOOP			2
+#define DCC_READ_WRITE			3
+
+#define MAX_DCC_OFFSET			GENMASK(9, 2)
+#define MAX_DCC_LEN			GENMASK(6, 0)
+#define MAX_LOOP_CNT			GENMASK(7, 0)
+
+#define DCC_ADDR_DESCRIPTOR		0x00
+#define DCC_LOOP_DESCRIPTOR		BIT(30)
+#define DCC_RD_MOD_WR_DESCRIPTOR	BIT(31)
+#define DCC_LINK_DESCRIPTOR		GENMASK(31, 30)
+
+#define DCC_READ_IND			0x00
+#define DCC_WRITE_IND			(BIT(28))
+
+#define DCC_AHB_IND			0x00
+#define DCC_APB_IND			BIT(29)
+
+#define DCC_MAX_LINK_LIST		8
+#define DCC_INVALID_LINK_LIST		GENMASK(7, 0)
+
+#define DCC_VER_MASK1			GENMASK(6, 0)
+#define DCC_VER_MASK2			GENMASK(5, 0)
+
+#define DCC_RD_MOD_WR_ADDR              0xC105E
+
+struct qcom_dcc_config {
+	const int dcc_ram_offset;
+};
+
+enum dcc_descriptor_type {
+	DCC_ADDR_TYPE,
+	DCC_LOOP_TYPE,
+	DCC_READ_WRITE_TYPE,
+	DCC_WRITE_TYPE
+};
+
+enum dcc_mem_map_ver {
+	DCC_MEM_MAP_VER1 = 1,
+	DCC_MEM_MAP_VER2 = 2,
+	DCC_MEM_MAP_VER3 = 3
+};
+
+struct dcc_config_entry {
+	u32				base;
+	u32				offset;
+	u32				len;
+	u32				index;
+	u32				loop_cnt;
+	u32				write_val;
+	u32				mask;
+	bool				apb_bus;
+	enum dcc_descriptor_type	desc_type;
+	struct list_head		list;
+};
+
+struct dcc_drvdata {
+	void __iomem		*base;
+	u32			reg_size;
+	struct device		*dev;
+	struct mutex		mutex;
+	void __iomem		*ram_base;
+	u32			ram_size;
+	u32			ram_offset;
+	enum dcc_mem_map_ver	mem_map_ver;
+	u32			ram_cfg;
+	u32			ram_start;
+	bool			*enable;
+	bool			*configured;
+	bool			interrupt_disable;
+	char			*sram_node;
+	struct cdev		sram_dev;
+	struct class		*sram_class;
+	struct list_head	*cfg_head;
+	u32			*nr_config;
+	u32			nr_link_list;
+	u8			curr_list;
+	u8			loopoff;
+};
+
+struct dcc_cfg_attr {
+	u32	addr;
+	u32	prev_addr;
+	u32	prev_off;
+	u32	link;
+	u32	sram_offset;
+};
+
+struct dcc_cfg_loop_attr {
+	u32	loop;
+	bool	loop_start;
+	u32	loop_cnt;
+	u32	loop_len;
+	u32	loop_off;
+};
+
+static size_t dcc_offset_conv(struct dcc_drvdata *drvdata, size_t off)
+{
+	if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL3)
+			return (off - DCC_MAP_OFFSET3);
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET2);
+		else if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL1)
+			return (off - DCC_MAP_OFFSET1);
+	} else if (drvdata->mem_map_ver == DCC_MEM_MAP_VER2) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET4);
+	}
+	return off;
+}
+
+static int dcc_sram_writel(struct dcc_drvdata *drvdata,
+					u32 val, u32 off)
+{
+	if (unlikely(off > (drvdata->ram_size - 4)))
+		return -EINVAL;
+
+	writel((val), drvdata->ram_base + off);
+
+	return 0;
+}
+
+static bool dcc_ready(struct dcc_drvdata *drvdata)
+{
+	u32 val;
+
+	/* poll until DCC ready */
+	if (!readl_poll_timeout((drvdata->base + DCC_STATUS), val,
+				(FIELD_GET(GENMASK(1, 0), val) == 0), 1, TIMEOUT_US))
+		return true;
+
+	return false;
+}
+
+static int dcc_read_status(struct dcc_drvdata *drvdata)
+{
+	int curr_list;
+	u32 bus_status;
+	u32 ll_cfg = 0;
+	u32 tmp_ll_cfg = 0;
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+
+		bus_status = dcc_readl(drvdata, DCC_LL_BUS_ACCESS_STATUS(curr_list));
+
+		if (bus_status) {
+			dev_err(drvdata->dev,
+				"Read access error for list %d err: 0x%x.\n",
+				curr_list, bus_status);
+
+			ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
+			tmp_ll_cfg = ll_cfg & ~BIT(9);
+			dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
+			dcc_writel(drvdata, 0x3,
+				DCC_LL_BUS_ACCESS_STATUS(curr_list));
+			dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
+			return -ENODATA;
+		}
+	}
+
+	return 0;
+}
+
+static int dcc_sw_trigger(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+	int curr_list;
+	u32 ll_cfg = 0;
+	u32 tmp_ll_cfg = 0;
+
+	mutex_lock(&drvdata->mutex);
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+		ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
+		tmp_ll_cfg = ll_cfg & ~BIT(9);
+		dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
+		dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
+		dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
+	}
+
+	if (!dcc_ready(drvdata)) {
+		dev_err(drvdata->dev,
+			"DCC is busy after receiving sw tigger.\n");
+		ret = -EBUSY;
+		goto err;
+	}
+
+	ret = dcc_read_status(drvdata);
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static void _dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg)
+{
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	cfg->prev_off = 0;
+	cfg->prev_addr = cfg->addr;
+}
+
+static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata,
+				  struct dcc_config_entry *entry,
+				  struct dcc_cfg_attr *cfg)
+{
+	int ret;
+
+	if (cfg->link) {
+		/*
+		 * write new offset = 1 to continue
+		 * processing the list
+		 */
+
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		_dcc_ll_cfg_reset_link(cfg);
+	}
+
+	cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR;
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	ret = dcc_sram_writel(drvdata, entry->mask, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	cfg->addr = 0;
+	return ret;
+}
+
+static int _dcc_ll_cfg_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry,
+			    struct dcc_cfg_attr *cfg,
+			    struct dcc_cfg_loop_attr *cfg_loop,
+			    u32 *total_len)
+{
+
+	int ret;
+
+	/* Check if we need to write link of prev entry */
+	if (cfg->link) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+	}
+
+	if (cfg_loop->loop_start) {
+		cfg_loop->loop = (cfg->sram_offset - cfg_loop->loop_off) / 4;
+		cfg_loop->loop |= (cfg_loop->loop_cnt << drvdata->loopoff) &
+		GENMASK(27, drvdata->loopoff);
+		cfg_loop->loop |= DCC_LOOP_DESCRIPTOR;
+		*total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt;
+
+		ret = dcc_sram_writel(drvdata, cfg_loop->loop, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+
+		cfg_loop->loop_start = false;
+		cfg_loop->loop_len = 0;
+		cfg_loop->loop_off = 0;
+	} else {
+		cfg_loop->loop_start = true;
+		cfg_loop->loop_cnt = entry->loop_cnt - 1;
+		cfg_loop->loop_len = *total_len;
+		cfg_loop->loop_off = cfg->sram_offset;
+	}
+
+	/* Reset link and prev_off */
+
+	_dcc_ll_cfg_reset_link(cfg);
+
+	return ret;
+}
+
+static int _dcc_ll_cfg_write(struct dcc_drvdata *drvdata,
+			     struct dcc_config_entry *entry,
+			     struct dcc_cfg_attr *cfg,
+			     u32 *total_len)
+{
+	u32 off;
+	int ret;
+
+	if (cfg->link) {
+		/*
+		 * write new offset = 1 to continue
+		 * processing the list
+		 */
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		cfg->addr = 0x00;
+		cfg->prev_off = 0;
+		cfg->prev_addr = cfg->addr;
+	}
+
+	off = entry->offset/4;
+	/* write new offset-length pair to correct position */
+	cfg->link |= ((off & GENMASK(7, 0)) | BIT(15) | ((entry->len << 8) & GENMASK(14, 8)));
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	/* Address type */
+	cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND;
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	return ret;
+}
+
+static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
+			       struct dcc_config_entry *entry,
+			       struct dcc_cfg_attr *cfg,
+			       u32 *pos, u32 *total_len)
+{
+	int ret;
+	u32 off;
+
+	cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
+
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND;
+
+	off = entry->offset/4;
+
+	*total_len += entry->len * 4;
+
+	if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) {
+		/* Check if we need to write prev link entry */
+		if (cfg->link) {
+			ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+			if (ret)
+				return ret;
+			cfg->sram_offset += 4;
+		}
+		dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset);
+
+		/* Write address */
+		ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+
+		/* Reset link and prev_off */
+		cfg->link = 0;
+		cfg->prev_off = 0;
+	}
+
+	if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
+		dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n",
+		entry->base, entry->offset);
+		ret = -EINVAL;
+		return ret;
+	}
+
+	if (cfg->link) {
+		/*
+		 * link already has one offset-length so new
+		 * offset-length needs to be placed at
+		 * bits [29:15]
+		 */
+		*pos = 15;
+
+		/* Clear bits [31:16] */
+		cfg->link &= GENMASK(14, 0);
+	} else {
+		/*
+		 * link is empty, so new offset-length needs
+		 * to be placed at bits [15:0]
+		 */
+		*pos = 0;
+		cfg->link = 1 << 15;
+	}
+
+	/* write new offset-length pair to correct position */
+	cfg->link |= (((off-cfg->prev_off) & GENMASK(7, 0)) |
+		     ((entry->len << 8) & GENMASK(14, 8))) << *pos;
+
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	if (*pos) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		cfg->link = 0;
+	}
+
+	cfg->prev_off  = off + entry->len - 1;
+	cfg->prev_addr = cfg->addr;
+	return ret;
+}
+
+static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list)
+{
+	int ret = 0;
+	u32 total_len, pos;
+	struct dcc_config_entry *entry;
+	struct dcc_cfg_attr cfg;
+	struct dcc_cfg_loop_attr cfg_loop;
+
+	memset(&cfg, 0, sizeof(cfg));
+	memset(&cfg_loop, 0, sizeof(cfg_loop));
+	cfg.sram_offset = drvdata->ram_cfg * 4;
+	total_len = 0;
+
+	list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+			ret = _dcc_ll_cfg_read_write(drvdata, entry, &cfg);
+			if (ret)
+				goto overstep;
+			break;
+
+		case DCC_LOOP_TYPE:
+			ret = _dcc_ll_cfg_loop(drvdata, entry, &cfg, &cfg_loop, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+
+		case DCC_WRITE_TYPE:
+			ret = _dcc_ll_cfg_write(drvdata, entry, &cfg, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+
+		default:
+			ret = _dcc_ll_cfg_default(drvdata, entry, &cfg, &pos, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+		}
+	}
+
+	if (cfg.link) {
+		ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
+		if (ret)
+			goto overstep;
+		cfg.sram_offset += 4;
+	}
+
+	if (cfg_loop.loop_start) {
+		dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* Handling special case of list ending with a rd_mod_wr */
+	if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) {
+		cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0);
+		cfg.addr |= DCC_ADDR_DESCRIPTOR;
+		ret = dcc_sram_writel(drvdata, cfg.addr, cfg.sram_offset);
+		if (ret)
+			goto overstep;
+		cfg.sram_offset += 4;
+	}
+
+	/* Setting zero to indicate end of the list */
+	cfg.link = DCC_LINK_DESCRIPTOR;
+	ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
+	if (ret)
+		goto overstep;
+	cfg.sram_offset += 4;
+
+	/* Update ram_cfg and check if the data will overstep */
+
+	drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4;
+
+	if (cfg.sram_offset + total_len > drvdata->ram_size) {
+		cfg.sram_offset += total_len;
+		goto overstep;
+	}
+
+	drvdata->ram_start = cfg.sram_offset/4;
+	return 0;
+overstep:
+	ret = -EINVAL;
+	memset_io(drvdata->ram_base, 0, drvdata->ram_size);
+	dev_err(drvdata->dev, "DCC SRAM oversteps, 0x%x (0x%x)\n",
+	cfg.sram_offset, drvdata->ram_size);
+
+err:
+	return ret;
+}
+
+static int dcc_valid_list(struct dcc_drvdata *drvdata, int curr_list)
+{
+	u32 lock_reg;
+
+	if (list_empty(&drvdata->cfg_head[curr_list]))
+		return -EINVAL;
+
+	if (drvdata->enable[curr_list]) {
+		dev_err(drvdata->dev, "List %d is already enabled\n",
+				curr_list);
+		return -EINVAL;
+	}
+
+	lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(curr_list));
+	if (lock_reg & 0x1) {
+		dev_err(drvdata->dev, "List %d is already locked\n",
+				curr_list);
+		return -EINVAL;
+	}
+
+	dev_err(drvdata->dev, "DCC list passed %d\n", curr_list);
+	return 0;
+}
+
+static bool is_dcc_enabled(struct dcc_drvdata *drvdata)
+{
+	bool dcc_enable = false;
+	int list;
+
+	for (list = 0; list < DCC_MAX_LINK_LIST; list++) {
+		if (drvdata->enable[list]) {
+			dcc_enable = true;
+			break;
+		}
+	}
+
+	return dcc_enable;
+}
+
+static int dcc_enable(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+	int list;
+	u32 ram_cfg_base;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (!is_dcc_enabled(drvdata)) {
+		memset_io(drvdata->ram_base,
+			0xDE, drvdata->ram_size);
+	}
+
+	for (list = 0; list < drvdata->nr_link_list; list++) {
+
+		if (dcc_valid_list(drvdata, list))
+			continue;
+
+		/* 1. Take ownership of the list */
+		dcc_writel(drvdata, BIT(0), DCC_LL_LOCK(list));
+
+		/* 2. Program linked-list in the SRAM */
+		ram_cfg_base = drvdata->ram_cfg;
+		ret = __dcc_ll_cfg(drvdata, list);
+		if (ret) {
+			dcc_writel(drvdata, 0, DCC_LL_LOCK(list));
+			dev_info(drvdata->dev, "DCC ram programming failed\n");
+			goto err;
+		}
+
+		/* 3. program DCC_RAM_CFG reg */
+		dcc_writel(drvdata, ram_cfg_base +
+			drvdata->ram_offset/4, DCC_LL_BASE(list));
+		dcc_writel(drvdata, drvdata->ram_start +
+			drvdata->ram_offset/4, DCC_FD_BASE(list));
+		dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list));
+
+		/* 4. Clears interrupt status register */
+		dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list));
+		dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)),
+					DCC_LL_INT_STATUS(list));
+
+		dev_info(drvdata->dev, "All values written to enable.\n");
+		/* Make sure all config is written in sram */
+		mb();
+
+		drvdata->enable[list] = true;
+
+		/* 5. Configure trigger */
+		dcc_writel(drvdata, BIT(9), DCC_LL_CFG(list));
+	}
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static void dcc_disable(struct dcc_drvdata *drvdata)
+{
+	int curr_list;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (!dcc_ready(drvdata))
+		dev_err(drvdata->dev, "DCC is not ready Disabling DCC...\n");
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+		dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list));
+		dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list));
+		dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list));
+		dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
+		drvdata->enable[curr_list] = false;
+	}
+	memset_io(drvdata->ram_base, 0, drvdata->ram_size);
+	drvdata->ram_cfg = 0;
+	drvdata->ram_start = 0;
+	mutex_unlock(&drvdata->mutex);
+}
+
+static ssize_t curr_list_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list == DCC_INVALID_LINK_LIST) {
+		dev_err(dev, "curr_list is not set.\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = scnprintf(buf, PAGE_SIZE, "%d\n",	drvdata->curr_list);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t curr_list_store(struct device *dev,
+						struct device_attribute *attr,
+						const char *buf, size_t size)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	unsigned long val;
+	u32 lock_reg;
+	bool dcc_enable = false;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val >= drvdata->nr_link_list)
+		return -EINVAL;
+
+	mutex_lock(&drvdata->mutex);
+
+	dcc_enable = is_dcc_enabled(drvdata);
+	if (drvdata->curr_list != DCC_INVALID_LINK_LIST	&& dcc_enable) {
+		dev_err(drvdata->dev, "DCC is enabled, please disable it first.\n");
+		mutex_unlock(&drvdata->mutex);
+		return -EINVAL;
+	}
+
+	lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
+	if (lock_reg & 0x1) {
+		dev_err(drvdata->dev, "DCC linked list is already configured\n");
+		mutex_unlock(&drvdata->mutex);
+		return -EINVAL;
+	}
+	drvdata->curr_list = val;
+	mutex_unlock(&drvdata->mutex);
+
+	return size;
+}
+
+static DEVICE_ATTR_RW(curr_list);
+
+
+static ssize_t trigger_store(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	int ret = 0;
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+	if (val != 1)
+		return -EINVAL;
+
+	ret = dcc_sw_trigger(drvdata);
+	if (!ret)
+		ret = size;
+
+	return ret;
+}
+static DEVICE_ATTR_WO(trigger);
+
+static ssize_t enable_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	bool dcc_enable = false;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	dcc_enable = is_dcc_enabled(drvdata);
+
+	ret = scnprintf(buf, PAGE_SIZE, "%u\n",
+				(unsigned int)dcc_enable);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t enable_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	int ret = 0;
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val)
+		ret = dcc_enable(drvdata);
+	else
+		dcc_disable(drvdata);
+
+	if (!ret)
+		ret = size;
+
+	return ret;
+
+}
+
+static DEVICE_ATTR_RW(enable);
+
+static ssize_t config_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	struct dcc_config_entry *entry;
+	char local_buf[64];
+	int len = 0, count = 0;
+
+	buf[0] = '\0';
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		count = -EINVAL;
+		goto err;
+	}
+
+	list_for_each_entry(entry,
+	&drvdata->cfg_head[drvdata->curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+			len = snprintf(local_buf, 64, "Index: 0x%x, mask: 0x%x, val: 0x%x\n",
+				entry->index, entry->mask, entry->write_val);
+			break;
+		case DCC_LOOP_TYPE:
+			len = snprintf(local_buf, 64, "Index: 0x%x, Loop: %d\n",
+				entry->index, entry->loop_cnt);
+			break;
+		case DCC_WRITE_TYPE:
+			len = snprintf(local_buf, 64,
+				"Write Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
+				entry->index, entry->base, entry->offset, entry->len,
+				entry->apb_bus);
+			break;
+		default:
+			len = snprintf(local_buf, 64,
+				"Read Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
+				entry->index, entry->base, entry->offset,
+				entry->len, entry->apb_bus);
+		}
+
+		if ((count + len) > PAGE_SIZE) {
+			dev_err(dev, "DCC: Couldn't write complete config\n");
+			break;
+		}
+		strlcat(buf, local_buf, PAGE_SIZE);
+		count += len;
+	}
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return count;
+}
+
+static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
+				unsigned int len, int apb_bus)
+{
+	int ret;
+	struct dcc_config_entry *entry, *pentry;
+	unsigned int base, offset;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(drvdata->dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (!len || len > (drvdata->ram_size / 8)) {
+		dev_err(drvdata->dev, "DCC: Invalid length\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	base = addr & GENMASK(31, 4);
+
+	if (!list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
+		pentry = list_last_entry(&drvdata->cfg_head[drvdata->curr_list],
+			struct dcc_config_entry, list);
+
+		if (pentry->desc_type == DCC_ADDR_TYPE &&
+				addr >= (pentry->base + pentry->offset) &&
+				addr <= (pentry->base +
+					pentry->offset + MAX_DCC_OFFSET)) {
+
+			/* Re-use base address from last entry */
+			base = pentry->base;
+
+			if ((pentry->len * 4 + pentry->base + pentry->offset)
+					== addr) {
+				len += pentry->len;
+
+				if (len > MAX_DCC_LEN)
+					pentry->len = MAX_DCC_LEN;
+				else
+					pentry->len = len;
+
+				addr = pentry->base + pentry->offset +
+					pentry->len * 4;
+				len -= pentry->len;
+			}
+		}
+	}
+
+	offset = addr - base;
+
+	while (len) {
+		entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+		if (!entry) {
+			ret = -ENOMEM;
+			goto err;
+		}
+
+		entry->base = base;
+		entry->offset = offset;
+		entry->len = min_t(u32, len, MAX_DCC_LEN);
+		entry->index = drvdata->nr_config[drvdata->curr_list]++;
+		entry->desc_type = DCC_ADDR_TYPE;
+		entry->apb_bus = apb_bus;
+		INIT_LIST_HEAD(&entry->list);
+		list_add_tail(&entry->list,
+			&drvdata->cfg_head[drvdata->curr_list]);
+
+		len -= entry->len;
+		offset += MAX_DCC_LEN * 4;
+	}
+
+	mutex_unlock(&drvdata->mutex);
+	return 0;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t config_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	int ret, len, apb_bus;
+	unsigned int base;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	int nval;
+
+	nval = sscanf(buf, "%x %i %d", &base, &len, &apb_bus);
+	if (nval <= 0 || nval > 3)
+		return -EINVAL;
+
+	if (nval == 1) {
+		len = 1;
+		apb_bus = 0;
+	} else if (nval == 2) {
+		apb_bus = 0;
+	} else {
+		apb_bus = 1;
+	}
+
+	ret = dcc_config_add(drvdata, base, len, apb_bus);
+	if (ret)
+		return ret;
+
+	return size;
+
+}
+
+static DEVICE_ATTR_RW(config);
+
+static void dcc_config_reset(struct dcc_drvdata *drvdata)
+{
+	struct dcc_config_entry *entry, *temp;
+	int curr_list;
+
+	mutex_lock(&drvdata->mutex);
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		list_for_each_entry_safe(entry, temp,
+			&drvdata->cfg_head[curr_list], list) {
+			list_del(&entry->list);
+			devm_kfree(drvdata->dev, entry);
+			drvdata->nr_config[curr_list]--;
+		}
+	}
+	drvdata->ram_start = 0;
+	drvdata->ram_cfg = 0;
+	mutex_unlock(&drvdata->mutex);
+}
+
+
+static ssize_t config_reset_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val)
+		dcc_config_reset(drvdata);
+
+	return size;
+}
+
+static DEVICE_ATTR_WO(config_reset);
+
+static ssize_t ready_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (!drvdata->enable[drvdata->curr_list]) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = scnprintf(buf, PAGE_SIZE, "%u\n",
+			(unsigned int)FIELD_GET(BIT(1), dcc_readl(drvdata, DCC_STATUS)));
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_RO(ready);
+
+static ssize_t interrupt_disable_show(struct device *dev,
+						struct device_attribute *attr,
+						char *buf)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n",
+				(unsigned int)drvdata->interrupt_disable);
+}
+
+static ssize_t interrupt_disable_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	mutex_lock(&drvdata->mutex);
+	drvdata->interrupt_disable = (val ? 1:0);
+	mutex_unlock(&drvdata->mutex);
+	return size;
+}
+
+static DEVICE_ATTR_RW(interrupt_disable);
+
+static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt)
+{
+	struct dcc_config_entry *entry;
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry)
+		return -ENOMEM;
+
+	entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT);
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	entry->desc_type = DCC_LOOP_TYPE;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+
+	return 0;
+}
+
+static ssize_t loop_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	int ret;
+	unsigned long loop_cnt;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	if (kstrtoul(buf, 16, &loop_cnt)) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = dcc_add_loop(drvdata, loop_cnt);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&drvdata->mutex);
+	return size;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_WO(loop);
+
+static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask,
+				unsigned int val)
+{
+	int ret = 0;
+	struct dcc_config_entry *entry;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(drvdata->dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
+		dev_err(drvdata->dev, "DCC: No read address programmed\n");
+		ret = -EPERM;
+		goto err;
+	}
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	entry->desc_type = DCC_READ_WRITE_TYPE;
+	entry->mask = mask;
+	entry->write_val = val;
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t rd_mod_wr_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	int ret;
+	int nval;
+	unsigned int mask, val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	nval = sscanf(buf, "%x %x", &mask, &val);
+
+	if (nval <= 1 || nval > 2)
+		return -EINVAL;
+
+	ret = dcc_rd_mod_wr_add(drvdata, mask, val);
+	if (ret)
+		return ret;
+
+	return size;
+
+}
+
+static DEVICE_ATTR_WO(rd_mod_wr);
+
+static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr,
+				unsigned int write_val, int apb_bus)
+{
+	struct dcc_config_entry *entry;
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry)
+		return -ENOMEM;
+
+	entry->desc_type = DCC_WRITE_TYPE;
+	entry->base = addr & GENMASK(31, 4);
+	entry->offset = addr - entry->base;
+	entry->write_val = write_val;
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	entry->len = 1;
+	entry->apb_bus = apb_bus;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+
+	return 0;
+}
+
+static ssize_t config_write_store(struct device *dev,
+						struct device_attribute *attr,
+						const char *buf, size_t size)
+{
+	int ret;
+	int nval;
+	unsigned int addr, write_val;
+	int apb_bus = 0;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	nval = sscanf(buf, "%x %x %d", &addr, &write_val, &apb_bus);
+
+	if (nval <= 1 || nval > 3) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (nval == 3 && apb_bus != 0)
+		apb_bus = 1;
+
+	ret = dcc_add_write(drvdata, addr, write_val, apb_bus);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&drvdata->mutex);
+	return size;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_WO(config_write);
+
+static const struct device_attribute *dcc_attrs[] = {
+	&dev_attr_trigger,
+	&dev_attr_enable,
+	&dev_attr_config,
+	&dev_attr_config_reset,
+	&dev_attr_ready,
+	&dev_attr_interrupt_disable,
+	&dev_attr_loop,
+	&dev_attr_rd_mod_wr,
+	&dev_attr_curr_list,
+	&dev_attr_config_write,
+	NULL,
+};
+
+static int dcc_create_files(struct device *dev,
+					const struct device_attribute **attrs)
+{
+	int ret = 0, i;
+
+	for (i = 0; attrs[i] != NULL; i++) {
+		ret = device_create_file(dev, attrs[i]);
+		if (ret) {
+			dev_err(dev, "DCC: Couldn't create sysfs attribute: %s\n",
+				attrs[i]->attr.name);
+			break;
+		}
+	}
+	return ret;
+}
+
+static int dcc_sram_open(struct inode *inode, struct file *file)
+{
+	struct dcc_drvdata *drvdata = container_of(inode->i_cdev,
+		struct dcc_drvdata,
+		sram_dev);
+	file->private_data = drvdata;
+
+	return	0;
+}
+
+static ssize_t dcc_sram_read(struct file *file, char __user *data,
+						size_t len, loff_t *ppos)
+{
+	unsigned char *buf;
+	struct dcc_drvdata *drvdata = file->private_data;
+
+	/* EOF check */
+	if (drvdata->ram_size <= *ppos)
+		return 0;
+
+	if ((*ppos + len) > drvdata->ram_size)
+		len = (drvdata->ram_size - *ppos);
+
+	buf = kzalloc(len, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	memcpy_fromio(buf, drvdata->ram_base + *ppos, len);
+
+	if (copy_to_user(data, buf, len)) {
+		dev_err(drvdata->dev, "DCC: Couldn't copy all data to user\n");
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	*ppos += len;
+
+	kfree(buf);
+
+	return len;
+}
+
+static const struct file_operations dcc_sram_fops = {
+	.owner		= THIS_MODULE,
+	.open		= dcc_sram_open,
+	.read		= dcc_sram_read,
+	.llseek		= no_llseek,
+};
+
+static int dcc_sram_dev_register(struct dcc_drvdata *drvdata)
+{
+	int ret;
+	struct device *device;
+	dev_t dev;
+
+	ret = alloc_chrdev_region(&dev, 0, 1, drvdata->sram_node);
+	if (ret)
+		goto err_alloc;
+
+	cdev_init(&drvdata->sram_dev, &dcc_sram_fops);
+
+	drvdata->sram_dev.owner = THIS_MODULE;
+	ret = cdev_add(&drvdata->sram_dev, dev, 1);
+	if (ret)
+		goto err_cdev_add;
+
+	drvdata->sram_class = class_create(THIS_MODULE, drvdata->sram_node);
+	if (IS_ERR(drvdata->sram_class)) {
+		ret = PTR_ERR(drvdata->sram_class);
+		goto err_class_create;
+	}
+
+	device = device_create(drvdata->sram_class, NULL,
+						drvdata->sram_dev.dev, drvdata,
+						drvdata->sram_node);
+	if (IS_ERR(device)) {
+		ret = PTR_ERR(device);
+		goto err_dev_create;
+	}
+
+	return 0;
+err_dev_create:
+	class_destroy(drvdata->sram_class);
+err_class_create:
+	cdev_del(&drvdata->sram_dev);
+err_cdev_add:
+	unregister_chrdev_region(drvdata->sram_dev.dev, 1);
+err_alloc:
+	return ret;
+}
+
+static void dcc_sram_dev_deregister(struct dcc_drvdata *drvdata)
+{
+	device_destroy(drvdata->sram_class, drvdata->sram_dev.dev);
+	class_destroy(drvdata->sram_class);
+	cdev_del(&drvdata->sram_dev);
+	unregister_chrdev_region(drvdata->sram_dev.dev, 1);
+}
+
+static int dcc_sram_dev_init(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+
+	drvdata->sram_node = DCC_SRAM_NODE;
+	if (!drvdata->sram_node)
+		return -ENOMEM;
+
+	ret = dcc_sram_dev_register(drvdata);
+	if (ret)
+		dev_err(drvdata->dev, "DCC: sram node not registered.\n");
+
+	return ret;
+}
+
+static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata)
+{
+	dcc_sram_dev_deregister(drvdata);
+}
+
+static int dcc_probe(struct platform_device *pdev)
+{
+	int ret = 0, i;
+	struct device *dev = &pdev->dev;
+	struct dcc_drvdata *dcc;
+	struct resource *res;
+	const struct qcom_dcc_config *cfg;
+
+	dcc = devm_kzalloc(dev, sizeof(*dcc), GFP_KERNEL);
+	if (!dcc)
+		return -ENOMEM;
+
+	dcc->dev = &pdev->dev;
+	platform_set_drvdata(pdev, dcc);
+
+	dcc->base = devm_platform_ioremap_resource_byname(pdev, "dcc");
+	if (!dcc->base)
+		return -ENOMEM;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dcc-ram");
+	if (!res)
+		return -EINVAL;
+
+	dcc->ram_size = resource_size(res);
+
+	dcc->ram_base = devm_ioremap(dev, res->start, resource_size(res));
+	if (!dcc->ram_base)
+		return -ENOMEM;
+
+	cfg = of_device_get_match_data(&pdev->dev);
+	dcc->ram_offset = cfg->dcc_ram_offset;
+
+	if (FIELD_GET(BIT(DCC_VER_INFO_BIT), dcc_readl(dcc, DCC_HW_INFO))) {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER3;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;
+	} else if ((dcc_readl(dcc, DCC_HW_INFO) & DCC_VER_MASK2) == DCC_VER_MASK2) {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER2;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;
+	} else {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER1;
+		dcc->nr_link_list = DCC_MAX_LINK_LIST;
+	}
+
+	if ((dcc_readl(dcc, DCC_HW_INFO) & BIT(6)) == BIT(6))
+		dcc->loopoff = DCC_FIX_LOOP_OFFSET;
+	else
+		dcc->loopoff = get_bitmask_order((dcc->ram_size +
+				dcc->ram_offset) / 4 - 1);
+
+	mutex_init(&dcc->mutex);
+	dcc->enable = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(bool), GFP_KERNEL);
+	if (!dcc->enable)
+		return -ENOMEM;
+
+	dcc->configured = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(bool), GFP_KERNEL);
+	if (!dcc->configured)
+		return -ENOMEM;
+
+	dcc->nr_config = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(u32), GFP_KERNEL);
+	if (!dcc->nr_config)
+		return -ENOMEM;
+
+	dcc->cfg_head = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(struct list_head), GFP_KERNEL);
+	if (!dcc->cfg_head)
+		return -ENOMEM;
+
+	for (i = 0; i < dcc->nr_link_list; i++)
+		INIT_LIST_HEAD(&dcc->cfg_head[i]);
+
+
+	memset_io(dcc->ram_base, 0, dcc->ram_size);
+	dcc->curr_list = DCC_INVALID_LINK_LIST;
+	ret = dcc_sram_dev_init(dcc);
+	if (ret)
+		goto out;
+
+	ret = dcc_create_files(dev, dcc_attrs);
+	if (ret)
+		goto out;
+
+out:
+	return ret;
+}
+
+static int dcc_remove(struct platform_device *pdev)
+{
+	struct dcc_drvdata *drvdata = platform_get_drvdata(pdev);
+
+	dcc_sram_dev_exit(drvdata);
+
+	dcc_config_reset(drvdata);
+
+	return 0;
+}
+
+static const struct qcom_dcc_config sm8150_cfg = {
+	.dcc_ram_offset	= 0x5000,
+};
+
+static const struct of_device_id dcc_match_table[] = {
+	{ .compatible = "qcom,sm8150-dcc", .data = &sm8150_cfg },
+};
+MODULE_DEVICE_TABLE(of, dcc_match_table);
+
+static struct platform_driver dcc_driver = {
+	.probe					= dcc_probe,
+	.remove					= dcc_remove,
+	.driver					= {
+		.name		= "qcom-dcc",
+		.of_match_table	= dcc_match_table,
+	},
+};
+
+module_platform_driver(dcc_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver");
+
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V2 3/5] DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver

[Souradeep Chowdhury]

The DCC is a DMA engine designed to store register values either in
case of a system crash or in case of software triggers manually done
by the user.Using DCC hardware and the sysfs interface of the driver
the user can exploit various functionalities of DCC.The user can specify
the register addresses,the values of which is stored by DCC in it's
dedicated SRAM.The register addresses can be used either to read from,
write to,first read and store value and then write or to loop.All these
options can be exploited using the sysfs interface given to the user.
Following are the sysfs interfaces exposed in DCC driver which are
documented
1)trigger
2)config
3)config_write
4)config_reset
5)enable
6)rd_mod_wr
7)loop

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 Documentation/ABI/testing/sysfs-driver-dcc | 114 +++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc

diff --git a/Documentation/ABI/testing/sysfs-driver-dcc b/Documentation/ABI/testing/sysfs-driver-dcc
new file mode 100644
index 0000000..05d24f0
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-dcc
@@ -0,0 +1,114 @@
+What:           /sys/bus/platform/devices/.../trigger
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This is the sysfs interface for manual software
+		triggers.The user can simply enter a 1 against
+		the sysfs file and enable a manual trigger.
+		Example:
+		echo  1 > /sys/bus/platform/devices/.../trigger
+
+What:           /sys/bus/platform/devices/.../enable
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This sysfs interface is used for enabling the
+		the dcc hardware.Without this being set to 1,
+		the dcc hardware ceases to function.
+		Example:
+		echo  0 > /sys/bus/platform/devices/.../enable
+		(disable interface)
+		echo  1 > /sys/bus/platform/devices/.../enable
+		(enable interface)
+
+What:           /sys/bus/platform/devices/.../config
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This is the most commonly used sysfs interface
+		file and this basically stores the addresses of
+		the registers which needs to be read in case of
+		a hardware crash or manual software triggers.
+		Example:
+		echo  0x80000010 10 > /sys/bus/platform/devices/../config
+		This specifies that 10 words starting from address
+		0x80000010 is to be read.In case there are no words to be
+		specified we can simply enter the address.
+
+What:           /sys/bus/platform/devices/.../config_write
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file allows user to write a value to the register
+		address given as argument.The values are entered in the
+		form of <register_address> <value>.The reason for this
+		feature of dcc is that for accessing certain registers
+		it is necessary to set some bits of soe other register.
+		That is achievable by giving DCC this privelege.
+		Example:
+		echo 0x80000000 0xFF > /sys/bus/platform/devices/.../config_write
+
+What:           /sys/bus/platform/devices/.../config_reset
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to reset the configuration of
+		a dcc driver to the default configuration.
+		Example:
+		echo  1 > /sys/bus/platform/devices/.../config_reset
+
+What:           /sys/bus/platform/devices/.../loop
+Date:		March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to enter the loop count as dcc
+		driver gives the option to loop multiple times on
+		the same register and store the values for each
+		loop.This is done to capture the changing values
+		of a register with time which comes handy for
+		debugging purposes.
+		Example:
+		echo 10 > /sys/bus/platform/devices/10a2000.dcc/loop
+		(Setting the loop count to 10)
+		echo  0x80000010 10 > /sys/bus/platform/devices/.../config
+                (Read 10 words starting from address 0x80000010O)
+		echo 1 > /sys/bus/platform/devices/.../loop
+		(Terminate the loop by writing a count of 1 to the loop sysfs node)
+
+What:           /sys/bus/platform/devices/.../rd_mod_wr
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to read the value of the register
+		and then write the value given as an argument to the
+		register address in config.The address argument should
+		be given of the form <mask> <value>.For debugging
+		purposes sometimes we need to first read from a register
+		and then set some values to the register.
+		Example:
+		echo 0x80000000 > /sys/bus/platform/devices/.../config
+		(Set the address in config file)
+		echo 0xF 0xA > /sys/bus/platform/devices/.../rd_mod_wr
+		(Provide the mask and the value to write)
+
+What:           /sys/bus/platform/devices/.../ready
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to check the status of the dcc
+		hardware if it's ready to take the inputs.
+		Example:
+		cat /sys/bus/platform/devices/.../ready
+
+What:		/sys/bus/platform/devices/.../curr_list
+Date:		February 2021
+Contact:	Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This attribute is used to enter the linklist to be
+		used while appending addresses.The range of values
+		for this can be from 0 to 3.This feature is given in
+		order to use certain linkedlist for certain debugging
+		purposes.
+		Example:
+		echo 0 > /sys/bus/platform/devices/10a2000.dcc/curr_list
+
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V2 4/5] MAINTAINERS: Add the entry for DCC(Data Capture and Compare) driver support

[Souradeep Chowdhury]

Added the entries for all the files added as a part of driver support for
DCC(Data Capture and Compare).

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85c..fb28218 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4969,6 +4969,14 @@ F:	include/linux/tfrc.h
 F:	include/uapi/linux/dccp.h
 F:	net/dccp/

+QTI DCC DRIVER
+M:	Souradeep Chowdhury <schowdhu@codeaurora.org>
+L:	linux-arm-msm@vger.kernel.org
+S:	Maintained
+F:	Documentation/ABI/testing/sysfs-driver-dcc
+F:	Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
+F:	drivers/soc/qcom/dcc.c
+
 DECnet NETWORK LAYER
 L:	linux-decnet-user@lists.sourceforge.net
 S:	Orphan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V2 5/5] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node

[Souradeep Chowdhury]

Add the DCC(Data Capture and Compare) device tree node entry along with
the addresses for register regions.

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index e5bb17b..e5a39c4 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -654,6 +654,13 @@
 			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		dcc@10a2000 {
+			compatible = "qcom,sm8150-dcc", "qcom,dcc";
+			reg = <0x0 0x010a2000 0x0 0x1000>,
+			      <0x0 0x010ad000 0x0 0ox3000>;
+			reg-names = "dcc", "dcc-ram";
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH V2 5/5] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1928 bytes --]

Hi Souradeep,

I love your patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.12-rc4 next-20210326]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Souradeep-Chowdhury/Add-driver-support-for-Data-Capture-and-Compare-Engine-DCC-for-SM8150/20210325-160634
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r033-20210326 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project f490a5969bd52c8a48586f134ff8f02ccbb295b3)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/0day-ci/linux/commit/a59f8279377cb9513ef51e05858aeaed2d8c18dd
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Souradeep-Chowdhury/Add-driver-support-for-Data-Capture-and-Compare-Engine-DCC-for-SM8150/20210325-160634
        git checkout a59f8279377cb9513ef51e05858aeaed2d8c18dd
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/qcom/sm8150.dtsi:660.31-32 syntax error
>> FATAL ERROR: Unable to parse input tree

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 41824 bytes --]

Re: [PATCH V2 1/5] dt-bindings: Added the yaml bindings for DCC

[Rob Herring]

On Thu, 25 Mar 2021 13:32:32 +0530, Souradeep Chowdhury wrote:
> Documentation for Data Capture and Compare(DCC) device tree bindings
> in yaml format.
> 
> Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
> ---
>  .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 ++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH V3 0/5] Add driver support for Data Capture and Compare Engine(DCC) for SM8150

[Souradeep Chowdhury]

DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.In case of a system
crash or manual software triggers by the user the DCC hardware stores the value at the register
addresses which can be used for debugging purposes.The DCC driver provides the user with sysfs
interface to configure the register addresses.The options that the DCC hardware provides include
reading from registers,writing to registers,first reading and then writing to registers and looping
through the values of the same register.

In certain cases a register write needs to be executed for accessing the rest of the registers,
also the user might want to record the changing values of a register with time for which he has the
option to use the loop feature.

The options mentioned above are exposed to the user by sysfs files once the driver is probed.The
details and usage of this sysfs files are documented in Documentation/ABI/testing/sysfs-driver-dcc.

As an example let us consider a couple of debug scenarios where DCC has been proved to be effective
for debugging purposes:-

i)TimeStamp Related Issue

On SC7180, there was a coresight timestamp issue where it would occasionally be all 0 instead of proper
timestamp values.

Proper timestamp:
Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e

Zero timestamp:
Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2

Now this is a non-fatal issue and doesn't need a system reset, but still needs
to be rootcaused and fixed for those who do care about coresight etm traces.
Since this is a timestamp issue, we would be looking for any timestamp related
clocks and such.

o we get all the clk register details from IP documentation and configure it
via DCC config syfs node. Before that we set the current linked list.

/* Set the current linked list */
echo 3 > /sys/bus/platform/devices/10a2000.dcc/curr_list

/* Program the linked list with the addresses */
echo 0x10c004 > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c008 > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c00c > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c010 > /sys/bus/platform/devices/10a2000.dcc/config
..... and so on for other timestamp related clk registers

/* Other way of specifying is in "addr len" pair, in below case it
specifies to capture 4 words starting 0x10C004 */

echo 0x10C004 4 > /sys/bus/platform/devices/10a2000.dcc/config

/* Enable DCC */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/enable

/* Run the timestamp test for working case */

/* Send SW trigger */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger

/* Read SRAM */
cat /dev/dcc_sram > dcc_sram1.bin

/* Run the timestamp test for non-working case */

/* Send SW trigger */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger

/* Read SRAM */
cat /dev/dcc_sram > dcc_sram2.bin

Get the parser from [1] and checkout the latest branch.

/* Parse the SRAM bin */
python dcc_parser.py -s dcc_sram1.bin --v2 -o output/
python dcc_parser.py -s dcc_sram2.bin --v2 -o output/

Sample parsed output of dcc_sram1.bin:

<hwioDump version="1">
        <timestamp>03/14/21</timestamp>
	        <generator>Linux DCC Parser</generator>
		        <chip name="None" version="None">
				<register address="0x0010c004" value="0x80000000" />
				<register address="0x0010c008" value="0x00000008" />
				<register address="0x0010c00c" value="0x80004220" />
				<register address="0x0010c010" value="0x80000000" />
			</chip>
	<next_ll_offset>next_ll_offset : 0x1c </next_ll_offset>
</hwioDump>

ii)NOC register errors

A particular class of registers called NOC which are functional registers was reporting
errors while logging the values.To trace these errors the DCC has been used effectively.
The steps followed were similar to the ones mentioned above.
In addition to NOC registers a few other dependent registers were configured in DCC to
monitor it's values during a crash. A look at the dependent register values revealed that
the crash was happening due to a secured access to one of these dependent registers.
All these debugging activity and finding the root cause was achieved using DCC.

DCC parser is available at the following open source location

https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser

Souradeep Chowdhury (5):
  dt-bindings: Added the yaml bindings for DCC
  soc: qcom: dcc:Add driver support for Data Capture and Compare
    unit(DCC)
  DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver
  MAINTAINERS:Add the entry for DCC(Data Capture and Compare) driver
    support
  arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support
    node

 Documentation/ABI/testing/sysfs-driver-dcc         |  114 ++
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      |   49 +
 MAINTAINERS                                        |    8 +
 arch/arm64/boot/dts/qcom/sm8150.dtsi               |    7 +
 drivers/soc/qcom/Kconfig                           |    8 +
 drivers/soc/qcom/Makefile                          |    1 +
 drivers/soc/qcom/dcc.c                             | 1549 ++++++++++++++++++++
 7 files changed, 1736 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
 create mode 100644 drivers/soc/qcom/dcc.c

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V3 1/5] dt-bindings: Added the yaml bindings for DCC

[Souradeep Chowdhury]

Documentation for Data Capture and Compare(DCC) device tree bindings
in yaml format.

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
new file mode 100644
index 0000000..c6e0a9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Data Capture and Compare
+
+maintainers:
+  - Souradeep Chowdhury <schowdhu@codeaurora.org>
+
+description: |
+    DCC (Data Capture and Compare) is a DMA engine which is used to save
+    configuration data or system memory contents during catastrophic failure
+    or SW trigger.DCC is used to capture and store data for debugging purpose
+
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,sm8150-dcc
+      - const: qcom,dcc
+
+  reg:
+    items:
+      - description: DCC base register region
+      - description: DCC RAM base register region
+
+  reg-names:
+    items:
+      - const: dcc
+      - const: dcc-ram
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+additionalProperties: false
+
+examples:
+  - |
+    dcc@10a2000{
+                compatible = "qcom,sm8150-dcc","qcom,dcc";
+                reg = <0x010a2000  0x1000>,
+                      <0x010ad000  0x2000>;
+                reg-names = "dcc", "dcc-ram";
+    };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V3 2/5] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)

[Souradeep Chowdhury]

The DCC is a DMA Engine designed to capture and store data
during system crash or software triggers.The DCC operates
based on user inputs via the sysfs interface.The user gives
addresses as inputs and these addresses are stored in the
form of linkedlists.In case of a system crash or a manual
software trigger by the user through the sysfs interface,
the dcc captures and stores the values at these addresses.
This patch contains the driver which has all the methods
pertaining to the sysfs interface, auxiliary functions to
support all the four fundamental operations of dcc namely
read, write, first read then write and loop.The probe method
here instantiates all the resources necessary for dcc to
operate mainly the dedicated dcc sram where it stores the
values.The DCC driver can be used for debugging purposes
without going for a reboot since it can perform manual
triggers.

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 drivers/soc/qcom/Kconfig  |    8 +
 drivers/soc/qcom/Makefile |    1 +
 drivers/soc/qcom/dcc.c    | 1549 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1558 insertions(+)
 create mode 100644 drivers/soc/qcom/dcc.c

diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 79b568f..8819e0b 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -69,6 +69,14 @@ config QCOM_LLCC
 	  SDM845. This provides interfaces to clients that use the LLCC.
 	  Say yes here to enable LLCC slice driver.

+config QCOM_DCC
+	tristate "Qualcomm Technologies, Inc. Data Capture and Compare engine driver"
+	depends on ARCH_QCOM || COMPILE_TEST
+	help
+	  This option enables driver for Data Capture and Compare engine. DCC
+	  driver provides interface to configure DCC block and read back
+	  captured data from DCC's internal SRAM.
+
 config QCOM_KRYO_L2_ACCESSORS
 	bool
 	depends on ARCH_QCOM && ARM64 || COMPILE_TEST
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index ad675a6..1b00870 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
 obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
 obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
+obj-$(CONFIG_QCOM_DCC) += dcc.o
diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c
new file mode 100644
index 0000000..a55d8ca7
--- /dev/null
+++ b/drivers/soc/qcom/dcc.c
@@ -0,0 +1,1549 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/cdev.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+
+#define TIMEOUT_US		100
+
+#define dcc_writel(drvdata, val, off)					\
+	writel((val), drvdata->base + dcc_offset_conv(drvdata, off))
+#define dcc_readl(drvdata, off)						\
+	readl(drvdata->base + dcc_offset_conv(drvdata, off))
+
+#define dcc_sram_readl(drvdata, off)					\
+	readl(drvdata->ram_base + off)
+
+#define DCC_SRAM_NODE "dcc_sram"
+
+/* DCC registers */
+#define DCC_HW_INFO			0x04
+#define DCC_LL_NUM_INFO			0x10
+#define DCC_STATUS			0x1C
+#define DCC_LL_LOCK(m)			(0x34 + 0x80 * m)
+#define DCC_LL_CFG(m)			(0x38 + 0x80 * m)
+#define DCC_LL_BASE(m)			(0x3c + 0x80 * m)
+#define DCC_FD_BASE(m)			(0x40 + 0x80 * m)
+#define DCC_LL_TIMEOUT(m)		(0x44 + 0x80 * m)
+#define DCC_LL_INT_ENABLE(m)		(0x4C + 0x80 * m)
+#define DCC_LL_INT_STATUS(m)		(0x50 + 0x80 * m)
+#define DCC_LL_SW_TRIGGER(m)		(0x60 + 0x80 * m)
+#define DCC_LL_BUS_ACCESS_STATUS(m)	(0x64 + 0x80 * m)
+
+#define DCC_MAP_LEVEL1			0x18
+#define DCC_MAP_LEVEL2			0x34
+#define DCC_MAP_LEVEL3			0x4C
+
+#define DCC_MAP_OFFSET1			0x10
+#define DCC_MAP_OFFSET2			0x18
+#define DCC_MAP_OFFSET3			0x1C
+#define DCC_MAP_OFFSET4			0x8
+
+#define DCC_FIX_LOOP_OFFSET		16
+#define DCC_VER_INFO_BIT		9
+
+#define DCC_READ			0
+#define DCC_WRITE			1
+#define DCC_LOOP			2
+#define DCC_READ_WRITE			3
+
+#define MAX_DCC_OFFSET			GENMASK(9, 2)
+#define MAX_DCC_LEN			GENMASK(6, 0)
+#define MAX_LOOP_CNT			GENMASK(7, 0)
+
+#define DCC_ADDR_DESCRIPTOR		0x00
+#define DCC_LOOP_DESCRIPTOR		BIT(30)
+#define DCC_RD_MOD_WR_DESCRIPTOR	BIT(31)
+#define DCC_LINK_DESCRIPTOR		GENMASK(31, 30)
+
+#define DCC_READ_IND			0x00
+#define DCC_WRITE_IND			(BIT(28))
+
+#define DCC_AHB_IND			0x00
+#define DCC_APB_IND			BIT(29)
+
+#define DCC_MAX_LINK_LIST		8
+#define DCC_INVALID_LINK_LIST		GENMASK(7, 0)
+
+#define DCC_VER_MASK1			GENMASK(6, 0)
+#define DCC_VER_MASK2			GENMASK(5, 0)
+
+#define DCC_RD_MOD_WR_ADDR              0xC105E
+
+struct qcom_dcc_config {
+	const int dcc_ram_offset;
+};
+
+enum dcc_descriptor_type {
+	DCC_ADDR_TYPE,
+	DCC_LOOP_TYPE,
+	DCC_READ_WRITE_TYPE,
+	DCC_WRITE_TYPE
+};
+
+enum dcc_mem_map_ver {
+	DCC_MEM_MAP_VER1 = 1,
+	DCC_MEM_MAP_VER2 = 2,
+	DCC_MEM_MAP_VER3 = 3
+};
+
+struct dcc_config_entry {
+	u32				base;
+	u32				offset;
+	u32				len;
+	u32				index;
+	u32				loop_cnt;
+	u32				write_val;
+	u32				mask;
+	bool				apb_bus;
+	enum dcc_descriptor_type	desc_type;
+	struct list_head		list;
+};
+
+struct dcc_drvdata {
+	void __iomem		*base;
+	u32			reg_size;
+	struct device		*dev;
+	struct mutex		mutex;
+	void __iomem		*ram_base;
+	u32			ram_size;
+	u32			ram_offset;
+	enum dcc_mem_map_ver	mem_map_ver;
+	u32			ram_cfg;
+	u32			ram_start;
+	bool			*enable;
+	bool			*configured;
+	bool			interrupt_disable;
+	char			*sram_node;
+	struct cdev		sram_dev;
+	struct class		*sram_class;
+	struct list_head	*cfg_head;
+	u32			*nr_config;
+	u32			nr_link_list;
+	u8			curr_list;
+	u8			loopoff;
+};
+
+struct dcc_cfg_attr {
+	u32	addr;
+	u32	prev_addr;
+	u32	prev_off;
+	u32	link;
+	u32	sram_offset;
+};
+
+struct dcc_cfg_loop_attr {
+	u32	loop;
+	bool	loop_start;
+	u32	loop_cnt;
+	u32	loop_len;
+	u32	loop_off;
+};
+
+static size_t dcc_offset_conv(struct dcc_drvdata *drvdata, size_t off)
+{
+	if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL3)
+			return (off - DCC_MAP_OFFSET3);
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET2);
+		else if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL1)
+			return (off - DCC_MAP_OFFSET1);
+	} else if (drvdata->mem_map_ver == DCC_MEM_MAP_VER2) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET4);
+	}
+	return off;
+}
+
+static int dcc_sram_writel(struct dcc_drvdata *drvdata,
+					u32 val, u32 off)
+{
+	if (unlikely(off > (drvdata->ram_size - 4)))
+		return -EINVAL;
+
+	writel((val), drvdata->ram_base + off);
+
+	return 0;
+}
+
+static bool dcc_ready(struct dcc_drvdata *drvdata)
+{
+	u32 val;
+
+	/* poll until DCC ready */
+	if (!readl_poll_timeout((drvdata->base + DCC_STATUS), val,
+				(FIELD_GET(GENMASK(1, 0), val) == 0), 1, TIMEOUT_US))
+		return true;
+
+	return false;
+}
+
+static int dcc_read_status(struct dcc_drvdata *drvdata)
+{
+	int curr_list;
+	u32 bus_status;
+	u32 ll_cfg = 0;
+	u32 tmp_ll_cfg = 0;
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+
+		bus_status = dcc_readl(drvdata, DCC_LL_BUS_ACCESS_STATUS(curr_list));
+
+		if (bus_status) {
+			dev_err(drvdata->dev,
+				"Read access error for list %d err: 0x%x.\n",
+				curr_list, bus_status);
+
+			ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
+			tmp_ll_cfg = ll_cfg & ~BIT(9);
+			dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
+			dcc_writel(drvdata, 0x3,
+				DCC_LL_BUS_ACCESS_STATUS(curr_list));
+			dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
+			return -ENODATA;
+		}
+	}
+
+	return 0;
+}
+
+static int dcc_sw_trigger(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+	int curr_list;
+	u32 ll_cfg = 0;
+	u32 tmp_ll_cfg = 0;
+
+	mutex_lock(&drvdata->mutex);
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+		ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
+		tmp_ll_cfg = ll_cfg & ~BIT(9);
+		dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
+		dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
+		dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
+	}
+
+	if (!dcc_ready(drvdata)) {
+		dev_err(drvdata->dev,
+			"DCC is busy after receiving sw tigger.\n");
+		ret = -EBUSY;
+		goto err;
+	}
+
+	ret = dcc_read_status(drvdata);
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static void _dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg)
+{
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	cfg->prev_off = 0;
+	cfg->prev_addr = cfg->addr;
+}
+
+static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata,
+				  struct dcc_config_entry *entry,
+				  struct dcc_cfg_attr *cfg)
+{
+	int ret;
+
+	if (cfg->link) {
+		/*
+		 * write new offset = 1 to continue
+		 * processing the list
+		 */
+
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		_dcc_ll_cfg_reset_link(cfg);
+	}
+
+	cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR;
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	ret = dcc_sram_writel(drvdata, entry->mask, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	cfg->addr = 0;
+	return ret;
+}
+
+static int _dcc_ll_cfg_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry,
+			    struct dcc_cfg_attr *cfg,
+			    struct dcc_cfg_loop_attr *cfg_loop,
+			    u32 *total_len)
+{
+
+	int ret;
+
+	/* Check if we need to write link of prev entry */
+	if (cfg->link) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+	}
+
+	if (cfg_loop->loop_start) {
+		cfg_loop->loop = (cfg->sram_offset - cfg_loop->loop_off) / 4;
+		cfg_loop->loop |= (cfg_loop->loop_cnt << drvdata->loopoff) &
+		GENMASK(27, drvdata->loopoff);
+		cfg_loop->loop |= DCC_LOOP_DESCRIPTOR;
+		*total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt;
+
+		ret = dcc_sram_writel(drvdata, cfg_loop->loop, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+
+		cfg_loop->loop_start = false;
+		cfg_loop->loop_len = 0;
+		cfg_loop->loop_off = 0;
+	} else {
+		cfg_loop->loop_start = true;
+		cfg_loop->loop_cnt = entry->loop_cnt - 1;
+		cfg_loop->loop_len = *total_len;
+		cfg_loop->loop_off = cfg->sram_offset;
+	}
+
+	/* Reset link and prev_off */
+
+	_dcc_ll_cfg_reset_link(cfg);
+
+	return ret;
+}
+
+static int _dcc_ll_cfg_write(struct dcc_drvdata *drvdata,
+			     struct dcc_config_entry *entry,
+			     struct dcc_cfg_attr *cfg,
+			     u32 *total_len)
+{
+	u32 off;
+	int ret;
+
+	if (cfg->link) {
+		/*
+		 * write new offset = 1 to continue
+		 * processing the list
+		 */
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		cfg->addr = 0x00;
+		cfg->prev_off = 0;
+		cfg->prev_addr = cfg->addr;
+	}
+
+	off = entry->offset/4;
+	/* write new offset-length pair to correct position */
+	cfg->link |= ((off & GENMASK(7, 0)) | BIT(15) | ((entry->len << 8) & GENMASK(14, 8)));
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	/* Address type */
+	cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND;
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	return ret;
+}
+
+static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
+			       struct dcc_config_entry *entry,
+			       struct dcc_cfg_attr *cfg,
+			       u32 *pos, u32 *total_len)
+{
+	int ret;
+	u32 off;
+
+	cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
+
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND;
+
+	off = entry->offset/4;
+
+	*total_len += entry->len * 4;
+
+	if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) {
+		/* Check if we need to write prev link entry */
+		if (cfg->link) {
+			ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+			if (ret)
+				return ret;
+			cfg->sram_offset += 4;
+		}
+		dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset);
+
+		/* Write address */
+		ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+
+		/* Reset link and prev_off */
+		cfg->link = 0;
+		cfg->prev_off = 0;
+	}
+
+	if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
+		dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n",
+		entry->base, entry->offset);
+		ret = -EINVAL;
+		return ret;
+	}
+
+	if (cfg->link) {
+		/*
+		 * link already has one offset-length so new
+		 * offset-length needs to be placed at
+		 * bits [29:15]
+		 */
+		*pos = 15;
+
+		/* Clear bits [31:16] */
+		cfg->link &= GENMASK(14, 0);
+	} else {
+		/*
+		 * link is empty, so new offset-length needs
+		 * to be placed at bits [15:0]
+		 */
+		*pos = 0;
+		cfg->link = 1 << 15;
+	}
+
+	/* write new offset-length pair to correct position */
+	cfg->link |= (((off-cfg->prev_off) & GENMASK(7, 0)) |
+		     ((entry->len << 8) & GENMASK(14, 8))) << *pos;
+
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	if (*pos) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		cfg->link = 0;
+	}
+
+	cfg->prev_off  = off + entry->len - 1;
+	cfg->prev_addr = cfg->addr;
+	return ret;
+}
+
+static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list)
+{
+	int ret = 0;
+	u32 total_len, pos;
+	struct dcc_config_entry *entry;
+	struct dcc_cfg_attr cfg;
+	struct dcc_cfg_loop_attr cfg_loop;
+
+	memset(&cfg, 0, sizeof(cfg));
+	memset(&cfg_loop, 0, sizeof(cfg_loop));
+	cfg.sram_offset = drvdata->ram_cfg * 4;
+	total_len = 0;
+
+	list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+			ret = _dcc_ll_cfg_read_write(drvdata, entry, &cfg);
+			if (ret)
+				goto overstep;
+			break;
+
+		case DCC_LOOP_TYPE:
+			ret = _dcc_ll_cfg_loop(drvdata, entry, &cfg, &cfg_loop, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+
+		case DCC_WRITE_TYPE:
+			ret = _dcc_ll_cfg_write(drvdata, entry, &cfg, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+
+		default:
+			ret = _dcc_ll_cfg_default(drvdata, entry, &cfg, &pos, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+		}
+	}
+
+	if (cfg.link) {
+		ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
+		if (ret)
+			goto overstep;
+		cfg.sram_offset += 4;
+	}
+
+	if (cfg_loop.loop_start) {
+		dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* Handling special case of list ending with a rd_mod_wr */
+	if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) {
+		cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0);
+		cfg.addr |= DCC_ADDR_DESCRIPTOR;
+		ret = dcc_sram_writel(drvdata, cfg.addr, cfg.sram_offset);
+		if (ret)
+			goto overstep;
+		cfg.sram_offset += 4;
+	}
+
+	/* Setting zero to indicate end of the list */
+	cfg.link = DCC_LINK_DESCRIPTOR;
+	ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
+	if (ret)
+		goto overstep;
+	cfg.sram_offset += 4;
+
+	/* Update ram_cfg and check if the data will overstep */
+
+	drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4;
+
+	if (cfg.sram_offset + total_len > drvdata->ram_size) {
+		cfg.sram_offset += total_len;
+		goto overstep;
+	}
+
+	drvdata->ram_start = cfg.sram_offset/4;
+	return 0;
+overstep:
+	ret = -EINVAL;
+	memset_io(drvdata->ram_base, 0, drvdata->ram_size);
+	dev_err(drvdata->dev, "DCC SRAM oversteps, 0x%x (0x%x)\n",
+	cfg.sram_offset, drvdata->ram_size);
+
+err:
+	return ret;
+}
+
+static int dcc_valid_list(struct dcc_drvdata *drvdata, int curr_list)
+{
+	u32 lock_reg;
+
+	if (list_empty(&drvdata->cfg_head[curr_list]))
+		return -EINVAL;
+
+	if (drvdata->enable[curr_list]) {
+		dev_err(drvdata->dev, "List %d is already enabled\n",
+				curr_list);
+		return -EINVAL;
+	}
+
+	lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(curr_list));
+	if (lock_reg & 0x1) {
+		dev_err(drvdata->dev, "List %d is already locked\n",
+				curr_list);
+		return -EINVAL;
+	}
+
+	dev_err(drvdata->dev, "DCC list passed %d\n", curr_list);
+	return 0;
+}
+
+static bool is_dcc_enabled(struct dcc_drvdata *drvdata)
+{
+	bool dcc_enable = false;
+	int list;
+
+	for (list = 0; list < DCC_MAX_LINK_LIST; list++) {
+		if (drvdata->enable[list]) {
+			dcc_enable = true;
+			break;
+		}
+	}
+
+	return dcc_enable;
+}
+
+static int dcc_enable(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+	int list;
+	u32 ram_cfg_base;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (!is_dcc_enabled(drvdata)) {
+		memset_io(drvdata->ram_base,
+			0xDE, drvdata->ram_size);
+	}
+
+	for (list = 0; list < drvdata->nr_link_list; list++) {
+
+		if (dcc_valid_list(drvdata, list))
+			continue;
+
+		/* 1. Take ownership of the list */
+		dcc_writel(drvdata, BIT(0), DCC_LL_LOCK(list));
+
+		/* 2. Program linked-list in the SRAM */
+		ram_cfg_base = drvdata->ram_cfg;
+		ret = __dcc_ll_cfg(drvdata, list);
+		if (ret) {
+			dcc_writel(drvdata, 0, DCC_LL_LOCK(list));
+			dev_info(drvdata->dev, "DCC ram programming failed\n");
+			goto err;
+		}
+
+		/* 3. program DCC_RAM_CFG reg */
+		dcc_writel(drvdata, ram_cfg_base +
+			drvdata->ram_offset/4, DCC_LL_BASE(list));
+		dcc_writel(drvdata, drvdata->ram_start +
+			drvdata->ram_offset/4, DCC_FD_BASE(list));
+		dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list));
+
+		/* 4. Clears interrupt status register */
+		dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list));
+		dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)),
+					DCC_LL_INT_STATUS(list));
+
+		dev_info(drvdata->dev, "All values written to enable.\n");
+		/* Make sure all config is written in sram */
+		mb();
+
+		drvdata->enable[list] = true;
+
+		/* 5. Configure trigger */
+		dcc_writel(drvdata, BIT(9), DCC_LL_CFG(list));
+	}
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static void dcc_disable(struct dcc_drvdata *drvdata)
+{
+	int curr_list;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (!dcc_ready(drvdata))
+		dev_err(drvdata->dev, "DCC is not ready Disabling DCC...\n");
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+		dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list));
+		dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list));
+		dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list));
+		dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
+		drvdata->enable[curr_list] = false;
+	}
+	memset_io(drvdata->ram_base, 0, drvdata->ram_size);
+	drvdata->ram_cfg = 0;
+	drvdata->ram_start = 0;
+	mutex_unlock(&drvdata->mutex);
+}
+
+static ssize_t curr_list_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list == DCC_INVALID_LINK_LIST) {
+		dev_err(dev, "curr_list is not set.\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = scnprintf(buf, PAGE_SIZE, "%d\n",	drvdata->curr_list);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t curr_list_store(struct device *dev,
+						struct device_attribute *attr,
+						const char *buf, size_t size)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	unsigned long val;
+	u32 lock_reg;
+	bool dcc_enable = false;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val >= drvdata->nr_link_list)
+		return -EINVAL;
+
+	mutex_lock(&drvdata->mutex);
+
+	dcc_enable = is_dcc_enabled(drvdata);
+	if (drvdata->curr_list != DCC_INVALID_LINK_LIST	&& dcc_enable) {
+		dev_err(drvdata->dev, "DCC is enabled, please disable it first.\n");
+		mutex_unlock(&drvdata->mutex);
+		return -EINVAL;
+	}
+
+	lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
+	if (lock_reg & 0x1) {
+		dev_err(drvdata->dev, "DCC linked list is already configured\n");
+		mutex_unlock(&drvdata->mutex);
+		return -EINVAL;
+	}
+	drvdata->curr_list = val;
+	mutex_unlock(&drvdata->mutex);
+
+	return size;
+}
+
+static DEVICE_ATTR_RW(curr_list);
+
+
+static ssize_t trigger_store(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	int ret = 0;
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+	if (val != 1)
+		return -EINVAL;
+
+	ret = dcc_sw_trigger(drvdata);
+	if (!ret)
+		ret = size;
+
+	return ret;
+}
+static DEVICE_ATTR_WO(trigger);
+
+static ssize_t enable_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	bool dcc_enable = false;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	dcc_enable = is_dcc_enabled(drvdata);
+
+	ret = scnprintf(buf, PAGE_SIZE, "%u\n",
+				(unsigned int)dcc_enable);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t enable_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	int ret = 0;
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val)
+		ret = dcc_enable(drvdata);
+	else
+		dcc_disable(drvdata);
+
+	if (!ret)
+		ret = size;
+
+	return ret;
+
+}
+
+static DEVICE_ATTR_RW(enable);
+
+static ssize_t config_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	struct dcc_config_entry *entry;
+	char local_buf[64];
+	int len = 0, count = 0;
+
+	buf[0] = '\0';
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		count = -EINVAL;
+		goto err;
+	}
+
+	list_for_each_entry(entry,
+	&drvdata->cfg_head[drvdata->curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+			len = snprintf(local_buf, 64, "Index: 0x%x, mask: 0x%x, val: 0x%x\n",
+				entry->index, entry->mask, entry->write_val);
+			break;
+		case DCC_LOOP_TYPE:
+			len = snprintf(local_buf, 64, "Index: 0x%x, Loop: %d\n",
+				entry->index, entry->loop_cnt);
+			break;
+		case DCC_WRITE_TYPE:
+			len = snprintf(local_buf, 64,
+				"Write Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
+				entry->index, entry->base, entry->offset, entry->len,
+				entry->apb_bus);
+			break;
+		default:
+			len = snprintf(local_buf, 64,
+				"Read Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
+				entry->index, entry->base, entry->offset,
+				entry->len, entry->apb_bus);
+		}
+
+		if ((count + len) > PAGE_SIZE) {
+			dev_err(dev, "DCC: Couldn't write complete config\n");
+			break;
+		}
+		strlcat(buf, local_buf, PAGE_SIZE);
+		count += len;
+	}
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return count;
+}
+
+static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
+				unsigned int len, int apb_bus)
+{
+	int ret;
+	struct dcc_config_entry *entry, *pentry;
+	unsigned int base, offset;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(drvdata->dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (!len || len > (drvdata->ram_size / 8)) {
+		dev_err(drvdata->dev, "DCC: Invalid length\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	base = addr & GENMASK(31, 4);
+
+	if (!list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
+		pentry = list_last_entry(&drvdata->cfg_head[drvdata->curr_list],
+			struct dcc_config_entry, list);
+
+		if (pentry->desc_type == DCC_ADDR_TYPE &&
+				addr >= (pentry->base + pentry->offset) &&
+				addr <= (pentry->base +
+					pentry->offset + MAX_DCC_OFFSET)) {
+
+			/* Re-use base address from last entry */
+			base = pentry->base;
+
+			if ((pentry->len * 4 + pentry->base + pentry->offset)
+					== addr) {
+				len += pentry->len;
+
+				if (len > MAX_DCC_LEN)
+					pentry->len = MAX_DCC_LEN;
+				else
+					pentry->len = len;
+
+				addr = pentry->base + pentry->offset +
+					pentry->len * 4;
+				len -= pentry->len;
+			}
+		}
+	}
+
+	offset = addr - base;
+
+	while (len) {
+		entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+		if (!entry) {
+			ret = -ENOMEM;
+			goto err;
+		}
+
+		entry->base = base;
+		entry->offset = offset;
+		entry->len = min_t(u32, len, MAX_DCC_LEN);
+		entry->index = drvdata->nr_config[drvdata->curr_list]++;
+		entry->desc_type = DCC_ADDR_TYPE;
+		entry->apb_bus = apb_bus;
+		INIT_LIST_HEAD(&entry->list);
+		list_add_tail(&entry->list,
+			&drvdata->cfg_head[drvdata->curr_list]);
+
+		len -= entry->len;
+		offset += MAX_DCC_LEN * 4;
+	}
+
+	mutex_unlock(&drvdata->mutex);
+	return 0;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t config_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	int ret, len, apb_bus;
+	unsigned int base;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	int nval;
+
+	nval = sscanf(buf, "%x %i %d", &base, &len, &apb_bus);
+	if (nval <= 0 || nval > 3)
+		return -EINVAL;
+
+	if (nval == 1) {
+		len = 1;
+		apb_bus = 0;
+	} else if (nval == 2) {
+		apb_bus = 0;
+	} else {
+		apb_bus = 1;
+	}
+
+	ret = dcc_config_add(drvdata, base, len, apb_bus);
+	if (ret)
+		return ret;
+
+	return size;
+
+}
+
+static DEVICE_ATTR_RW(config);
+
+static void dcc_config_reset(struct dcc_drvdata *drvdata)
+{
+	struct dcc_config_entry *entry, *temp;
+	int curr_list;
+
+	mutex_lock(&drvdata->mutex);
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		list_for_each_entry_safe(entry, temp,
+			&drvdata->cfg_head[curr_list], list) {
+			list_del(&entry->list);
+			devm_kfree(drvdata->dev, entry);
+			drvdata->nr_config[curr_list]--;
+		}
+	}
+	drvdata->ram_start = 0;
+	drvdata->ram_cfg = 0;
+	mutex_unlock(&drvdata->mutex);
+}
+
+
+static ssize_t config_reset_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val)
+		dcc_config_reset(drvdata);
+
+	return size;
+}
+
+static DEVICE_ATTR_WO(config_reset);
+
+static ssize_t ready_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (!drvdata->enable[drvdata->curr_list]) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = scnprintf(buf, PAGE_SIZE, "%u\n",
+			(unsigned int)FIELD_GET(BIT(1), dcc_readl(drvdata, DCC_STATUS)));
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_RO(ready);
+
+static ssize_t interrupt_disable_show(struct device *dev,
+						struct device_attribute *attr,
+						char *buf)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n",
+				(unsigned int)drvdata->interrupt_disable);
+}
+
+static ssize_t interrupt_disable_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	mutex_lock(&drvdata->mutex);
+	drvdata->interrupt_disable = (val ? 1:0);
+	mutex_unlock(&drvdata->mutex);
+	return size;
+}
+
+static DEVICE_ATTR_RW(interrupt_disable);
+
+static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt)
+{
+	struct dcc_config_entry *entry;
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry)
+		return -ENOMEM;
+
+	entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT);
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	entry->desc_type = DCC_LOOP_TYPE;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+
+	return 0;
+}
+
+static ssize_t loop_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	int ret;
+	unsigned long loop_cnt;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	if (kstrtoul(buf, 16, &loop_cnt)) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = dcc_add_loop(drvdata, loop_cnt);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&drvdata->mutex);
+	return size;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_WO(loop);
+
+static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask,
+				unsigned int val)
+{
+	int ret = 0;
+	struct dcc_config_entry *entry;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(drvdata->dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
+		dev_err(drvdata->dev, "DCC: No read address programmed\n");
+		ret = -EPERM;
+		goto err;
+	}
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	entry->desc_type = DCC_READ_WRITE_TYPE;
+	entry->mask = mask;
+	entry->write_val = val;
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t rd_mod_wr_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	int ret;
+	int nval;
+	unsigned int mask, val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	nval = sscanf(buf, "%x %x", &mask, &val);
+
+	if (nval <= 1 || nval > 2)
+		return -EINVAL;
+
+	ret = dcc_rd_mod_wr_add(drvdata, mask, val);
+	if (ret)
+		return ret;
+
+	return size;
+
+}
+
+static DEVICE_ATTR_WO(rd_mod_wr);
+
+static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr,
+				unsigned int write_val, int apb_bus)
+{
+	struct dcc_config_entry *entry;
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry)
+		return -ENOMEM;
+
+	entry->desc_type = DCC_WRITE_TYPE;
+	entry->base = addr & GENMASK(31, 4);
+	entry->offset = addr - entry->base;
+	entry->write_val = write_val;
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	entry->len = 1;
+	entry->apb_bus = apb_bus;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+
+	return 0;
+}
+
+static ssize_t config_write_store(struct device *dev,
+						struct device_attribute *attr,
+						const char *buf, size_t size)
+{
+	int ret;
+	int nval;
+	unsigned int addr, write_val;
+	int apb_bus = 0;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	nval = sscanf(buf, "%x %x %d", &addr, &write_val, &apb_bus);
+
+	if (nval <= 1 || nval > 3) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (nval == 3 && apb_bus != 0)
+		apb_bus = 1;
+
+	ret = dcc_add_write(drvdata, addr, write_val, apb_bus);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&drvdata->mutex);
+	return size;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_WO(config_write);
+
+static const struct device_attribute *dcc_attrs[] = {
+	&dev_attr_trigger,
+	&dev_attr_enable,
+	&dev_attr_config,
+	&dev_attr_config_reset,
+	&dev_attr_ready,
+	&dev_attr_interrupt_disable,
+	&dev_attr_loop,
+	&dev_attr_rd_mod_wr,
+	&dev_attr_curr_list,
+	&dev_attr_config_write,
+	NULL,
+};
+
+static int dcc_create_files(struct device *dev,
+					const struct device_attribute **attrs)
+{
+	int ret = 0, i;
+
+	for (i = 0; attrs[i] != NULL; i++) {
+		ret = device_create_file(dev, attrs[i]);
+		if (ret) {
+			dev_err(dev, "DCC: Couldn't create sysfs attribute: %s\n",
+				attrs[i]->attr.name);
+			break;
+		}
+	}
+	return ret;
+}
+
+static int dcc_sram_open(struct inode *inode, struct file *file)
+{
+	struct dcc_drvdata *drvdata = container_of(inode->i_cdev,
+		struct dcc_drvdata,
+		sram_dev);
+	file->private_data = drvdata;
+
+	return	0;
+}
+
+static ssize_t dcc_sram_read(struct file *file, char __user *data,
+						size_t len, loff_t *ppos)
+{
+	unsigned char *buf;
+	struct dcc_drvdata *drvdata = file->private_data;
+
+	/* EOF check */
+	if (drvdata->ram_size <= *ppos)
+		return 0;
+
+	if ((*ppos + len) > drvdata->ram_size)
+		len = (drvdata->ram_size - *ppos);
+
+	buf = kzalloc(len, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	memcpy_fromio(buf, drvdata->ram_base + *ppos, len);
+
+	if (copy_to_user(data, buf, len)) {
+		dev_err(drvdata->dev, "DCC: Couldn't copy all data to user\n");
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	*ppos += len;
+
+	kfree(buf);
+
+	return len;
+}
+
+static const struct file_operations dcc_sram_fops = {
+	.owner		= THIS_MODULE,
+	.open		= dcc_sram_open,
+	.read		= dcc_sram_read,
+	.llseek		= no_llseek,
+};
+
+static int dcc_sram_dev_register(struct dcc_drvdata *drvdata)
+{
+	int ret;
+	struct device *device;
+	dev_t dev;
+
+	ret = alloc_chrdev_region(&dev, 0, 1, drvdata->sram_node);
+	if (ret)
+		goto err_alloc;
+
+	cdev_init(&drvdata->sram_dev, &dcc_sram_fops);
+
+	drvdata->sram_dev.owner = THIS_MODULE;
+	ret = cdev_add(&drvdata->sram_dev, dev, 1);
+	if (ret)
+		goto err_cdev_add;
+
+	drvdata->sram_class = class_create(THIS_MODULE, drvdata->sram_node);
+	if (IS_ERR(drvdata->sram_class)) {
+		ret = PTR_ERR(drvdata->sram_class);
+		goto err_class_create;
+	}
+
+	device = device_create(drvdata->sram_class, NULL,
+						drvdata->sram_dev.dev, drvdata,
+						drvdata->sram_node);
+	if (IS_ERR(device)) {
+		ret = PTR_ERR(device);
+		goto err_dev_create;
+	}
+
+	return 0;
+err_dev_create:
+	class_destroy(drvdata->sram_class);
+err_class_create:
+	cdev_del(&drvdata->sram_dev);
+err_cdev_add:
+	unregister_chrdev_region(drvdata->sram_dev.dev, 1);
+err_alloc:
+	return ret;
+}
+
+static void dcc_sram_dev_deregister(struct dcc_drvdata *drvdata)
+{
+	device_destroy(drvdata->sram_class, drvdata->sram_dev.dev);
+	class_destroy(drvdata->sram_class);
+	cdev_del(&drvdata->sram_dev);
+	unregister_chrdev_region(drvdata->sram_dev.dev, 1);
+}
+
+static int dcc_sram_dev_init(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+
+	drvdata->sram_node = DCC_SRAM_NODE;
+	if (!drvdata->sram_node)
+		return -ENOMEM;
+
+	ret = dcc_sram_dev_register(drvdata);
+	if (ret)
+		dev_err(drvdata->dev, "DCC: sram node not registered.\n");
+
+	return ret;
+}
+
+static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata)
+{
+	dcc_sram_dev_deregister(drvdata);
+}
+
+static int dcc_probe(struct platform_device *pdev)
+{
+	int ret = 0, i;
+	struct device *dev = &pdev->dev;
+	struct dcc_drvdata *dcc;
+	struct resource *res;
+	const struct qcom_dcc_config *cfg;
+
+	dcc = devm_kzalloc(dev, sizeof(*dcc), GFP_KERNEL);
+	if (!dcc)
+		return -ENOMEM;
+
+	dcc->dev = &pdev->dev;
+	platform_set_drvdata(pdev, dcc);
+
+	dcc->base = devm_platform_ioremap_resource_byname(pdev, "dcc");
+	if (!dcc->base)
+		return -ENOMEM;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dcc-ram");
+	if (!res)
+		return -EINVAL;
+
+	dcc->ram_size = resource_size(res);
+
+	dcc->ram_base = devm_ioremap(dev, res->start, resource_size(res));
+	if (!dcc->ram_base)
+		return -ENOMEM;
+
+	cfg = of_device_get_match_data(&pdev->dev);
+	dcc->ram_offset = cfg->dcc_ram_offset;
+
+	if (FIELD_GET(BIT(DCC_VER_INFO_BIT), dcc_readl(dcc, DCC_HW_INFO))) {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER3;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;
+	} else if ((dcc_readl(dcc, DCC_HW_INFO) & DCC_VER_MASK2) == DCC_VER_MASK2) {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER2;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;
+	} else {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER1;
+		dcc->nr_link_list = DCC_MAX_LINK_LIST;
+	}
+
+	if ((dcc_readl(dcc, DCC_HW_INFO) & BIT(6)) == BIT(6))
+		dcc->loopoff = DCC_FIX_LOOP_OFFSET;
+	else
+		dcc->loopoff = get_bitmask_order((dcc->ram_size +
+				dcc->ram_offset) / 4 - 1);
+
+	mutex_init(&dcc->mutex);
+	dcc->enable = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(bool), GFP_KERNEL);
+	if (!dcc->enable)
+		return -ENOMEM;
+
+	dcc->configured = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(bool), GFP_KERNEL);
+	if (!dcc->configured)
+		return -ENOMEM;
+
+	dcc->nr_config = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(u32), GFP_KERNEL);
+	if (!dcc->nr_config)
+		return -ENOMEM;
+
+	dcc->cfg_head = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(struct list_head), GFP_KERNEL);
+	if (!dcc->cfg_head)
+		return -ENOMEM;
+
+	for (i = 0; i < dcc->nr_link_list; i++)
+		INIT_LIST_HEAD(&dcc->cfg_head[i]);
+
+
+	memset_io(dcc->ram_base, 0, dcc->ram_size);
+	dcc->curr_list = DCC_INVALID_LINK_LIST;
+	ret = dcc_sram_dev_init(dcc);
+	if (ret)
+		goto out;
+
+	ret = dcc_create_files(dev, dcc_attrs);
+	if (ret)
+		goto out;
+
+out:
+	return ret;
+}
+
+static int dcc_remove(struct platform_device *pdev)
+{
+	struct dcc_drvdata *drvdata = platform_get_drvdata(pdev);
+
+	dcc_sram_dev_exit(drvdata);
+
+	dcc_config_reset(drvdata);
+
+	return 0;
+}
+
+static const struct qcom_dcc_config sm8150_cfg = {
+	.dcc_ram_offset	= 0x5000,
+};
+
+static const struct of_device_id dcc_match_table[] = {
+	{ .compatible = "qcom,sm8150-dcc", .data = &sm8150_cfg },
+};
+MODULE_DEVICE_TABLE(of, dcc_match_table);
+
+static struct platform_driver dcc_driver = {
+	.probe					= dcc_probe,
+	.remove					= dcc_remove,
+	.driver					= {
+		.name		= "qcom-dcc",
+		.of_match_table	= dcc_match_table,
+	},
+};
+
+module_platform_driver(dcc_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver");
+
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V3 3/5] DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver

[Souradeep Chowdhury]

The DCC is a DMA engine designed to store register values either in
case of a system crash or in case of software triggers manually done
by the user.Using DCC hardware and the sysfs interface of the driver
the user can exploit various functionalities of DCC.The user can specify
the register addresses,the values of which is stored by DCC in it's
dedicated SRAM.The register addresses can be used either to read from,
write to,first read and store value and then write or to loop.All these
options can be exploited using the sysfs interface given to the user.
Following are the sysfs interfaces exposed in DCC driver which are
documented
1)trigger
2)config
3)config_write
4)config_reset
5)enable
6)rd_mod_wr
7)loop

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 Documentation/ABI/testing/sysfs-driver-dcc | 114 +++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc

diff --git a/Documentation/ABI/testing/sysfs-driver-dcc b/Documentation/ABI/testing/sysfs-driver-dcc
new file mode 100644
index 0000000..05d24f0
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-dcc
@@ -0,0 +1,114 @@
+What:           /sys/bus/platform/devices/.../trigger
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This is the sysfs interface for manual software
+		triggers.The user can simply enter a 1 against
+		the sysfs file and enable a manual trigger.
+		Example:
+		echo  1 > /sys/bus/platform/devices/.../trigger
+
+What:           /sys/bus/platform/devices/.../enable
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This sysfs interface is used for enabling the
+		the dcc hardware.Without this being set to 1,
+		the dcc hardware ceases to function.
+		Example:
+		echo  0 > /sys/bus/platform/devices/.../enable
+		(disable interface)
+		echo  1 > /sys/bus/platform/devices/.../enable
+		(enable interface)
+
+What:           /sys/bus/platform/devices/.../config
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This is the most commonly used sysfs interface
+		file and this basically stores the addresses of
+		the registers which needs to be read in case of
+		a hardware crash or manual software triggers.
+		Example:
+		echo  0x80000010 10 > /sys/bus/platform/devices/../config
+		This specifies that 10 words starting from address
+		0x80000010 is to be read.In case there are no words to be
+		specified we can simply enter the address.
+
+What:           /sys/bus/platform/devices/.../config_write
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file allows user to write a value to the register
+		address given as argument.The values are entered in the
+		form of <register_address> <value>.The reason for this
+		feature of dcc is that for accessing certain registers
+		it is necessary to set some bits of soe other register.
+		That is achievable by giving DCC this privelege.
+		Example:
+		echo 0x80000000 0xFF > /sys/bus/platform/devices/.../config_write
+
+What:           /sys/bus/platform/devices/.../config_reset
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to reset the configuration of
+		a dcc driver to the default configuration.
+		Example:
+		echo  1 > /sys/bus/platform/devices/.../config_reset
+
+What:           /sys/bus/platform/devices/.../loop
+Date:		March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to enter the loop count as dcc
+		driver gives the option to loop multiple times on
+		the same register and store the values for each
+		loop.This is done to capture the changing values
+		of a register with time which comes handy for
+		debugging purposes.
+		Example:
+		echo 10 > /sys/bus/platform/devices/10a2000.dcc/loop
+		(Setting the loop count to 10)
+		echo  0x80000010 10 > /sys/bus/platform/devices/.../config
+                (Read 10 words starting from address 0x80000010O)
+		echo 1 > /sys/bus/platform/devices/.../loop
+		(Terminate the loop by writing a count of 1 to the loop sysfs node)
+
+What:           /sys/bus/platform/devices/.../rd_mod_wr
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to read the value of the register
+		and then write the value given as an argument to the
+		register address in config.The address argument should
+		be given of the form <mask> <value>.For debugging
+		purposes sometimes we need to first read from a register
+		and then set some values to the register.
+		Example:
+		echo 0x80000000 > /sys/bus/platform/devices/.../config
+		(Set the address in config file)
+		echo 0xF 0xA > /sys/bus/platform/devices/.../rd_mod_wr
+		(Provide the mask and the value to write)
+
+What:           /sys/bus/platform/devices/.../ready
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to check the status of the dcc
+		hardware if it's ready to take the inputs.
+		Example:
+		cat /sys/bus/platform/devices/.../ready
+
+What:		/sys/bus/platform/devices/.../curr_list
+Date:		February 2021
+Contact:	Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This attribute is used to enter the linklist to be
+		used while appending addresses.The range of values
+		for this can be from 0 to 3.This feature is given in
+		order to use certain linkedlist for certain debugging
+		purposes.
+		Example:
+		echo 0 > /sys/bus/platform/devices/10a2000.dcc/curr_list
+
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V3 4/5] MAINTAINERS: Add the entry for DCC(Data Capture and Compare) driver support

[Souradeep Chowdhury]

Added the entries for all the files added as a part of driver support for
DCC(Data Capture and Compare).

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85c..fb28218 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4969,6 +4969,14 @@ F:	include/linux/tfrc.h
 F:	include/uapi/linux/dccp.h
 F:	net/dccp/

+QTI DCC DRIVER
+M:	Souradeep Chowdhury <schowdhu@codeaurora.org>
+L:	linux-arm-msm@vger.kernel.org
+S:	Maintained
+F:	Documentation/ABI/testing/sysfs-driver-dcc
+F:	Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
+F:	drivers/soc/qcom/dcc.c
+
 DECnet NETWORK LAYER
 L:	linux-decnet-user@lists.sourceforge.net
 S:	Orphan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH V3 5/5] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node

[Souradeep Chowdhury]

Add the DCC(Data Capture and Compare) device tree node entry along with
the addresses for register regions.

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index e5bb17b..ba6acf4 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -654,6 +654,13 @@
 			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		dcc@10a2000 {
+			compatible = "qcom,sm8150-dcc", "qcom,dcc";
+			reg = <0x0 0x010a2000 0x0 0x1000>,
+			      <0x0 0x010ad000 0x0 0x3000>;
+			reg-names = "dcc", "dcc-ram";
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[Resend PATCH V3 0/5] Add driver support for Data Capture and Compare Engine(DCC) for SM8150

[Souradeep Chowdhury]

DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.In case of a system
crash or manual software triggers by the user the DCC hardware stores the value at the register
addresses which can be used for debugging purposes.The DCC driver provides the user with sysfs
interface to configure the register addresses.The options that the DCC hardware provides include
reading from registers,writing to registers,first reading and then writing to registers and looping
through the values of the same register.

In certain cases a register write needs to be executed for accessing the rest of the registers,
also the user might want to record the changing values of a register with time for which he has the
option to use the loop feature.

The options mentioned above are exposed to the user by sysfs files once the driver is probed.The
details and usage of this sysfs files are documented in Documentation/ABI/testing/sysfs-driver-dcc.

As an example let us consider a couple of debug scenarios where DCC has been proved to be effective
for debugging purposes:-

i)TimeStamp Related Issue

On SC7180, there was a coresight timestamp issue where it would occasionally be all 0 instead of proper
timestamp values.

Proper timestamp:
Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e

Zero timestamp:
Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2

Now this is a non-fatal issue and doesn't need a system reset, but still needs
to be rootcaused and fixed for those who do care about coresight etm traces.
Since this is a timestamp issue, we would be looking for any timestamp related
clocks and such.

o we get all the clk register details from IP documentation and configure it
via DCC config syfs node. Before that we set the current linked list.

/* Set the current linked list */
echo 3 > /sys/bus/platform/devices/10a2000.dcc/curr_list

/* Program the linked list with the addresses */
echo 0x10c004 > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c008 > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c00c > /sys/bus/platform/devices/10a2000.dcc/config
echo 0x10c010 > /sys/bus/platform/devices/10a2000.dcc/config
..... and so on for other timestamp related clk registers

/* Other way of specifying is in "addr len" pair, in below case it
specifies to capture 4 words starting 0x10C004 */

echo 0x10C004 4 > /sys/bus/platform/devices/10a2000.dcc/config

/* Enable DCC */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/enable

/* Run the timestamp test for working case */

/* Send SW trigger */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger

/* Read SRAM */
cat /dev/dcc_sram > dcc_sram1.bin

/* Run the timestamp test for non-working case */

/* Send SW trigger */
echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger

/* Read SRAM */
cat /dev/dcc_sram > dcc_sram2.bin

Get the parser from [1] and checkout the latest branch.

/* Parse the SRAM bin */
python dcc_parser.py -s dcc_sram1.bin --v2 -o output/
python dcc_parser.py -s dcc_sram2.bin --v2 -o output/

Sample parsed output of dcc_sram1.bin:

<hwioDump version="1">
        <timestamp>03/14/21</timestamp>
	        <generator>Linux DCC Parser</generator>
		        <chip name="None" version="None">
				<register address="0x0010c004" value="0x80000000" />
				<register address="0x0010c008" value="0x00000008" />
				<register address="0x0010c00c" value="0x80004220" />
				<register address="0x0010c010" value="0x80000000" />
			</chip>
	<next_ll_offset>next_ll_offset : 0x1c </next_ll_offset>
</hwioDump>

ii)NOC register errors

A particular class of registers called NOC which are functional registers was reporting
errors while logging the values.To trace these errors the DCC has been used effectively.
The steps followed were similar to the ones mentioned above.
In addition to NOC registers a few other dependent registers were configured in DCC to
monitor it's values during a crash. A look at the dependent register values revealed that
the crash was happening due to a secured access to one of these dependent registers.
All these debugging activity and finding the root cause was achieved using DCC.

DCC parser is available at the following open source location

https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser

Changes in v3:
* Collect the review tag
* Fix the dtsi issue reported in v2

Souradeep Chowdhury (5):
  dt-bindings: Added the yaml bindings for DCC
  soc: qcom: dcc:Add driver support for Data Capture and Compare
    unit(DCC)
  DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver
  MAINTAINERS:Add the entry for DCC(Data Capture and Compare) driver
    support
  arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support
    node

 Documentation/ABI/testing/sysfs-driver-dcc         |  114 ++
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      |   49 +
 MAINTAINERS                                        |    8 +
 arch/arm64/boot/dts/qcom/sm8150.dtsi               |    7 +
 drivers/soc/qcom/Kconfig                           |    8 +
 drivers/soc/qcom/Makefile                          |    1 +
 drivers/soc/qcom/dcc.c                             | 1549 ++++++++++++++++++++
 7 files changed, 1736 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
 create mode 100644 drivers/soc/qcom/dcc.c

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[Resend PATCH V3 1/5] dt-bindings: Added the yaml bindings for DCC

[Souradeep Chowdhury]

Documentation for Data Capture and Compare(DCC) device tree bindings
in yaml format.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
new file mode 100644
index 0000000..c6e0a9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Data Capture and Compare
+
+maintainers:
+  - Souradeep Chowdhury <schowdhu@codeaurora.org>
+
+description: |
+    DCC (Data Capture and Compare) is a DMA engine which is used to save
+    configuration data or system memory contents during catastrophic failure
+    or SW trigger.DCC is used to capture and store data for debugging purpose
+
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,sm8150-dcc
+      - const: qcom,dcc
+
+  reg:
+    items:
+      - description: DCC base register region
+      - description: DCC RAM base register region
+
+  reg-names:
+    items:
+      - const: dcc
+      - const: dcc-ram
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+additionalProperties: false
+
+examples:
+  - |
+    dcc@10a2000{
+                compatible = "qcom,sm8150-dcc","qcom,dcc";
+                reg = <0x010a2000  0x1000>,
+                      <0x010ad000  0x2000>;
+                reg-names = "dcc", "dcc-ram";
+    };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[Resend PATCH V3 2/5] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)

[Souradeep Chowdhury]

The DCC is a DMA Engine designed to capture and store data
during system crash or software triggers.The DCC operates
based on user inputs via the sysfs interface.The user gives
addresses as inputs and these addresses are stored in the
form of linkedlists.In case of a system crash or a manual
software trigger by the user through the sysfs interface,
the dcc captures and stores the values at these addresses.
This patch contains the driver which has all the methods
pertaining to the sysfs interface, auxiliary functions to
support all the four fundamental operations of dcc namely
read, write, first read then write and loop.The probe method
here instantiates all the resources necessary for dcc to
operate mainly the dedicated dcc sram where it stores the
values.The DCC driver can be used for debugging purposes
without going for a reboot since it can perform manual
triggers.

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 drivers/soc/qcom/Kconfig  |    8 +
 drivers/soc/qcom/Makefile |    1 +
 drivers/soc/qcom/dcc.c    | 1549 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1558 insertions(+)
 create mode 100644 drivers/soc/qcom/dcc.c

diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 79b568f..8819e0b 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -69,6 +69,14 @@ config QCOM_LLCC
 	  SDM845. This provides interfaces to clients that use the LLCC.
 	  Say yes here to enable LLCC slice driver.

+config QCOM_DCC
+	tristate "Qualcomm Technologies, Inc. Data Capture and Compare engine driver"
+	depends on ARCH_QCOM || COMPILE_TEST
+	help
+	  This option enables driver for Data Capture and Compare engine. DCC
+	  driver provides interface to configure DCC block and read back
+	  captured data from DCC's internal SRAM.
+
 config QCOM_KRYO_L2_ACCESSORS
 	bool
 	depends on ARCH_QCOM && ARM64 || COMPILE_TEST
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index ad675a6..1b00870 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
 obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
 obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
+obj-$(CONFIG_QCOM_DCC) += dcc.o
diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c
new file mode 100644
index 0000000..a55d8ca7
--- /dev/null
+++ b/drivers/soc/qcom/dcc.c
@@ -0,0 +1,1549 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/cdev.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+
+#define TIMEOUT_US		100
+
+#define dcc_writel(drvdata, val, off)					\
+	writel((val), drvdata->base + dcc_offset_conv(drvdata, off))
+#define dcc_readl(drvdata, off)						\
+	readl(drvdata->base + dcc_offset_conv(drvdata, off))
+
+#define dcc_sram_readl(drvdata, off)					\
+	readl(drvdata->ram_base + off)
+
+#define DCC_SRAM_NODE "dcc_sram"
+
+/* DCC registers */
+#define DCC_HW_INFO			0x04
+#define DCC_LL_NUM_INFO			0x10
+#define DCC_STATUS			0x1C
+#define DCC_LL_LOCK(m)			(0x34 + 0x80 * m)
+#define DCC_LL_CFG(m)			(0x38 + 0x80 * m)
+#define DCC_LL_BASE(m)			(0x3c + 0x80 * m)
+#define DCC_FD_BASE(m)			(0x40 + 0x80 * m)
+#define DCC_LL_TIMEOUT(m)		(0x44 + 0x80 * m)
+#define DCC_LL_INT_ENABLE(m)		(0x4C + 0x80 * m)
+#define DCC_LL_INT_STATUS(m)		(0x50 + 0x80 * m)
+#define DCC_LL_SW_TRIGGER(m)		(0x60 + 0x80 * m)
+#define DCC_LL_BUS_ACCESS_STATUS(m)	(0x64 + 0x80 * m)
+
+#define DCC_MAP_LEVEL1			0x18
+#define DCC_MAP_LEVEL2			0x34
+#define DCC_MAP_LEVEL3			0x4C
+
+#define DCC_MAP_OFFSET1			0x10
+#define DCC_MAP_OFFSET2			0x18
+#define DCC_MAP_OFFSET3			0x1C
+#define DCC_MAP_OFFSET4			0x8
+
+#define DCC_FIX_LOOP_OFFSET		16
+#define DCC_VER_INFO_BIT		9
+
+#define DCC_READ			0
+#define DCC_WRITE			1
+#define DCC_LOOP			2
+#define DCC_READ_WRITE			3
+
+#define MAX_DCC_OFFSET			GENMASK(9, 2)
+#define MAX_DCC_LEN			GENMASK(6, 0)
+#define MAX_LOOP_CNT			GENMASK(7, 0)
+
+#define DCC_ADDR_DESCRIPTOR		0x00
+#define DCC_LOOP_DESCRIPTOR		BIT(30)
+#define DCC_RD_MOD_WR_DESCRIPTOR	BIT(31)
+#define DCC_LINK_DESCRIPTOR		GENMASK(31, 30)
+
+#define DCC_READ_IND			0x00
+#define DCC_WRITE_IND			(BIT(28))
+
+#define DCC_AHB_IND			0x00
+#define DCC_APB_IND			BIT(29)
+
+#define DCC_MAX_LINK_LIST		8
+#define DCC_INVALID_LINK_LIST		GENMASK(7, 0)
+
+#define DCC_VER_MASK1			GENMASK(6, 0)
+#define DCC_VER_MASK2			GENMASK(5, 0)
+
+#define DCC_RD_MOD_WR_ADDR              0xC105E
+
+struct qcom_dcc_config {
+	const int dcc_ram_offset;
+};
+
+enum dcc_descriptor_type {
+	DCC_ADDR_TYPE,
+	DCC_LOOP_TYPE,
+	DCC_READ_WRITE_TYPE,
+	DCC_WRITE_TYPE
+};
+
+enum dcc_mem_map_ver {
+	DCC_MEM_MAP_VER1 = 1,
+	DCC_MEM_MAP_VER2 = 2,
+	DCC_MEM_MAP_VER3 = 3
+};
+
+struct dcc_config_entry {
+	u32				base;
+	u32				offset;
+	u32				len;
+	u32				index;
+	u32				loop_cnt;
+	u32				write_val;
+	u32				mask;
+	bool				apb_bus;
+	enum dcc_descriptor_type	desc_type;
+	struct list_head		list;
+};
+
+struct dcc_drvdata {
+	void __iomem		*base;
+	u32			reg_size;
+	struct device		*dev;
+	struct mutex		mutex;
+	void __iomem		*ram_base;
+	u32			ram_size;
+	u32			ram_offset;
+	enum dcc_mem_map_ver	mem_map_ver;
+	u32			ram_cfg;
+	u32			ram_start;
+	bool			*enable;
+	bool			*configured;
+	bool			interrupt_disable;
+	char			*sram_node;
+	struct cdev		sram_dev;
+	struct class		*sram_class;
+	struct list_head	*cfg_head;
+	u32			*nr_config;
+	u32			nr_link_list;
+	u8			curr_list;
+	u8			loopoff;
+};
+
+struct dcc_cfg_attr {
+	u32	addr;
+	u32	prev_addr;
+	u32	prev_off;
+	u32	link;
+	u32	sram_offset;
+};
+
+struct dcc_cfg_loop_attr {
+	u32	loop;
+	bool	loop_start;
+	u32	loop_cnt;
+	u32	loop_len;
+	u32	loop_off;
+};
+
+static size_t dcc_offset_conv(struct dcc_drvdata *drvdata, size_t off)
+{
+	if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL3)
+			return (off - DCC_MAP_OFFSET3);
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET2);
+		else if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL1)
+			return (off - DCC_MAP_OFFSET1);
+	} else if (drvdata->mem_map_ver == DCC_MEM_MAP_VER2) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET4);
+	}
+	return off;
+}
+
+static int dcc_sram_writel(struct dcc_drvdata *drvdata,
+					u32 val, u32 off)
+{
+	if (unlikely(off > (drvdata->ram_size - 4)))
+		return -EINVAL;
+
+	writel((val), drvdata->ram_base + off);
+
+	return 0;
+}
+
+static bool dcc_ready(struct dcc_drvdata *drvdata)
+{
+	u32 val;
+
+	/* poll until DCC ready */
+	if (!readl_poll_timeout((drvdata->base + DCC_STATUS), val,
+				(FIELD_GET(GENMASK(1, 0), val) == 0), 1, TIMEOUT_US))
+		return true;
+
+	return false;
+}
+
+static int dcc_read_status(struct dcc_drvdata *drvdata)
+{
+	int curr_list;
+	u32 bus_status;
+	u32 ll_cfg = 0;
+	u32 tmp_ll_cfg = 0;
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+
+		bus_status = dcc_readl(drvdata, DCC_LL_BUS_ACCESS_STATUS(curr_list));
+
+		if (bus_status) {
+			dev_err(drvdata->dev,
+				"Read access error for list %d err: 0x%x.\n",
+				curr_list, bus_status);
+
+			ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
+			tmp_ll_cfg = ll_cfg & ~BIT(9);
+			dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
+			dcc_writel(drvdata, 0x3,
+				DCC_LL_BUS_ACCESS_STATUS(curr_list));
+			dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
+			return -ENODATA;
+		}
+	}
+
+	return 0;
+}
+
+static int dcc_sw_trigger(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+	int curr_list;
+	u32 ll_cfg = 0;
+	u32 tmp_ll_cfg = 0;
+
+	mutex_lock(&drvdata->mutex);
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+		ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
+		tmp_ll_cfg = ll_cfg & ~BIT(9);
+		dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
+		dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
+		dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
+	}
+
+	if (!dcc_ready(drvdata)) {
+		dev_err(drvdata->dev,
+			"DCC is busy after receiving sw tigger.\n");
+		ret = -EBUSY;
+		goto err;
+	}
+
+	ret = dcc_read_status(drvdata);
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static void _dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg)
+{
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	cfg->prev_off = 0;
+	cfg->prev_addr = cfg->addr;
+}
+
+static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata,
+				  struct dcc_config_entry *entry,
+				  struct dcc_cfg_attr *cfg)
+{
+	int ret;
+
+	if (cfg->link) {
+		/*
+		 * write new offset = 1 to continue
+		 * processing the list
+		 */
+
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		_dcc_ll_cfg_reset_link(cfg);
+	}
+
+	cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR;
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	ret = dcc_sram_writel(drvdata, entry->mask, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	cfg->addr = 0;
+	return ret;
+}
+
+static int _dcc_ll_cfg_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry,
+			    struct dcc_cfg_attr *cfg,
+			    struct dcc_cfg_loop_attr *cfg_loop,
+			    u32 *total_len)
+{
+
+	int ret;
+
+	/* Check if we need to write link of prev entry */
+	if (cfg->link) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+	}
+
+	if (cfg_loop->loop_start) {
+		cfg_loop->loop = (cfg->sram_offset - cfg_loop->loop_off) / 4;
+		cfg_loop->loop |= (cfg_loop->loop_cnt << drvdata->loopoff) &
+		GENMASK(27, drvdata->loopoff);
+		cfg_loop->loop |= DCC_LOOP_DESCRIPTOR;
+		*total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt;
+
+		ret = dcc_sram_writel(drvdata, cfg_loop->loop, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+
+		cfg_loop->loop_start = false;
+		cfg_loop->loop_len = 0;
+		cfg_loop->loop_off = 0;
+	} else {
+		cfg_loop->loop_start = true;
+		cfg_loop->loop_cnt = entry->loop_cnt - 1;
+		cfg_loop->loop_len = *total_len;
+		cfg_loop->loop_off = cfg->sram_offset;
+	}
+
+	/* Reset link and prev_off */
+
+	_dcc_ll_cfg_reset_link(cfg);
+
+	return ret;
+}
+
+static int _dcc_ll_cfg_write(struct dcc_drvdata *drvdata,
+			     struct dcc_config_entry *entry,
+			     struct dcc_cfg_attr *cfg,
+			     u32 *total_len)
+{
+	u32 off;
+	int ret;
+
+	if (cfg->link) {
+		/*
+		 * write new offset = 1 to continue
+		 * processing the list
+		 */
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		cfg->addr = 0x00;
+		cfg->prev_off = 0;
+		cfg->prev_addr = cfg->addr;
+	}
+
+	off = entry->offset/4;
+	/* write new offset-length pair to correct position */
+	cfg->link |= ((off & GENMASK(7, 0)) | BIT(15) | ((entry->len << 8) & GENMASK(14, 8)));
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	/* Address type */
+	cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND;
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	return ret;
+}
+
+static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
+			       struct dcc_config_entry *entry,
+			       struct dcc_cfg_attr *cfg,
+			       u32 *pos, u32 *total_len)
+{
+	int ret;
+	u32 off;
+
+	cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
+
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND;
+
+	off = entry->offset/4;
+
+	*total_len += entry->len * 4;
+
+	if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) {
+		/* Check if we need to write prev link entry */
+		if (cfg->link) {
+			ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+			if (ret)
+				return ret;
+			cfg->sram_offset += 4;
+		}
+		dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset);
+
+		/* Write address */
+		ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+
+		/* Reset link and prev_off */
+		cfg->link = 0;
+		cfg->prev_off = 0;
+	}
+
+	if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
+		dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n",
+		entry->base, entry->offset);
+		ret = -EINVAL;
+		return ret;
+	}
+
+	if (cfg->link) {
+		/*
+		 * link already has one offset-length so new
+		 * offset-length needs to be placed at
+		 * bits [29:15]
+		 */
+		*pos = 15;
+
+		/* Clear bits [31:16] */
+		cfg->link &= GENMASK(14, 0);
+	} else {
+		/*
+		 * link is empty, so new offset-length needs
+		 * to be placed at bits [15:0]
+		 */
+		*pos = 0;
+		cfg->link = 1 << 15;
+	}
+
+	/* write new offset-length pair to correct position */
+	cfg->link |= (((off-cfg->prev_off) & GENMASK(7, 0)) |
+		     ((entry->len << 8) & GENMASK(14, 8))) << *pos;
+
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	if (*pos) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		cfg->link = 0;
+	}
+
+	cfg->prev_off  = off + entry->len - 1;
+	cfg->prev_addr = cfg->addr;
+	return ret;
+}
+
+static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list)
+{
+	int ret = 0;
+	u32 total_len, pos;
+	struct dcc_config_entry *entry;
+	struct dcc_cfg_attr cfg;
+	struct dcc_cfg_loop_attr cfg_loop;
+
+	memset(&cfg, 0, sizeof(cfg));
+	memset(&cfg_loop, 0, sizeof(cfg_loop));
+	cfg.sram_offset = drvdata->ram_cfg * 4;
+	total_len = 0;
+
+	list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+			ret = _dcc_ll_cfg_read_write(drvdata, entry, &cfg);
+			if (ret)
+				goto overstep;
+			break;
+
+		case DCC_LOOP_TYPE:
+			ret = _dcc_ll_cfg_loop(drvdata, entry, &cfg, &cfg_loop, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+
+		case DCC_WRITE_TYPE:
+			ret = _dcc_ll_cfg_write(drvdata, entry, &cfg, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+
+		default:
+			ret = _dcc_ll_cfg_default(drvdata, entry, &cfg, &pos, &total_len);
+			if (ret)
+				goto overstep;
+			break;
+		}
+	}
+
+	if (cfg.link) {
+		ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
+		if (ret)
+			goto overstep;
+		cfg.sram_offset += 4;
+	}
+
+	if (cfg_loop.loop_start) {
+		dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* Handling special case of list ending with a rd_mod_wr */
+	if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) {
+		cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0);
+		cfg.addr |= DCC_ADDR_DESCRIPTOR;
+		ret = dcc_sram_writel(drvdata, cfg.addr, cfg.sram_offset);
+		if (ret)
+			goto overstep;
+		cfg.sram_offset += 4;
+	}
+
+	/* Setting zero to indicate end of the list */
+	cfg.link = DCC_LINK_DESCRIPTOR;
+	ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
+	if (ret)
+		goto overstep;
+	cfg.sram_offset += 4;
+
+	/* Update ram_cfg and check if the data will overstep */
+
+	drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4;
+
+	if (cfg.sram_offset + total_len > drvdata->ram_size) {
+		cfg.sram_offset += total_len;
+		goto overstep;
+	}
+
+	drvdata->ram_start = cfg.sram_offset/4;
+	return 0;
+overstep:
+	ret = -EINVAL;
+	memset_io(drvdata->ram_base, 0, drvdata->ram_size);
+	dev_err(drvdata->dev, "DCC SRAM oversteps, 0x%x (0x%x)\n",
+	cfg.sram_offset, drvdata->ram_size);
+
+err:
+	return ret;
+}
+
+static int dcc_valid_list(struct dcc_drvdata *drvdata, int curr_list)
+{
+	u32 lock_reg;
+
+	if (list_empty(&drvdata->cfg_head[curr_list]))
+		return -EINVAL;
+
+	if (drvdata->enable[curr_list]) {
+		dev_err(drvdata->dev, "List %d is already enabled\n",
+				curr_list);
+		return -EINVAL;
+	}
+
+	lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(curr_list));
+	if (lock_reg & 0x1) {
+		dev_err(drvdata->dev, "List %d is already locked\n",
+				curr_list);
+		return -EINVAL;
+	}
+
+	dev_err(drvdata->dev, "DCC list passed %d\n", curr_list);
+	return 0;
+}
+
+static bool is_dcc_enabled(struct dcc_drvdata *drvdata)
+{
+	bool dcc_enable = false;
+	int list;
+
+	for (list = 0; list < DCC_MAX_LINK_LIST; list++) {
+		if (drvdata->enable[list]) {
+			dcc_enable = true;
+			break;
+		}
+	}
+
+	return dcc_enable;
+}
+
+static int dcc_enable(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+	int list;
+	u32 ram_cfg_base;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (!is_dcc_enabled(drvdata)) {
+		memset_io(drvdata->ram_base,
+			0xDE, drvdata->ram_size);
+	}
+
+	for (list = 0; list < drvdata->nr_link_list; list++) {
+
+		if (dcc_valid_list(drvdata, list))
+			continue;
+
+		/* 1. Take ownership of the list */
+		dcc_writel(drvdata, BIT(0), DCC_LL_LOCK(list));
+
+		/* 2. Program linked-list in the SRAM */
+		ram_cfg_base = drvdata->ram_cfg;
+		ret = __dcc_ll_cfg(drvdata, list);
+		if (ret) {
+			dcc_writel(drvdata, 0, DCC_LL_LOCK(list));
+			dev_info(drvdata->dev, "DCC ram programming failed\n");
+			goto err;
+		}
+
+		/* 3. program DCC_RAM_CFG reg */
+		dcc_writel(drvdata, ram_cfg_base +
+			drvdata->ram_offset/4, DCC_LL_BASE(list));
+		dcc_writel(drvdata, drvdata->ram_start +
+			drvdata->ram_offset/4, DCC_FD_BASE(list));
+		dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list));
+
+		/* 4. Clears interrupt status register */
+		dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list));
+		dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)),
+					DCC_LL_INT_STATUS(list));
+
+		dev_info(drvdata->dev, "All values written to enable.\n");
+		/* Make sure all config is written in sram */
+		mb();
+
+		drvdata->enable[list] = true;
+
+		/* 5. Configure trigger */
+		dcc_writel(drvdata, BIT(9), DCC_LL_CFG(list));
+	}
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static void dcc_disable(struct dcc_drvdata *drvdata)
+{
+	int curr_list;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (!dcc_ready(drvdata))
+		dev_err(drvdata->dev, "DCC is not ready Disabling DCC...\n");
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+		dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list));
+		dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list));
+		dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list));
+		dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
+		drvdata->enable[curr_list] = false;
+	}
+	memset_io(drvdata->ram_base, 0, drvdata->ram_size);
+	drvdata->ram_cfg = 0;
+	drvdata->ram_start = 0;
+	mutex_unlock(&drvdata->mutex);
+}
+
+static ssize_t curr_list_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list == DCC_INVALID_LINK_LIST) {
+		dev_err(dev, "curr_list is not set.\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = scnprintf(buf, PAGE_SIZE, "%d\n",	drvdata->curr_list);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t curr_list_store(struct device *dev,
+						struct device_attribute *attr,
+						const char *buf, size_t size)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	unsigned long val;
+	u32 lock_reg;
+	bool dcc_enable = false;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val >= drvdata->nr_link_list)
+		return -EINVAL;
+
+	mutex_lock(&drvdata->mutex);
+
+	dcc_enable = is_dcc_enabled(drvdata);
+	if (drvdata->curr_list != DCC_INVALID_LINK_LIST	&& dcc_enable) {
+		dev_err(drvdata->dev, "DCC is enabled, please disable it first.\n");
+		mutex_unlock(&drvdata->mutex);
+		return -EINVAL;
+	}
+
+	lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
+	if (lock_reg & 0x1) {
+		dev_err(drvdata->dev, "DCC linked list is already configured\n");
+		mutex_unlock(&drvdata->mutex);
+		return -EINVAL;
+	}
+	drvdata->curr_list = val;
+	mutex_unlock(&drvdata->mutex);
+
+	return size;
+}
+
+static DEVICE_ATTR_RW(curr_list);
+
+
+static ssize_t trigger_store(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	int ret = 0;
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+	if (val != 1)
+		return -EINVAL;
+
+	ret = dcc_sw_trigger(drvdata);
+	if (!ret)
+		ret = size;
+
+	return ret;
+}
+static DEVICE_ATTR_WO(trigger);
+
+static ssize_t enable_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	bool dcc_enable = false;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	dcc_enable = is_dcc_enabled(drvdata);
+
+	ret = scnprintf(buf, PAGE_SIZE, "%u\n",
+				(unsigned int)dcc_enable);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t enable_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	int ret = 0;
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val)
+		ret = dcc_enable(drvdata);
+	else
+		dcc_disable(drvdata);
+
+	if (!ret)
+		ret = size;
+
+	return ret;
+
+}
+
+static DEVICE_ATTR_RW(enable);
+
+static ssize_t config_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	struct dcc_config_entry *entry;
+	char local_buf[64];
+	int len = 0, count = 0;
+
+	buf[0] = '\0';
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		count = -EINVAL;
+		goto err;
+	}
+
+	list_for_each_entry(entry,
+	&drvdata->cfg_head[drvdata->curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+			len = snprintf(local_buf, 64, "Index: 0x%x, mask: 0x%x, val: 0x%x\n",
+				entry->index, entry->mask, entry->write_val);
+			break;
+		case DCC_LOOP_TYPE:
+			len = snprintf(local_buf, 64, "Index: 0x%x, Loop: %d\n",
+				entry->index, entry->loop_cnt);
+			break;
+		case DCC_WRITE_TYPE:
+			len = snprintf(local_buf, 64,
+				"Write Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
+				entry->index, entry->base, entry->offset, entry->len,
+				entry->apb_bus);
+			break;
+		default:
+			len = snprintf(local_buf, 64,
+				"Read Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
+				entry->index, entry->base, entry->offset,
+				entry->len, entry->apb_bus);
+		}
+
+		if ((count + len) > PAGE_SIZE) {
+			dev_err(dev, "DCC: Couldn't write complete config\n");
+			break;
+		}
+		strlcat(buf, local_buf, PAGE_SIZE);
+		count += len;
+	}
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return count;
+}
+
+static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
+				unsigned int len, int apb_bus)
+{
+	int ret;
+	struct dcc_config_entry *entry, *pentry;
+	unsigned int base, offset;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(drvdata->dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (!len || len > (drvdata->ram_size / 8)) {
+		dev_err(drvdata->dev, "DCC: Invalid length\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	base = addr & GENMASK(31, 4);
+
+	if (!list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
+		pentry = list_last_entry(&drvdata->cfg_head[drvdata->curr_list],
+			struct dcc_config_entry, list);
+
+		if (pentry->desc_type == DCC_ADDR_TYPE &&
+				addr >= (pentry->base + pentry->offset) &&
+				addr <= (pentry->base +
+					pentry->offset + MAX_DCC_OFFSET)) {
+
+			/* Re-use base address from last entry */
+			base = pentry->base;
+
+			if ((pentry->len * 4 + pentry->base + pentry->offset)
+					== addr) {
+				len += pentry->len;
+
+				if (len > MAX_DCC_LEN)
+					pentry->len = MAX_DCC_LEN;
+				else
+					pentry->len = len;
+
+				addr = pentry->base + pentry->offset +
+					pentry->len * 4;
+				len -= pentry->len;
+			}
+		}
+	}
+
+	offset = addr - base;
+
+	while (len) {
+		entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+		if (!entry) {
+			ret = -ENOMEM;
+			goto err;
+		}
+
+		entry->base = base;
+		entry->offset = offset;
+		entry->len = min_t(u32, len, MAX_DCC_LEN);
+		entry->index = drvdata->nr_config[drvdata->curr_list]++;
+		entry->desc_type = DCC_ADDR_TYPE;
+		entry->apb_bus = apb_bus;
+		INIT_LIST_HEAD(&entry->list);
+		list_add_tail(&entry->list,
+			&drvdata->cfg_head[drvdata->curr_list]);
+
+		len -= entry->len;
+		offset += MAX_DCC_LEN * 4;
+	}
+
+	mutex_unlock(&drvdata->mutex);
+	return 0;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t config_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	int ret, len, apb_bus;
+	unsigned int base;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	int nval;
+
+	nval = sscanf(buf, "%x %i %d", &base, &len, &apb_bus);
+	if (nval <= 0 || nval > 3)
+		return -EINVAL;
+
+	if (nval == 1) {
+		len = 1;
+		apb_bus = 0;
+	} else if (nval == 2) {
+		apb_bus = 0;
+	} else {
+		apb_bus = 1;
+	}
+
+	ret = dcc_config_add(drvdata, base, len, apb_bus);
+	if (ret)
+		return ret;
+
+	return size;
+
+}
+
+static DEVICE_ATTR_RW(config);
+
+static void dcc_config_reset(struct dcc_drvdata *drvdata)
+{
+	struct dcc_config_entry *entry, *temp;
+	int curr_list;
+
+	mutex_lock(&drvdata->mutex);
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		list_for_each_entry_safe(entry, temp,
+			&drvdata->cfg_head[curr_list], list) {
+			list_del(&entry->list);
+			devm_kfree(drvdata->dev, entry);
+			drvdata->nr_config[curr_list]--;
+		}
+	}
+	drvdata->ram_start = 0;
+	drvdata->ram_cfg = 0;
+	mutex_unlock(&drvdata->mutex);
+}
+
+
+static ssize_t config_reset_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val)
+		dcc_config_reset(drvdata);
+
+	return size;
+}
+
+static DEVICE_ATTR_WO(config_reset);
+
+static ssize_t ready_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (!drvdata->enable[drvdata->curr_list]) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = scnprintf(buf, PAGE_SIZE, "%u\n",
+			(unsigned int)FIELD_GET(BIT(1), dcc_readl(drvdata, DCC_STATUS)));
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_RO(ready);
+
+static ssize_t interrupt_disable_show(struct device *dev,
+						struct device_attribute *attr,
+						char *buf)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n",
+				(unsigned int)drvdata->interrupt_disable);
+}
+
+static ssize_t interrupt_disable_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	mutex_lock(&drvdata->mutex);
+	drvdata->interrupt_disable = (val ? 1:0);
+	mutex_unlock(&drvdata->mutex);
+	return size;
+}
+
+static DEVICE_ATTR_RW(interrupt_disable);
+
+static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt)
+{
+	struct dcc_config_entry *entry;
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry)
+		return -ENOMEM;
+
+	entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT);
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	entry->desc_type = DCC_LOOP_TYPE;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+
+	return 0;
+}
+
+static ssize_t loop_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	int ret;
+	unsigned long loop_cnt;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	if (kstrtoul(buf, 16, &loop_cnt)) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = dcc_add_loop(drvdata, loop_cnt);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&drvdata->mutex);
+	return size;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_WO(loop);
+
+static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask,
+				unsigned int val)
+{
+	int ret = 0;
+	struct dcc_config_entry *entry;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(drvdata->dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
+		dev_err(drvdata->dev, "DCC: No read address programmed\n");
+		ret = -EPERM;
+		goto err;
+	}
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	entry->desc_type = DCC_READ_WRITE_TYPE;
+	entry->mask = mask;
+	entry->write_val = val;
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t rd_mod_wr_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	int ret;
+	int nval;
+	unsigned int mask, val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	nval = sscanf(buf, "%x %x", &mask, &val);
+
+	if (nval <= 1 || nval > 2)
+		return -EINVAL;
+
+	ret = dcc_rd_mod_wr_add(drvdata, mask, val);
+	if (ret)
+		return ret;
+
+	return size;
+
+}
+
+static DEVICE_ATTR_WO(rd_mod_wr);
+
+static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr,
+				unsigned int write_val, int apb_bus)
+{
+	struct dcc_config_entry *entry;
+
+	entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry)
+		return -ENOMEM;
+
+	entry->desc_type = DCC_WRITE_TYPE;
+	entry->base = addr & GENMASK(31, 4);
+	entry->offset = addr - entry->base;
+	entry->write_val = write_val;
+	entry->index = drvdata->nr_config[drvdata->curr_list]++;
+	entry->len = 1;
+	entry->apb_bus = apb_bus;
+	INIT_LIST_HEAD(&entry->list);
+	list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
+
+	return 0;
+}
+
+static ssize_t config_write_store(struct device *dev,
+						struct device_attribute *attr,
+						const char *buf, size_t size)
+{
+	int ret;
+	int nval;
+	unsigned int addr, write_val;
+	int apb_bus = 0;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	nval = sscanf(buf, "%x %x %d", &addr, &write_val, &apb_bus);
+
+	if (nval <= 1 || nval > 3) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (nval == 3 && apb_bus != 0)
+		apb_bus = 1;
+
+	ret = dcc_add_write(drvdata, addr, write_val, apb_bus);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&drvdata->mutex);
+	return size;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_WO(config_write);
+
+static const struct device_attribute *dcc_attrs[] = {
+	&dev_attr_trigger,
+	&dev_attr_enable,
+	&dev_attr_config,
+	&dev_attr_config_reset,
+	&dev_attr_ready,
+	&dev_attr_interrupt_disable,
+	&dev_attr_loop,
+	&dev_attr_rd_mod_wr,
+	&dev_attr_curr_list,
+	&dev_attr_config_write,
+	NULL,
+};
+
+static int dcc_create_files(struct device *dev,
+					const struct device_attribute **attrs)
+{
+	int ret = 0, i;
+
+	for (i = 0; attrs[i] != NULL; i++) {
+		ret = device_create_file(dev, attrs[i]);
+		if (ret) {
+			dev_err(dev, "DCC: Couldn't create sysfs attribute: %s\n",
+				attrs[i]->attr.name);
+			break;
+		}
+	}
+	return ret;
+}
+
+static int dcc_sram_open(struct inode *inode, struct file *file)
+{
+	struct dcc_drvdata *drvdata = container_of(inode->i_cdev,
+		struct dcc_drvdata,
+		sram_dev);
+	file->private_data = drvdata;
+
+	return	0;
+}
+
+static ssize_t dcc_sram_read(struct file *file, char __user *data,
+						size_t len, loff_t *ppos)
+{
+	unsigned char *buf;
+	struct dcc_drvdata *drvdata = file->private_data;
+
+	/* EOF check */
+	if (drvdata->ram_size <= *ppos)
+		return 0;
+
+	if ((*ppos + len) > drvdata->ram_size)
+		len = (drvdata->ram_size - *ppos);
+
+	buf = kzalloc(len, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	memcpy_fromio(buf, drvdata->ram_base + *ppos, len);
+
+	if (copy_to_user(data, buf, len)) {
+		dev_err(drvdata->dev, "DCC: Couldn't copy all data to user\n");
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	*ppos += len;
+
+	kfree(buf);
+
+	return len;
+}
+
+static const struct file_operations dcc_sram_fops = {
+	.owner		= THIS_MODULE,
+	.open		= dcc_sram_open,
+	.read		= dcc_sram_read,
+	.llseek		= no_llseek,
+};
+
+static int dcc_sram_dev_register(struct dcc_drvdata *drvdata)
+{
+	int ret;
+	struct device *device;
+	dev_t dev;
+
+	ret = alloc_chrdev_region(&dev, 0, 1, drvdata->sram_node);
+	if (ret)
+		goto err_alloc;
+
+	cdev_init(&drvdata->sram_dev, &dcc_sram_fops);
+
+	drvdata->sram_dev.owner = THIS_MODULE;
+	ret = cdev_add(&drvdata->sram_dev, dev, 1);
+	if (ret)
+		goto err_cdev_add;
+
+	drvdata->sram_class = class_create(THIS_MODULE, drvdata->sram_node);
+	if (IS_ERR(drvdata->sram_class)) {
+		ret = PTR_ERR(drvdata->sram_class);
+		goto err_class_create;
+	}
+
+	device = device_create(drvdata->sram_class, NULL,
+						drvdata->sram_dev.dev, drvdata,
+						drvdata->sram_node);
+	if (IS_ERR(device)) {
+		ret = PTR_ERR(device);
+		goto err_dev_create;
+	}
+
+	return 0;
+err_dev_create:
+	class_destroy(drvdata->sram_class);
+err_class_create:
+	cdev_del(&drvdata->sram_dev);
+err_cdev_add:
+	unregister_chrdev_region(drvdata->sram_dev.dev, 1);
+err_alloc:
+	return ret;
+}
+
+static void dcc_sram_dev_deregister(struct dcc_drvdata *drvdata)
+{
+	device_destroy(drvdata->sram_class, drvdata->sram_dev.dev);
+	class_destroy(drvdata->sram_class);
+	cdev_del(&drvdata->sram_dev);
+	unregister_chrdev_region(drvdata->sram_dev.dev, 1);
+}
+
+static int dcc_sram_dev_init(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+
+	drvdata->sram_node = DCC_SRAM_NODE;
+	if (!drvdata->sram_node)
+		return -ENOMEM;
+
+	ret = dcc_sram_dev_register(drvdata);
+	if (ret)
+		dev_err(drvdata->dev, "DCC: sram node not registered.\n");
+
+	return ret;
+}
+
+static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata)
+{
+	dcc_sram_dev_deregister(drvdata);
+}
+
+static int dcc_probe(struct platform_device *pdev)
+{
+	int ret = 0, i;
+	struct device *dev = &pdev->dev;
+	struct dcc_drvdata *dcc;
+	struct resource *res;
+	const struct qcom_dcc_config *cfg;
+
+	dcc = devm_kzalloc(dev, sizeof(*dcc), GFP_KERNEL);
+	if (!dcc)
+		return -ENOMEM;
+
+	dcc->dev = &pdev->dev;
+	platform_set_drvdata(pdev, dcc);
+
+	dcc->base = devm_platform_ioremap_resource_byname(pdev, "dcc");
+	if (!dcc->base)
+		return -ENOMEM;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dcc-ram");
+	if (!res)
+		return -EINVAL;
+
+	dcc->ram_size = resource_size(res);
+
+	dcc->ram_base = devm_ioremap(dev, res->start, resource_size(res));
+	if (!dcc->ram_base)
+		return -ENOMEM;
+
+	cfg = of_device_get_match_data(&pdev->dev);
+	dcc->ram_offset = cfg->dcc_ram_offset;
+
+	if (FIELD_GET(BIT(DCC_VER_INFO_BIT), dcc_readl(dcc, DCC_HW_INFO))) {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER3;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;
+	} else if ((dcc_readl(dcc, DCC_HW_INFO) & DCC_VER_MASK2) == DCC_VER_MASK2) {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER2;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;
+	} else {
+		dcc->mem_map_ver = DCC_MEM_MAP_VER1;
+		dcc->nr_link_list = DCC_MAX_LINK_LIST;
+	}
+
+	if ((dcc_readl(dcc, DCC_HW_INFO) & BIT(6)) == BIT(6))
+		dcc->loopoff = DCC_FIX_LOOP_OFFSET;
+	else
+		dcc->loopoff = get_bitmask_order((dcc->ram_size +
+				dcc->ram_offset) / 4 - 1);
+
+	mutex_init(&dcc->mutex);
+	dcc->enable = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(bool), GFP_KERNEL);
+	if (!dcc->enable)
+		return -ENOMEM;
+
+	dcc->configured = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(bool), GFP_KERNEL);
+	if (!dcc->configured)
+		return -ENOMEM;
+
+	dcc->nr_config = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(u32), GFP_KERNEL);
+	if (!dcc->nr_config)
+		return -ENOMEM;
+
+	dcc->cfg_head = devm_kcalloc(dev, dcc->nr_link_list,
+			sizeof(struct list_head), GFP_KERNEL);
+	if (!dcc->cfg_head)
+		return -ENOMEM;
+
+	for (i = 0; i < dcc->nr_link_list; i++)
+		INIT_LIST_HEAD(&dcc->cfg_head[i]);
+
+
+	memset_io(dcc->ram_base, 0, dcc->ram_size);
+	dcc->curr_list = DCC_INVALID_LINK_LIST;
+	ret = dcc_sram_dev_init(dcc);
+	if (ret)
+		goto out;
+
+	ret = dcc_create_files(dev, dcc_attrs);
+	if (ret)
+		goto out;
+
+out:
+	return ret;
+}
+
+static int dcc_remove(struct platform_device *pdev)
+{
+	struct dcc_drvdata *drvdata = platform_get_drvdata(pdev);
+
+	dcc_sram_dev_exit(drvdata);
+
+	dcc_config_reset(drvdata);
+
+	return 0;
+}
+
+static const struct qcom_dcc_config sm8150_cfg = {
+	.dcc_ram_offset	= 0x5000,
+};
+
+static const struct of_device_id dcc_match_table[] = {
+	{ .compatible = "qcom,sm8150-dcc", .data = &sm8150_cfg },
+};
+MODULE_DEVICE_TABLE(of, dcc_match_table);
+
+static struct platform_driver dcc_driver = {
+	.probe					= dcc_probe,
+	.remove					= dcc_remove,
+	.driver					= {
+		.name		= "qcom-dcc",
+		.of_match_table	= dcc_match_table,
+	},
+};
+
+module_platform_driver(dcc_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver");
+
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[Resend PATCH V3 3/5] DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver

[Souradeep Chowdhury]

The DCC is a DMA engine designed to store register values either in
case of a system crash or in case of software triggers manually done
by the user.Using DCC hardware and the sysfs interface of the driver
the user can exploit various functionalities of DCC.The user can specify
the register addresses,the values of which is stored by DCC in it's
dedicated SRAM.The register addresses can be used either to read from,
write to,first read and store value and then write or to loop.All these
options can be exploited using the sysfs interface given to the user.
Following are the sysfs interfaces exposed in DCC driver which are
documented
1)trigger
2)config
3)config_write
4)config_reset
5)enable
6)rd_mod_wr
7)loop

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 Documentation/ABI/testing/sysfs-driver-dcc | 114 +++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc

diff --git a/Documentation/ABI/testing/sysfs-driver-dcc b/Documentation/ABI/testing/sysfs-driver-dcc
new file mode 100644
index 0000000..05d24f0
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-dcc
@@ -0,0 +1,114 @@
+What:           /sys/bus/platform/devices/.../trigger
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This is the sysfs interface for manual software
+		triggers.The user can simply enter a 1 against
+		the sysfs file and enable a manual trigger.
+		Example:
+		echo  1 > /sys/bus/platform/devices/.../trigger
+
+What:           /sys/bus/platform/devices/.../enable
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This sysfs interface is used for enabling the
+		the dcc hardware.Without this being set to 1,
+		the dcc hardware ceases to function.
+		Example:
+		echo  0 > /sys/bus/platform/devices/.../enable
+		(disable interface)
+		echo  1 > /sys/bus/platform/devices/.../enable
+		(enable interface)
+
+What:           /sys/bus/platform/devices/.../config
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This is the most commonly used sysfs interface
+		file and this basically stores the addresses of
+		the registers which needs to be read in case of
+		a hardware crash or manual software triggers.
+		Example:
+		echo  0x80000010 10 > /sys/bus/platform/devices/../config
+		This specifies that 10 words starting from address
+		0x80000010 is to be read.In case there are no words to be
+		specified we can simply enter the address.
+
+What:           /sys/bus/platform/devices/.../config_write
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file allows user to write a value to the register
+		address given as argument.The values are entered in the
+		form of <register_address> <value>.The reason for this
+		feature of dcc is that for accessing certain registers
+		it is necessary to set some bits of soe other register.
+		That is achievable by giving DCC this privelege.
+		Example:
+		echo 0x80000000 0xFF > /sys/bus/platform/devices/.../config_write
+
+What:           /sys/bus/platform/devices/.../config_reset
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to reset the configuration of
+		a dcc driver to the default configuration.
+		Example:
+		echo  1 > /sys/bus/platform/devices/.../config_reset
+
+What:           /sys/bus/platform/devices/.../loop
+Date:		March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to enter the loop count as dcc
+		driver gives the option to loop multiple times on
+		the same register and store the values for each
+		loop.This is done to capture the changing values
+		of a register with time which comes handy for
+		debugging purposes.
+		Example:
+		echo 10 > /sys/bus/platform/devices/10a2000.dcc/loop
+		(Setting the loop count to 10)
+		echo  0x80000010 10 > /sys/bus/platform/devices/.../config
+                (Read 10 words starting from address 0x80000010O)
+		echo 1 > /sys/bus/platform/devices/.../loop
+		(Terminate the loop by writing a count of 1 to the loop sysfs node)
+
+What:           /sys/bus/platform/devices/.../rd_mod_wr
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to read the value of the register
+		and then write the value given as an argument to the
+		register address in config.The address argument should
+		be given of the form <mask> <value>.For debugging
+		purposes sometimes we need to first read from a register
+		and then set some values to the register.
+		Example:
+		echo 0x80000000 > /sys/bus/platform/devices/.../config
+		(Set the address in config file)
+		echo 0xF 0xA > /sys/bus/platform/devices/.../rd_mod_wr
+		(Provide the mask and the value to write)
+
+What:           /sys/bus/platform/devices/.../ready
+Date:           March 2021
+Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This file is used to check the status of the dcc
+		hardware if it's ready to take the inputs.
+		Example:
+		cat /sys/bus/platform/devices/.../ready
+
+What:		/sys/bus/platform/devices/.../curr_list
+Date:		February 2021
+Contact:	Souradeep Chowdhury <schowdhu@codeaurora.org>
+Description:
+		This attribute is used to enter the linklist to be
+		used while appending addresses.The range of values
+		for this can be from 0 to 3.This feature is given in
+		order to use certain linkedlist for certain debugging
+		purposes.
+		Example:
+		echo 0 > /sys/bus/platform/devices/10a2000.dcc/curr_list
+
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[Resend PATCH V3 4/5] MAINTAINERS:Add the entry for DCC(Data Capture and Compare) driver support

[Souradeep Chowdhury]

Added the entries for all the files added as a part of driver support for
DCC(Data Capture and Compare).

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85c..fb28218 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4969,6 +4969,14 @@ F:	include/linux/tfrc.h
 F:	include/uapi/linux/dccp.h
 F:	net/dccp/

+QTI DCC DRIVER
+M:	Souradeep Chowdhury <schowdhu@codeaurora.org>
+L:	linux-arm-msm@vger.kernel.org
+S:	Maintained
+F:	Documentation/ABI/testing/sysfs-driver-dcc
+F:	Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
+F:	drivers/soc/qcom/dcc.c
+
 DECnet NETWORK LAYER
 L:	linux-decnet-user@lists.sourceforge.net
 S:	Orphan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[Resend PATCH V3 5/5] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node

[Souradeep Chowdhury]

Add the DCC(Data Capture and Compare) device tree node entry along with
the addresses for register regions.

Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index e5bb17b..ba6acf4 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -654,6 +654,13 @@
 			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 		};

+		dcc@10a2000 {
+			compatible = "qcom,sm8150-dcc", "qcom,dcc";
+			reg = <0x0 0x010a2000 0x0 0x1000>,
+			      <0x0 0x010ad000 0x0 0x3000>;
+			reg-names = "dcc", "dcc-ram";
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH V3 1/5] dt-bindings: Added the yaml bindings for DCC

[schowdhu]

On 2021-03-29 12:02, Souradeep Chowdhury wrote:
> Documentation for Data Capture and Compare(DCC) device tree bindings
> in yaml format.
> 

Resent this patch by adding the review tag

Link as follows

https://lore.kernel.org/lkml/20210329074909.vpO1kbU39ZSxJpJFZqQc-9i_h5ucqyd4gqZK3a1DQtg@z/

> Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
> ---
>  .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 
> ++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
> b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
> new file mode 100644
> index 0000000..c6e0a9c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Data Capture and Compare
> +
> +maintainers:
> +  - Souradeep Chowdhury <schowdhu@codeaurora.org>
> +
> +description: |
> +    DCC (Data Capture and Compare) is a DMA engine which is used to 
> save
> +    configuration data or system memory contents during catastrophic 
> failure
> +    or SW trigger.DCC is used to capture and store data for debugging 
> purpose
> +
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - qcom,sm8150-dcc
> +      - const: qcom,dcc
> +
> +  reg:
> +    items:
> +      - description: DCC base register region
> +      - description: DCC RAM base register region
> +
> +  reg-names:
> +    items:
> +      - const: dcc
> +      - const: dcc-ram
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    dcc@10a2000{
> +                compatible = "qcom,sm8150-dcc","qcom,dcc";
> +                reg = <0x010a2000  0x1000>,
> +                      <0x010ad000  0x2000>;
> +                reg-names = "dcc", "dcc-ram";
> +    };

Re: [PATCH V2 1/5] dt-bindings: Added the yaml bindings for DCC

[Stephen Boyd]

Quoting Souradeep Chowdhury (2021-03-25 01:02:32)
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
> new file mode 100644
> index 0000000..c6e0a9c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Data Capture and Compare
> +
> +maintainers:
> +  - Souradeep Chowdhury <schowdhu@codeaurora.org>
> +
> +description: |
> +    DCC (Data Capture and Compare) is a DMA engine which is used to save
> +    configuration data or system memory contents during catastrophic failure
> +    or SW trigger.DCC is used to capture and store data for debugging purpose

Add space between trigger. and DCC?

> +
> +

Drop double newline?

> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - qcom,sm8150-dcc
> +      - const: qcom,dcc
> +
> +  reg:
> +    items:
> +      - description: DCC base register region
> +      - description: DCC RAM base register region
> +
> +  reg-names:
> +    items:
> +      - const: dcc
> +      - const: dcc-ram
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names

Do we really need reg names? Seems like we can assume the ordering.

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    dcc@10a2000{

dma@10a2000? Or debug@10a2000?

> +                compatible = "qcom,sm8150-dcc","qcom,dcc";
> +                reg = <0x010a2000  0x1000>,
> +                      <0x010ad000  0x2000>;
> +                reg-names = "dcc", "dcc-ram";
> +    };

Re: [PATCH V2 2/5] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)

[Stephen Boyd]

Quoting Souradeep Chowdhury (2021-03-25 01:02:33)
> The DCC is a DMA Engine designed to capture and store data
> during system crash or software triggers.The DCC operates
> based on user inputs via the sysfs interface.The user gives
> addresses as inputs and these addresses are stored in the
> form of linkedlists.In case of a system crash or a manual
> software trigger by the user through the sysfs interface,
> the dcc captures and stores the values at these addresses.
> This patch contains the driver which has all the methods
> pertaining to the sysfs interface, auxiliary functions to
> support all the four fundamental operations of dcc namely
> read, write, first read then write and loop.The probe method
> here instantiates all the resources necessary for dcc to
> operate mainly the dedicated dcc sram where it stores the
> values.The DCC driver can be used for debugging purposes
> without going for a reboot since it can perform manual
> triggers.
> 
> Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
> ---
>  drivers/soc/qcom/Kconfig  |    8 +
>  drivers/soc/qcom/Makefile |    1 +
>  drivers/soc/qcom/dcc.c    | 1549 +++++++++++++++++++++++++++++++++++++++++++++

Where's the document for various sysfs attributes in Documentation/ABI?

>  3 files changed, 1558 insertions(+)
>  create mode 100644 drivers/soc/qcom/dcc.c
> 
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 79b568f..8819e0b 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -69,6 +69,14 @@ config QCOM_LLCC
>           SDM845. This provides interfaces to clients that use the LLCC.
>           Say yes here to enable LLCC slice driver.
> 
> +config QCOM_DCC
> +       tristate "Qualcomm Technologies, Inc. Data Capture and Compare engine driver"

Put (DCC) after Compare?

> +       depends on ARCH_QCOM || COMPILE_TEST
> +       help
> +         This option enables driver for Data Capture and Compare engine. DCC
> +         driver provides interface to configure DCC block and read back
> +         captured data from DCC's internal SRAM.
> +
>  config QCOM_KRYO_L2_ACCESSORS
>         bool
>         depends on ARCH_QCOM && ARM64 || COMPILE_TEST
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index ad675a6..1b00870 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
>  obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
>  obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
>  obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=        kryo-l2-accessors.o
> +obj-$(CONFIG_QCOM_DCC) += dcc.o

Can this be sorted based on config or file name instead of adding to the
end of the file and leading to endless conflicts?

> diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c
> new file mode 100644
> index 0000000..a55d8ca7
> --- /dev/null
> +++ b/drivers/soc/qcom/dcc.c
> @@ -0,0 +1,1549 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <linux/cdev.h>
> +#include <linux/delay.h>
> +#include <linux/fs.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/uaccess.h>
> +
> +
> +#define TIMEOUT_US             100
> +
> +#define dcc_writel(drvdata, val, off)                                  \
> +       writel((val), drvdata->base + dcc_offset_conv(drvdata, off))
> +#define dcc_readl(drvdata, off)                                                \
> +       readl(drvdata->base + dcc_offset_conv(drvdata, off))
> +
> +#define dcc_sram_readl(drvdata, off)                                   \
> +       readl(drvdata->ram_base + off)
> +
> +#define DCC_SRAM_NODE "dcc_sram"
> +
> +/* DCC registers */
> +#define DCC_HW_INFO                    0x04
> +#define DCC_LL_NUM_INFO                        0x10
> +#define DCC_STATUS                     0x1C
> +#define DCC_LL_LOCK(m)                 (0x34 + 0x80 * m)
> +#define DCC_LL_CFG(m)                  (0x38 + 0x80 * m)
> +#define DCC_LL_BASE(m)                 (0x3c + 0x80 * m)
> +#define DCC_FD_BASE(m)                 (0x40 + 0x80 * m)
> +#define DCC_LL_TIMEOUT(m)              (0x44 + 0x80 * m)
> +#define DCC_LL_INT_ENABLE(m)           (0x4C + 0x80 * m)
> +#define DCC_LL_INT_STATUS(m)           (0x50 + 0x80 * m)
> +#define DCC_LL_SW_TRIGGER(m)           (0x60 + 0x80 * m)
> +#define DCC_LL_BUS_ACCESS_STATUS(m)    (0x64 + 0x80 * m)
> +
> +#define DCC_MAP_LEVEL1                 0x18
> +#define DCC_MAP_LEVEL2                 0x34
> +#define DCC_MAP_LEVEL3                 0x4C
> +
> +#define DCC_MAP_OFFSET1                        0x10
> +#define DCC_MAP_OFFSET2                        0x18
> +#define DCC_MAP_OFFSET3                        0x1C
> +#define DCC_MAP_OFFSET4                        0x8
> +
> +#define DCC_FIX_LOOP_OFFSET            16
> +#define DCC_VER_INFO_BIT               9
> +
> +#define DCC_READ                       0
> +#define DCC_WRITE                      1
> +#define DCC_LOOP                       2
> +#define DCC_READ_WRITE                 3
> +
> +#define MAX_DCC_OFFSET                 GENMASK(9, 2)
> +#define MAX_DCC_LEN                    GENMASK(6, 0)
> +#define MAX_LOOP_CNT                   GENMASK(7, 0)
> +
> +#define DCC_ADDR_DESCRIPTOR            0x00
> +#define DCC_LOOP_DESCRIPTOR            BIT(30)
> +#define DCC_RD_MOD_WR_DESCRIPTOR       BIT(31)
> +#define DCC_LINK_DESCRIPTOR            GENMASK(31, 30)
> +
> +#define DCC_READ_IND                   0x00
> +#define DCC_WRITE_IND                  (BIT(28))
> +
> +#define DCC_AHB_IND                    0x00
> +#define DCC_APB_IND                    BIT(29)
> +
> +#define DCC_MAX_LINK_LIST              8
> +#define DCC_INVALID_LINK_LIST          GENMASK(7, 0)
> +
> +#define DCC_VER_MASK1                  GENMASK(6, 0)
> +#define DCC_VER_MASK2                  GENMASK(5, 0)
> +
> +#define DCC_RD_MOD_WR_ADDR              0xC105E
> +
> +struct qcom_dcc_config {
> +       const int dcc_ram_offset;

Why const here? The container structure can be const and then this is
easier to read.

> +};
> +
> +enum dcc_descriptor_type {
> +       DCC_ADDR_TYPE,
> +       DCC_LOOP_TYPE,
> +       DCC_READ_WRITE_TYPE,
> +       DCC_WRITE_TYPE
> +};
> +
> +enum dcc_mem_map_ver {
> +       DCC_MEM_MAP_VER1 = 1,
> +       DCC_MEM_MAP_VER2 = 2,
> +       DCC_MEM_MAP_VER3 = 3
> +};
> +
> +struct dcc_config_entry {
> +       u32                             base;
> +       u32                             offset;
> +       u32                             len;
> +       u32                             index;
> +       u32                             loop_cnt;
> +       u32                             write_val;
> +       u32                             mask;
> +       bool                            apb_bus;
> +       enum dcc_descriptor_type        desc_type;
> +       struct list_head                list;
> +};
> +
> +struct dcc_drvdata {

Can we get some kernel doc on this structure?

> +       void __iomem            *base;
> +       u32                     reg_size;
> +       struct device           *dev;
> +       struct mutex            mutex;

In particular what this mutex is protecting.

> +       void __iomem            *ram_base;
> +       u32                     ram_size;
> +       u32                     ram_offset;
> +       enum dcc_mem_map_ver    mem_map_ver;
> +       u32                     ram_cfg;
> +       u32                     ram_start;

phys_addr_t?

> +       bool                    *enable;
> +       bool                    *configured;
> +       bool                    interrupt_disable;
> +       char                    *sram_node;

This is always a define, so why make a struct member?

> +       struct cdev             sram_dev;
> +       struct class            *sram_class;
> +       struct list_head        *cfg_head;
> +       u32                     *nr_config;
> +       u32                     nr_link_list;

size_t?

> +       u8                      curr_list;
> +       u8                      loopoff;
> +};
> +
> +struct dcc_cfg_attr {
> +       u32     addr;
> +       u32     prev_addr;
> +       u32     prev_off;
> +       u32     link;
> +       u32     sram_offset;
> +};
> +
> +struct dcc_cfg_loop_attr {
> +       u32     loop;
> +       bool    loop_start;
> +       u32     loop_cnt;
> +       u32     loop_len;
> +       u32     loop_off;
> +};
> +
> +static size_t dcc_offset_conv(struct dcc_drvdata *drvdata, size_t off)
> +{
> +       if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) {
> +               if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL3)
> +                       return (off - DCC_MAP_OFFSET3);

Drop useless parenthesis please.

> +               if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
> +                       return (off - DCC_MAP_OFFSET2);

Drop useless parenthesis please.

> +               else if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL1)
> +                       return (off - DCC_MAP_OFFSET1);

Drop useless parenthesis please.

> +       } else if (drvdata->mem_map_ver == DCC_MEM_MAP_VER2) {
> +               if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
> +                       return (off - DCC_MAP_OFFSET4);

Drop useless parenthesis please.

> +       }

Newline please.

> +       return off;
> +}
> +
> +static int dcc_sram_writel(struct dcc_drvdata *drvdata,
> +                                       u32 val, u32 off)
> +{
> +       if (unlikely(off > (drvdata->ram_size - 4)))
> +               return -EINVAL;

Can this be pushed up one level? It would be great if we didn't have to
track the fact that we've gone off the end of the ram in each writel
call, instead doing something for every word in the ram and stopping
that loop higher up.

> +
> +       writel((val), drvdata->ram_base + off);

Drop useless parenthesis please.

> +
> +       return 0;
> +}
> +
> +static bool dcc_ready(struct dcc_drvdata *drvdata)
> +{
> +       u32 val;
> +
> +       /* poll until DCC ready */

Drop useless comment please.

> +       if (!readl_poll_timeout((drvdata->base + DCC_STATUS), val,
> +                               (FIELD_GET(GENMASK(1, 0), val) == 0), 1, TIMEOUT_US))
> +               return true;
> +
> +       return false;

return !readl_poll_timeout(...) instead?

> +}
> +
> +static int dcc_read_status(struct dcc_drvdata *drvdata)
> +{
> +       int curr_list;
> +       u32 bus_status;
> +       u32 ll_cfg = 0;
> +       u32 tmp_ll_cfg = 0;

Drop assignments as they're overwritten.

> +
> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
> +               if (!drvdata->enable[curr_list])
> +                       continue;
> +
> +               bus_status = dcc_readl(drvdata, DCC_LL_BUS_ACCESS_STATUS(curr_list));
> +
> +               if (bus_status) {
> +                       dev_err(drvdata->dev,
> +                               "Read access error for list %d err: 0x%x.\n",
> +                               curr_list, bus_status);
> +
> +                       ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
> +                       tmp_ll_cfg = ll_cfg & ~BIT(9);
> +                       dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
> +                       dcc_writel(drvdata, 0x3,
> +                               DCC_LL_BUS_ACCESS_STATUS(curr_list));
> +                       dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
> +                       return -ENODATA;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int dcc_sw_trigger(struct dcc_drvdata *drvdata)
> +{
> +       int ret = 0;
> +       int curr_list;
> +       u32 ll_cfg = 0;
> +       u32 tmp_ll_cfg = 0;

Drop assignments as they're overwritten.

> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
> +               if (!drvdata->enable[curr_list])
> +                       continue;
> +               ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
> +               tmp_ll_cfg = ll_cfg & ~BIT(9);
> +               dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
> +               dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
> +               dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
> +       }

Does the mutex need to be held while waiting for ready?

> +
> +       if (!dcc_ready(drvdata)) {
> +               dev_err(drvdata->dev,
> +                       "DCC is busy after receiving sw tigger.\n");
> +               ret = -EBUSY;
> +               goto err;
> +       }
> +
> +       ret = dcc_read_status(drvdata);
> +
> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return ret;
> +}
> +
> +static void _dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg)
> +{
> +       cfg->addr = 0x00;
> +       cfg->link = 0;
> +       cfg->prev_off = 0;
> +       cfg->prev_addr = cfg->addr;
> +}
> +
> +static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata,
> +                                 struct dcc_config_entry *entry,
> +                                 struct dcc_cfg_attr *cfg)
> +{
> +       int ret;
> +
> +       if (cfg->link) {
> +               /*
> +                * write new offset = 1 to continue
> +                * processing the list
> +                */
> +
> +               ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
> +               if (ret)
> +                       return ret;
> +               cfg->sram_offset += 4;
> +               /* Reset link and prev_off */
> +               _dcc_ll_cfg_reset_link(cfg);
> +       }
> +
> +       cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR;
> +       ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
> +       if (ret)
> +               return ret;
> +
> +       cfg->sram_offset += 4;
> +       ret = dcc_sram_writel(drvdata, entry->mask, cfg->sram_offset);
> +       if (ret)
> +               return ret;
> +
> +       cfg->sram_offset += 4;
> +       ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
> +       if (ret)
> +               return ret;
> +
> +       cfg->sram_offset += 4;
> +       cfg->addr = 0;
> +       return ret;
> +}
> +
> +static int _dcc_ll_cfg_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry,
> +                           struct dcc_cfg_attr *cfg,
> +                           struct dcc_cfg_loop_attr *cfg_loop,
> +                           u32 *total_len)
> +{
> +
> +       int ret;
> +
> +       /* Check if we need to write link of prev entry */
> +       if (cfg->link) {
> +               ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
> +               if (ret)
> +                       return ret;
> +               cfg->sram_offset += 4;
> +       }
> +
> +       if (cfg_loop->loop_start) {
> +               cfg_loop->loop = (cfg->sram_offset - cfg_loop->loop_off) / 4;
> +               cfg_loop->loop |= (cfg_loop->loop_cnt << drvdata->loopoff) &
> +               GENMASK(27, drvdata->loopoff);

What is 27? Can it be a define?

> +               cfg_loop->loop |= DCC_LOOP_DESCRIPTOR;
> +               *total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt;
> +
> +               ret = dcc_sram_writel(drvdata, cfg_loop->loop, cfg->sram_offset);
> +

Drop newline?

> +               if (ret)
> +                       return ret;
> +               cfg->sram_offset += 4;
> +
> +               cfg_loop->loop_start = false;
> +               cfg_loop->loop_len = 0;
> +               cfg_loop->loop_off = 0;
> +       } else {
> +               cfg_loop->loop_start = true;
> +               cfg_loop->loop_cnt = entry->loop_cnt - 1;
> +               cfg_loop->loop_len = *total_len;
> +               cfg_loop->loop_off = cfg->sram_offset;
> +       }
> +
> +       /* Reset link and prev_off */
> +

Drop newline?

> +       _dcc_ll_cfg_reset_link(cfg);
> +
> +       return ret;
> +}
> +
> +static int _dcc_ll_cfg_write(struct dcc_drvdata *drvdata,
> +                            struct dcc_config_entry *entry,
> +                            struct dcc_cfg_attr *cfg,
> +                            u32 *total_len)
> +{
> +       u32 off;
> +       int ret;
> +
> +       if (cfg->link) {
> +               /*
> +                * write new offset = 1 to continue
> +                * processing the list
> +                */
> +               ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
> +
> +               if (ret)
> +                       return ret;
> +
> +               cfg->sram_offset += 4;
> +               /* Reset link and prev_off */
> +               cfg->addr = 0x00;
> +               cfg->prev_off = 0;
> +               cfg->prev_addr = cfg->addr;
> +       }
> +
> +       off = entry->offset/4;
> +       /* write new offset-length pair to correct position */
> +       cfg->link |= ((off & GENMASK(7, 0)) | BIT(15) | ((entry->len << 8) & GENMASK(14, 8)));
> +       cfg->link |= DCC_LINK_DESCRIPTOR;
> +
> +       /* Address type */
> +       cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
> +       if (entry->apb_bus)
> +               cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND;
> +       else
> +               cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND;
> +       ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
> +
> +       if (ret)
> +               return ret;
> +       cfg->sram_offset += 4;
> +
> +       ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
> +       if (ret)
> +               return ret;
> +       cfg->sram_offset += 4;
> +
> +       ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
> +
> +       if (ret)
> +               return ret;
> +
> +       cfg->sram_offset += 4;
> +       cfg->addr = 0x00;
> +       cfg->link = 0;
> +       return ret;
> +}
> +
> +static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
> +                              struct dcc_config_entry *entry,
> +                              struct dcc_cfg_attr *cfg,
> +                              u32 *pos, u32 *total_len)
> +{
> +       int ret;
> +       u32 off;
> +
> +       cfg->addr = (entry->base >> 4) & GENMASK(27, 0);

There's 27 again!

> +
> +       if (entry->apb_bus)
> +               cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND;
> +       else
> +               cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND;
> +
> +       off = entry->offset/4;
> +
> +       *total_len += entry->len * 4;
> +
> +       if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) {
> +               /* Check if we need to write prev link entry */
> +               if (cfg->link) {
> +                       ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
> +                       if (ret)
> +                               return ret;
> +                       cfg->sram_offset += 4;
> +               }
> +               dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset);
> +
> +               /* Write address */
> +               ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
> +
> +               if (ret)
> +                       return ret;
> +
> +               cfg->sram_offset += 4;
> +
> +               /* Reset link and prev_off */
> +               cfg->link = 0;
> +               cfg->prev_off = 0;
> +       }
> +
> +       if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
> +               dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n",
> +               entry->base, entry->offset);
> +               ret = -EINVAL;
> +               return ret;
> +       }
> +
> +       if (cfg->link) {
> +               /*
> +                * link already has one offset-length so new
> +                * offset-length needs to be placed at
> +                * bits [29:15]
> +                */
> +               *pos = 15;
> +
> +               /* Clear bits [31:16] */
> +               cfg->link &= GENMASK(14, 0);
> +       } else {
> +               /*
> +                * link is empty, so new offset-length needs
> +                * to be placed at bits [15:0]
> +                */
> +               *pos = 0;
> +               cfg->link = 1 << 15;
> +       }
> +
> +       /* write new offset-length pair to correct position */
> +       cfg->link |= (((off-cfg->prev_off) & GENMASK(7, 0)) |
> +                    ((entry->len << 8) & GENMASK(14, 8))) << *pos;

Can this be split to multiple statements? It's crazy hard to read.

> +
> +       cfg->link |= DCC_LINK_DESCRIPTOR;
> +
> +       if (*pos) {
> +               ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
> +               if (ret)
> +                       return ret;
> +               cfg->sram_offset += 4;
> +               cfg->link = 0;
> +       }
> +
> +       cfg->prev_off  = off + entry->len - 1;
> +       cfg->prev_addr = cfg->addr;
> +       return ret;
> +}
> +
> +static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list)
> +{
> +       int ret = 0;
> +       u32 total_len, pos;
> +       struct dcc_config_entry *entry;
> +       struct dcc_cfg_attr cfg;
> +       struct dcc_cfg_loop_attr cfg_loop;
> +
> +       memset(&cfg, 0, sizeof(cfg));
> +       memset(&cfg_loop, 0, sizeof(cfg_loop));
> +       cfg.sram_offset = drvdata->ram_cfg * 4;
> +       total_len = 0;
> +
> +       list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) {
> +               switch (entry->desc_type) {
> +               case DCC_READ_WRITE_TYPE:
> +                       ret = _dcc_ll_cfg_read_write(drvdata, entry, &cfg);
> +                       if (ret)
> +                               goto overstep;
> +                       break;
> +
> +               case DCC_LOOP_TYPE:
> +                       ret = _dcc_ll_cfg_loop(drvdata, entry, &cfg, &cfg_loop, &total_len);
> +                       if (ret)
> +                               goto overstep;
> +                       break;
> +
> +               case DCC_WRITE_TYPE:
> +                       ret = _dcc_ll_cfg_write(drvdata, entry, &cfg, &total_len);
> +                       if (ret)
> +                               goto overstep;
> +                       break;
> +
> +               default:
> +                       ret = _dcc_ll_cfg_default(drvdata, entry, &cfg, &pos, &total_len);
> +                       if (ret)
> +                               goto overstep;
> +                       break;
> +               }
> +       }
> +
> +       if (cfg.link) {
> +               ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
> +               if (ret)
> +                       goto overstep;
> +               cfg.sram_offset += 4;
> +       }
> +
> +       if (cfg_loop.loop_start) {
> +               dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       /* Handling special case of list ending with a rd_mod_wr */
> +       if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) {
> +               cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0);
> +               cfg.addr |= DCC_ADDR_DESCRIPTOR;
> +               ret = dcc_sram_writel(drvdata, cfg.addr, cfg.sram_offset);
> +               if (ret)
> +                       goto overstep;
> +               cfg.sram_offset += 4;
> +       }
> +
> +       /* Setting zero to indicate end of the list */
> +       cfg.link = DCC_LINK_DESCRIPTOR;
> +       ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
> +       if (ret)
> +               goto overstep;
> +       cfg.sram_offset += 4;
> +
> +       /* Update ram_cfg and check if the data will overstep */
> +
> +       drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4;
> +
> +       if (cfg.sram_offset + total_len > drvdata->ram_size) {
> +               cfg.sram_offset += total_len;
> +               goto overstep;
> +       }
> +
> +       drvdata->ram_start = cfg.sram_offset/4;
> +       return 0;
> +overstep:
> +       ret = -EINVAL;
> +       memset_io(drvdata->ram_base, 0, drvdata->ram_size);
> +       dev_err(drvdata->dev, "DCC SRAM oversteps, 0x%x (0x%x)\n",
> +       cfg.sram_offset, drvdata->ram_size);
> +
> +err:
> +       return ret;
> +}
> +
> +static int dcc_valid_list(struct dcc_drvdata *drvdata, int curr_list)
> +{
> +       u32 lock_reg;
> +
> +       if (list_empty(&drvdata->cfg_head[curr_list]))
> +               return -EINVAL;
> +
> +       if (drvdata->enable[curr_list]) {
> +               dev_err(drvdata->dev, "List %d is already enabled\n",
> +                               curr_list);
> +               return -EINVAL;
> +       }
> +
> +       lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(curr_list));
> +       if (lock_reg & 0x1) {
> +               dev_err(drvdata->dev, "List %d is already locked\n",
> +                               curr_list);
> +               return -EINVAL;
> +       }
> +
> +       dev_err(drvdata->dev, "DCC list passed %d\n", curr_list);
> +       return 0;
> +}
> +
> +static bool is_dcc_enabled(struct dcc_drvdata *drvdata)
> +{
> +       bool dcc_enable = false;
> +       int list;
> +
> +       for (list = 0; list < DCC_MAX_LINK_LIST; list++) {
> +               if (drvdata->enable[list]) {
> +                       dcc_enable = true;
> +                       break;
> +               }
> +       }
> +
> +       return dcc_enable;
> +}
> +
> +static int dcc_enable(struct dcc_drvdata *drvdata)
> +{
> +       int ret = 0;
> +       int list;
> +       u32 ram_cfg_base;
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       if (!is_dcc_enabled(drvdata)) {
> +               memset_io(drvdata->ram_base,
> +                       0xDE, drvdata->ram_size);
> +       }
> +
> +       for (list = 0; list < drvdata->nr_link_list; list++) {
> +
> +               if (dcc_valid_list(drvdata, list))
> +                       continue;
> +
> +               /* 1. Take ownership of the list */
> +               dcc_writel(drvdata, BIT(0), DCC_LL_LOCK(list));
> +
> +               /* 2. Program linked-list in the SRAM */
> +               ram_cfg_base = drvdata->ram_cfg;
> +               ret = __dcc_ll_cfg(drvdata, list);
> +               if (ret) {
> +                       dcc_writel(drvdata, 0, DCC_LL_LOCK(list));
> +                       dev_info(drvdata->dev, "DCC ram programming failed\n");
> +                       goto err;
> +               }
> +
> +               /* 3. program DCC_RAM_CFG reg */
> +               dcc_writel(drvdata, ram_cfg_base +
> +                       drvdata->ram_offset/4, DCC_LL_BASE(list));
> +               dcc_writel(drvdata, drvdata->ram_start +
> +                       drvdata->ram_offset/4, DCC_FD_BASE(list));
> +               dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list));
> +
> +               /* 4. Clears interrupt status register */
> +               dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list));
> +               dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)),
> +                                       DCC_LL_INT_STATUS(list));
> +
> +               dev_info(drvdata->dev, "All values written to enable.\n");

Debug print?

> +               /* Make sure all config is written in sram */
> +               mb();

This won't work as intended.

> +
> +               drvdata->enable[list] = true;
> +
> +               /* 5. Configure trigger */
> +               dcc_writel(drvdata, BIT(9), DCC_LL_CFG(list));
> +       }
> +
> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return ret;
> +}
> +
> +static void dcc_disable(struct dcc_drvdata *drvdata)
> +{
> +       int curr_list;
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       if (!dcc_ready(drvdata))
> +               dev_err(drvdata->dev, "DCC is not ready Disabling DCC...\n");

Is that two sentences? And a debug print?

> +
> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
> +               if (!drvdata->enable[curr_list])
> +                       continue;
> +               dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list));
> +               dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list));
> +               dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list));
> +               dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
> +               drvdata->enable[curr_list] = false;
> +       }
> +       memset_io(drvdata->ram_base, 0, drvdata->ram_size);
> +       drvdata->ram_cfg = 0;
> +       drvdata->ram_start = 0;
> +       mutex_unlock(&drvdata->mutex);
> +}
> +
> +static ssize_t curr_list_show(struct device *dev,
> +       struct device_attribute *attr, char *buf)
> +{
> +       int ret;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       mutex_lock(&drvdata->mutex);
> +       if (drvdata->curr_list == DCC_INVALID_LINK_LIST) {
> +               dev_err(dev, "curr_list is not set.\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       ret = scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->curr_list);
> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return ret;
> +}
> +
> +static ssize_t curr_list_store(struct device *dev,
> +                                               struct device_attribute *attr,
> +                                               const char *buf, size_t size)
> +{
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +       unsigned long val;
> +       u32 lock_reg;
> +       bool dcc_enable = false;
> +
> +       if (kstrtoul(buf, 16, &val))
> +               return -EINVAL;
> +
> +       if (val >= drvdata->nr_link_list)
> +               return -EINVAL;
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       dcc_enable = is_dcc_enabled(drvdata);
> +       if (drvdata->curr_list != DCC_INVALID_LINK_LIST && dcc_enable) {
> +               dev_err(drvdata->dev, "DCC is enabled, please disable it first.\n");
> +               mutex_unlock(&drvdata->mutex);
> +               return -EINVAL;
> +       }
> +
> +       lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
> +       if (lock_reg & 0x1) {
> +               dev_err(drvdata->dev, "DCC linked list is already configured\n");
> +               mutex_unlock(&drvdata->mutex);
> +               return -EINVAL;
> +       }
> +       drvdata->curr_list = val;
> +       mutex_unlock(&drvdata->mutex);
> +
> +       return size;
> +}
> +
> +static DEVICE_ATTR_RW(curr_list);
> +
> +
> +static ssize_t trigger_store(struct device *dev,
> +                                       struct device_attribute *attr,
> +                                       const char *buf, size_t size)
> +{
> +       int ret = 0;
> +       unsigned long val;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       if (kstrtoul(buf, 16, &val))
> +               return -EINVAL;
> +       if (val != 1)
> +               return -EINVAL;
> +
> +       ret = dcc_sw_trigger(drvdata);
> +       if (!ret)
> +               ret = size;
> +
> +       return ret;
> +}
> +static DEVICE_ATTR_WO(trigger);
> +
> +static ssize_t enable_show(struct device *dev,
> +       struct device_attribute *attr, char *buf)
> +{
> +       int ret;
> +       bool dcc_enable = false;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       mutex_lock(&drvdata->mutex);
> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> +               dev_err(dev, "Select link list to program using curr_list\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       dcc_enable = is_dcc_enabled(drvdata);
> +
> +       ret = scnprintf(buf, PAGE_SIZE, "%u\n",
> +                               (unsigned int)dcc_enable);
> +err:
> +       mutex_unlock(&drvdata->mutex);

What does the mutex being held serve here?

> +       return ret;
> +}
> +
> +static ssize_t enable_store(struct device *dev,
> +                               struct device_attribute *attr,
> +                               const char *buf, size_t size)
> +{
> +       int ret = 0;
> +       unsigned long val;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       if (kstrtoul(buf, 16, &val))
> +               return -EINVAL;
> +
> +       if (val)
> +               ret = dcc_enable(drvdata);
> +       else
> +               dcc_disable(drvdata);
> +
> +       if (!ret)
> +               ret = size;
> +
> +       return ret;
> +
> +}
> +
> +static DEVICE_ATTR_RW(enable);
> +
> +static ssize_t config_show(struct device *dev,
> +       struct device_attribute *attr, char *buf)
> +{
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +       struct dcc_config_entry *entry;
> +       char local_buf[64];
> +       int len = 0, count = 0;
> +
> +       buf[0] = '\0';

Why?

> +
> +       mutex_lock(&drvdata->mutex);
> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> +               dev_err(dev, "Select link list to program using curr_list\n");
> +               count = -EINVAL;
> +               goto err;
> +       }
> +
> +       list_for_each_entry(entry,
> +       &drvdata->cfg_head[drvdata->curr_list], list) {
> +               switch (entry->desc_type) {
> +               case DCC_READ_WRITE_TYPE:
> +                       len = snprintf(local_buf, 64, "Index: 0x%x, mask: 0x%x, val: 0x%x\n",
> +                               entry->index, entry->mask, entry->write_val);
> +                       break;
> +               case DCC_LOOP_TYPE:
> +                       len = snprintf(local_buf, 64, "Index: 0x%x, Loop: %d\n",
> +                               entry->index, entry->loop_cnt);
> +                       break;
> +               case DCC_WRITE_TYPE:
> +                       len = snprintf(local_buf, 64,
> +                               "Write Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
> +                               entry->index, entry->base, entry->offset, entry->len,
> +                               entry->apb_bus);
> +                       break;
> +               default:
> +                       len = snprintf(local_buf, 64,
> +                               "Read Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
> +                               entry->index, entry->base, entry->offset,
> +                               entry->len, entry->apb_bus);
> +               }
> +
> +               if ((count + len) > PAGE_SIZE) {
> +                       dev_err(dev, "DCC: Couldn't write complete config\n");
> +                       break;
> +               }
> +               strlcat(buf, local_buf, PAGE_SIZE);
> +               count += len;
> +       }
> +
> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return count;
> +}
> +
> +static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
> +                               unsigned int len, int apb_bus)
> +{
> +       int ret;
> +       struct dcc_config_entry *entry, *pentry;
> +       unsigned int base, offset;
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> +               dev_err(drvdata->dev, "Select link list to program using curr_list\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       if (!len || len > (drvdata->ram_size / 8)) {

What is 8?

> +               dev_err(drvdata->dev, "DCC: Invalid length\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       base = addr & GENMASK(31, 4);

Make a define for the GENMASK?

> +
> +       if (!list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
> +               pentry = list_last_entry(&drvdata->cfg_head[drvdata->curr_list],
> +                       struct dcc_config_entry, list);
> +
> +               if (pentry->desc_type == DCC_ADDR_TYPE &&
> +                               addr >= (pentry->base + pentry->offset) &&
> +                               addr <= (pentry->base +
> +                                       pentry->offset + MAX_DCC_OFFSET)) {
> +
> +                       /* Re-use base address from last entry */
> +                       base = pentry->base;
> +
> +                       if ((pentry->len * 4 + pentry->base + pentry->offset)
> +                                       == addr) {
> +                               len += pentry->len;
> +
> +                               if (len > MAX_DCC_LEN)
> +                                       pentry->len = MAX_DCC_LEN;
> +                               else
> +                                       pentry->len = len;
> +
> +                               addr = pentry->base + pentry->offset +
> +                                       pentry->len * 4;
> +                               len -= pentry->len;
> +                       }
> +               }
> +       }
> +
> +       offset = addr - base;
> +
> +       while (len) {
> +               entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
> +               if (!entry) {
> +                       ret = -ENOMEM;
> +                       goto err;
> +               }
> +
> +               entry->base = base;
> +               entry->offset = offset;
> +               entry->len = min_t(u32, len, MAX_DCC_LEN);
> +               entry->index = drvdata->nr_config[drvdata->curr_list]++;
> +               entry->desc_type = DCC_ADDR_TYPE;
> +               entry->apb_bus = apb_bus;
> +               INIT_LIST_HEAD(&entry->list);
> +               list_add_tail(&entry->list,
> +                       &drvdata->cfg_head[drvdata->curr_list]);
> +
> +               len -= entry->len;
> +               offset += MAX_DCC_LEN * 4;
> +       }
> +

err:

> +       mutex_unlock(&drvdata->mutex);
> +       return 0;

return ret;

> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return ret;

Remove these three lines.

> +}
> +
> +static ssize_t config_store(struct device *dev,
> +                               struct device_attribute *attr,
> +                               const char *buf, size_t size)
> +{
> +       int ret, len, apb_bus;
> +       unsigned int base;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +       int nval;
> +
> +       nval = sscanf(buf, "%x %i %d", &base, &len, &apb_bus);
> +       if (nval <= 0 || nval > 3)
> +               return -EINVAL;
> +
> +       if (nval == 1) {
> +               len = 1;
> +               apb_bus = 0;
> +       } else if (nval == 2) {
> +               apb_bus = 0;
> +       } else {
> +               apb_bus = 1;
> +       }
> +
> +       ret = dcc_config_add(drvdata, base, len, apb_bus);
> +       if (ret)
> +               return ret;
> +
> +       return size;
> +
> +}
> +
> +static DEVICE_ATTR_RW(config);
> +
> +static void dcc_config_reset(struct dcc_drvdata *drvdata)
> +{
> +       struct dcc_config_entry *entry, *temp;
> +       int curr_list;
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
> +               list_for_each_entry_safe(entry, temp,
> +                       &drvdata->cfg_head[curr_list], list) {
> +                       list_del(&entry->list);
> +                       devm_kfree(drvdata->dev, entry);
> +                       drvdata->nr_config[curr_list]--;
> +               }
> +       }
> +       drvdata->ram_start = 0;
> +       drvdata->ram_cfg = 0;
> +       mutex_unlock(&drvdata->mutex);
> +}
> +
> +
> +static ssize_t config_reset_store(struct device *dev,
> +       struct device_attribute *attr,
> +       const char *buf, size_t size)
> +{
> +       unsigned long val;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       if (kstrtoul(buf, 16, &val))
> +               return -EINVAL;
> +
> +       if (val)
> +               dcc_config_reset(drvdata);
> +
> +       return size;
> +}
> +
> +static DEVICE_ATTR_WO(config_reset);
> +
> +static ssize_t ready_show(struct device *dev,
> +       struct device_attribute *attr, char *buf)
> +{
> +       int ret;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> +               dev_err(dev, "Select link list to program using curr_list\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       if (!drvdata->enable[drvdata->curr_list]) {
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       ret = scnprintf(buf, PAGE_SIZE, "%u\n",
> +                       (unsigned int)FIELD_GET(BIT(1), dcc_readl(drvdata, DCC_STATUS)));
> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return ret;
> +}
> +
> +static DEVICE_ATTR_RO(ready);
> +
> +static ssize_t interrupt_disable_show(struct device *dev,
> +                                               struct device_attribute *attr,
> +                                               char *buf)
> +{
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       return scnprintf(buf, PAGE_SIZE, "%u\n",
> +                               (unsigned int)drvdata->interrupt_disable);
> +}
> +
> +static ssize_t interrupt_disable_store(struct device *dev,
> +       struct device_attribute *attr,
> +       const char *buf, size_t size)
> +{
> +       unsigned long val;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       if (kstrtoul(buf, 16, &val))
> +               return -EINVAL;
> +
> +       mutex_lock(&drvdata->mutex);
> +       drvdata->interrupt_disable = (val ? 1:0);
> +       mutex_unlock(&drvdata->mutex);
> +       return size;
> +}
> +
> +static DEVICE_ATTR_RW(interrupt_disable);
> +
> +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt)
> +{
> +       struct dcc_config_entry *entry;
> +
> +       entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
> +       if (!entry)
> +               return -ENOMEM;
> +
> +       entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT);
> +       entry->index = drvdata->nr_config[drvdata->curr_list]++;
> +       entry->desc_type = DCC_LOOP_TYPE;
> +       INIT_LIST_HEAD(&entry->list);
> +       list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
> +
> +       return 0;
> +}
> +
> +static ssize_t loop_store(struct device *dev,
> +       struct device_attribute *attr,
> +       const char *buf, size_t size)
> +{
> +       int ret;
> +       unsigned long loop_cnt;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       if (kstrtoul(buf, 16, &loop_cnt)) {
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> +               dev_err(dev, "Select link list to program using curr_list\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       ret = dcc_add_loop(drvdata, loop_cnt);
> +       if (ret)
> +               goto err;
> +
> +       mutex_unlock(&drvdata->mutex);
> +       return size;
> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return ret;
> +}
> +
> +static DEVICE_ATTR_WO(loop);
> +
> +static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask,
> +                               unsigned int val)
> +{
> +       int ret = 0;
> +       struct dcc_config_entry *entry;
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> +               dev_err(drvdata->dev, "Select link list to program using curr_list\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       if (list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
> +               dev_err(drvdata->dev, "DCC: No read address programmed\n");
> +               ret = -EPERM;
> +               goto err;
> +       }
> +
> +       entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
> +       if (!entry) {
> +               ret = -ENOMEM;
> +               goto err;
> +       }
> +
> +       entry->desc_type = DCC_READ_WRITE_TYPE;
> +       entry->mask = mask;
> +       entry->write_val = val;
> +       entry->index = drvdata->nr_config[drvdata->curr_list]++;
> +       INIT_LIST_HEAD(&entry->list);
> +       list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return ret;
> +}
> +
> +static ssize_t rd_mod_wr_store(struct device *dev,
> +       struct device_attribute *attr,
> +       const char *buf, size_t size)
> +{
> +       int ret;
> +       int nval;
> +       unsigned int mask, val;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       nval = sscanf(buf, "%x %x", &mask, &val);
> +
> +       if (nval <= 1 || nval > 2)
> +               return -EINVAL;
> +
> +       ret = dcc_rd_mod_wr_add(drvdata, mask, val);
> +       if (ret)
> +               return ret;
> +
> +       return size;
> +
> +}
> +
> +static DEVICE_ATTR_WO(rd_mod_wr);
> +
> +static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr,
> +                               unsigned int write_val, int apb_bus)
> +{
> +       struct dcc_config_entry *entry;
> +
> +       entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
> +       if (!entry)
> +               return -ENOMEM;
> +
> +       entry->desc_type = DCC_WRITE_TYPE;
> +       entry->base = addr & GENMASK(31, 4);
> +       entry->offset = addr - entry->base;
> +       entry->write_val = write_val;
> +       entry->index = drvdata->nr_config[drvdata->curr_list]++;
> +       entry->len = 1;
> +       entry->apb_bus = apb_bus;
> +       INIT_LIST_HEAD(&entry->list);
> +       list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
> +
> +       return 0;
> +}
> +
> +static ssize_t config_write_store(struct device *dev,
> +                                               struct device_attribute *attr,
> +                                               const char *buf, size_t size)
> +{
> +       int ret;
> +       int nval;
> +       unsigned int addr, write_val;
> +       int apb_bus = 0;
> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> +       mutex_lock(&drvdata->mutex);
> +
> +       nval = sscanf(buf, "%x %x %d", &addr, &write_val, &apb_bus);
> +
> +       if (nval <= 1 || nval > 3) {
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> +               dev_err(dev, "Select link list to program using curr_list\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       if (nval == 3 && apb_bus != 0)
> +               apb_bus = 1;
> +
> +       ret = dcc_add_write(drvdata, addr, write_val, apb_bus);
> +       if (ret)
> +               goto err;
> +
> +       mutex_unlock(&drvdata->mutex);
> +       return size;
> +err:
> +       mutex_unlock(&drvdata->mutex);
> +       return ret;
> +}
> +
> +static DEVICE_ATTR_WO(config_write);
> +
> +static const struct device_attribute *dcc_attrs[] = {
> +       &dev_attr_trigger,
> +       &dev_attr_enable,
> +       &dev_attr_config,
> +       &dev_attr_config_reset,
> +       &dev_attr_ready,
> +       &dev_attr_interrupt_disable,
> +       &dev_attr_loop,
> +       &dev_attr_rd_mod_wr,
> +       &dev_attr_curr_list,
> +       &dev_attr_config_write,
> +       NULL,
> +};
> +
> +static int dcc_create_files(struct device *dev,
> +                                       const struct device_attribute **attrs)
> +{
> +       int ret = 0, i;
> +
> +       for (i = 0; attrs[i] != NULL; i++) {
> +               ret = device_create_file(dev, attrs[i]);
> +               if (ret) {
> +                       dev_err(dev, "DCC: Couldn't create sysfs attribute: %s\n",
> +                               attrs[i]->attr.name);
> +                       break;
> +               }
> +       }
> +       return ret;
> +}
> +
> +static int dcc_sram_open(struct inode *inode, struct file *file)
> +{
> +       struct dcc_drvdata *drvdata = container_of(inode->i_cdev,
> +               struct dcc_drvdata,
> +               sram_dev);
> +       file->private_data = drvdata;
> +
> +       return  0;
> +}
> +
> +static ssize_t dcc_sram_read(struct file *file, char __user *data,
> +                                               size_t len, loff_t *ppos)
> +{
> +       unsigned char *buf;
> +       struct dcc_drvdata *drvdata = file->private_data;

const?

> +
> +       /* EOF check */
> +       if (drvdata->ram_size <= *ppos)
> +               return 0;
> +
> +       if ((*ppos + len) > drvdata->ram_size)
> +               len = (drvdata->ram_size - *ppos);
> +
> +       buf = kzalloc(len, GFP_KERNEL);
> +       if (!buf)
> +               return -ENOMEM;
> +
> +       memcpy_fromio(buf, drvdata->ram_base + *ppos, len);
> +
> +       if (copy_to_user(data, buf, len)) {

Is there any sort of memcpy_fromio_to_user() API? That would avoid the
extra buffer allocation by copying to userspace in the readl loop.

> +               dev_err(drvdata->dev, "DCC: Couldn't copy all data to user\n");

I think we don't want this sort of error message in userspace
triggerable copy operations.

> +               kfree(buf);
> +               return -EFAULT;
> +       }
> +
> +       *ppos += len;
> +
> +       kfree(buf);
> +
> +       return len;
> +}
> +
> +static const struct file_operations dcc_sram_fops = {
> +       .owner          = THIS_MODULE,
> +       .open           = dcc_sram_open,
> +       .read           = dcc_sram_read,
> +       .llseek         = no_llseek,
> +};
> +
> +static int dcc_sram_dev_register(struct dcc_drvdata *drvdata)
> +{
> +       int ret;
> +       struct device *device;
> +       dev_t dev;
> +
> +       ret = alloc_chrdev_region(&dev, 0, 1, drvdata->sram_node);
> +       if (ret)
> +               goto err_alloc;
> +
> +       cdev_init(&drvdata->sram_dev, &dcc_sram_fops);
> +
> +       drvdata->sram_dev.owner = THIS_MODULE;
> +       ret = cdev_add(&drvdata->sram_dev, dev, 1);
> +       if (ret)
> +               goto err_cdev_add;
> +
> +       drvdata->sram_class = class_create(THIS_MODULE, drvdata->sram_node);
> +       if (IS_ERR(drvdata->sram_class)) {
> +               ret = PTR_ERR(drvdata->sram_class);
> +               goto err_class_create;
> +       }
> +
> +       device = device_create(drvdata->sram_class, NULL,
> +                                               drvdata->sram_dev.dev, drvdata,
> +                                               drvdata->sram_node);
> +       if (IS_ERR(device)) {
> +               ret = PTR_ERR(device);
> +               goto err_dev_create;
> +       }
> +
> +       return 0;
> +err_dev_create:
> +       class_destroy(drvdata->sram_class);
> +err_class_create:
> +       cdev_del(&drvdata->sram_dev);
> +err_cdev_add:
> +       unregister_chrdev_region(drvdata->sram_dev.dev, 1);
> +err_alloc:
> +       return ret;
> +}
> +
> +static void dcc_sram_dev_deregister(struct dcc_drvdata *drvdata)
> +{
> +       device_destroy(drvdata->sram_class, drvdata->sram_dev.dev);
> +       class_destroy(drvdata->sram_class);
> +       cdev_del(&drvdata->sram_dev);
> +       unregister_chrdev_region(drvdata->sram_dev.dev, 1);
> +}
> +
> +static int dcc_sram_dev_init(struct dcc_drvdata *drvdata)
> +{
> +       int ret = 0;
> +
> +       drvdata->sram_node = DCC_SRAM_NODE;
> +       if (!drvdata->sram_node)
> +               return -ENOMEM;
> +
> +       ret = dcc_sram_dev_register(drvdata);
> +       if (ret)
> +               dev_err(drvdata->dev, "DCC: sram node not registered.\n");
> +
> +       return ret;
> +}
> +
> +static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata)
> +{
> +       dcc_sram_dev_deregister(drvdata);
> +}
> +
> +static int dcc_probe(struct platform_device *pdev)
> +{
> +       int ret = 0, i;
> +       struct device *dev = &pdev->dev;
> +       struct dcc_drvdata *dcc;
> +       struct resource *res;
> +       const struct qcom_dcc_config *cfg;
> +
> +       dcc = devm_kzalloc(dev, sizeof(*dcc), GFP_KERNEL);
> +       if (!dcc)
> +               return -ENOMEM;
> +
> +       dcc->dev = &pdev->dev;
> +       platform_set_drvdata(pdev, dcc);
> +
> +       dcc->base = devm_platform_ioremap_resource_byname(pdev, "dcc");
> +       if (!dcc->base)
> +               return -ENOMEM;
> +
> +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dcc-ram");
> +       if (!res)
> +               return -EINVAL;
> +
> +       dcc->ram_size = resource_size(res);
> +
> +       dcc->ram_base = devm_ioremap(dev, res->start, resource_size(res));
> +       if (!dcc->ram_base)
> +               return -ENOMEM;

How about

	dcc->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(dcc->base))
		return PTR_ERR(dcc->base);

	dcc->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
	if (IS_ERR(dcc->ram_base))
		return PTR_ERR(dcc->ram_base);

	dcc->ram_size = resource_size(res);

> +
> +       cfg = of_device_get_match_data(&pdev->dev);

	if (!cfg)
		return -EINVAL;


> +       dcc->ram_offset = cfg->dcc_ram_offset;
> +
> +       if (FIELD_GET(BIT(DCC_VER_INFO_BIT), dcc_readl(dcc, DCC_HW_INFO))) {
> +               dcc->mem_map_ver = DCC_MEM_MAP_VER3;
> +               dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
> +               if (dcc->nr_link_list == 0)
> +                       return  -EINVAL;
> +       } else if ((dcc_readl(dcc, DCC_HW_INFO) & DCC_VER_MASK2) == DCC_VER_MASK2) {

Can we u32 val = dcc_readl(dcc, DCC_HW_INFO) once instead of twice?

> +               dcc->mem_map_ver = DCC_MEM_MAP_VER2;
> +               dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
> +               if (dcc->nr_link_list == 0)
> +                       return  -EINVAL;
> +       } else {
> +               dcc->mem_map_ver = DCC_MEM_MAP_VER1;
> +               dcc->nr_link_list = DCC_MAX_LINK_LIST;
> +       }
> +
> +       if ((dcc_readl(dcc, DCC_HW_INFO) & BIT(6)) == BIT(6))

Err thrice.

> +               dcc->loopoff = DCC_FIX_LOOP_OFFSET;
> +       else
> +               dcc->loopoff = get_bitmask_order((dcc->ram_size +
> +                               dcc->ram_offset) / 4 - 1);
> +
> +       mutex_init(&dcc->mutex);
> +       dcc->enable = devm_kcalloc(dev, dcc->nr_link_list,
> +                       sizeof(bool), GFP_KERNEL);
> +       if (!dcc->enable)
> +               return -ENOMEM;
> +
> +       dcc->configured = devm_kcalloc(dev, dcc->nr_link_list,
> +                       sizeof(bool), GFP_KERNEL);
> +       if (!dcc->configured)
> +               return -ENOMEM;
> +
> +       dcc->nr_config = devm_kcalloc(dev, dcc->nr_link_list,
> +                       sizeof(u32), GFP_KERNEL);
> +       if (!dcc->nr_config)
> +               return -ENOMEM;
> +
> +       dcc->cfg_head = devm_kcalloc(dev, dcc->nr_link_list,
> +                       sizeof(struct list_head), GFP_KERNEL);
> +       if (!dcc->cfg_head)
> +               return -ENOMEM;

These are a lot of allocations. Any chance we can do one instead of this
many?

> +
> +       for (i = 0; i < dcc->nr_link_list; i++)
> +               INIT_LIST_HEAD(&dcc->cfg_head[i]);
> +
> +

Drop double newline?

> +       memset_io(dcc->ram_base, 0, dcc->ram_size);
> +       dcc->curr_list = DCC_INVALID_LINK_LIST;
> +       ret = dcc_sram_dev_init(dcc);
> +       if (ret)
> +               goto out;

		return ret;

> +
> +       ret = dcc_create_files(dev, dcc_attrs);
> +       if (ret)
> +               goto out;
> +
> +out:
> +       return ret;

Just

	return dcc_create_files(...)

> +}
> +
> +static int dcc_remove(struct platform_device *pdev)
> +{
> +       struct dcc_drvdata *drvdata = platform_get_drvdata(pdev);
> +
> +       dcc_sram_dev_exit(drvdata);
> +
> +       dcc_config_reset(drvdata);
> +
> +       return 0;
> +}
> +
> +static const struct qcom_dcc_config sm8150_cfg = {
> +       .dcc_ram_offset = 0x5000,
> +};
> +
> +static const struct of_device_id dcc_match_table[] = {
> +       { .compatible = "qcom,sm8150-dcc", .data = &sm8150_cfg },

Missing a {} terminator.

> +};
> +MODULE_DEVICE_TABLE(of, dcc_match_table);
> +
> +static struct platform_driver dcc_driver = {
> +       .probe                                  = dcc_probe,
> +       .remove                                 = dcc_remove,
> +       .driver                                 = {

This tabbing is very odd. I'd expect

> +static struct platform_driver dcc_driver = {
> +       .probe   = dcc_probe,
> +       .remove  = dcc_remove,
> +       .driver  = {

that (ignoring spaces instead of tabs)

> +               .name           = "qcom-dcc",
> +               .of_match_table = dcc_match_table,
> +       },
> +};
> +
> +module_platform_driver(dcc_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver");
> +

Re: [PATCH V2 3/5] DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver

[Stephen Boyd]

Quoting Souradeep Chowdhury (2021-03-25 01:02:34)
> The DCC is a DMA engine designed to store register values either in
> case of a system crash or in case of software triggers manually done
> by the user.Using DCC hardware and the sysfs interface of the driver
> the user can exploit various functionalities of DCC.The user can specify
> the register addresses,the values of which is stored by DCC in it's
> dedicated SRAM.The register addresses can be used either to read from,
> write to,first read and store value and then write or to loop.All these
> options can be exploited using the sysfs interface given to the user.
> Following are the sysfs interfaces exposed in DCC driver which are
> documented
> 1)trigger
> 2)config
> 3)config_write
> 4)config_reset
> 5)enable
> 6)rd_mod_wr
> 7)loop
> 
> Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
> ---
>  Documentation/ABI/testing/sysfs-driver-dcc | 114 +++++++++++++++++++++++++++++

Please combine this with the driver patch.

>  1 file changed, 114 insertions(+)
>  create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc

Perhaps this should be an ioctl interface instead of a sysfs interface?

> 
> diff --git a/Documentation/ABI/testing/sysfs-driver-dcc b/Documentation/ABI/testing/sysfs-driver-dcc
> new file mode 100644
> index 0000000..05d24f0
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-dcc
> @@ -0,0 +1,114 @@
> +What:           /sys/bus/platform/devices/.../trigger
> +Date:           March 2021
> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
> +Description:
> +               This is the sysfs interface for manual software
> +               triggers.The user can simply enter a 1 against
> +               the sysfs file and enable a manual trigger.
> +               Example:
> +               echo  1 > /sys/bus/platform/devices/.../trigger
> +
> +What:           /sys/bus/platform/devices/.../enable
> +Date:           March 2021
> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
> +Description:
> +               This sysfs interface is used for enabling the
> +               the dcc hardware.Without this being set to 1,

Space after period please.

> +               the dcc hardware ceases to function.
> +               Example:
> +               echo  0 > /sys/bus/platform/devices/.../enable
> +               (disable interface)
> +               echo  1 > /sys/bus/platform/devices/.../enable
> +               (enable interface)
> +
> +What:           /sys/bus/platform/devices/.../config
> +Date:           March 2021
> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
> +Description:
> +               This is the most commonly used sysfs interface
> +               file and this basically stores the addresses of
> +               the registers which needs to be read in case of
> +               a hardware crash or manual software triggers.
> +               Example:
> +               echo  0x80000010 10 > /sys/bus/platform/devices/../config
> +               This specifies that 10 words starting from address
> +               0x80000010 is to be read.In case there are no words to be
> +               specified we can simply enter the address.
> +
> +What:           /sys/bus/platform/devices/.../config_write
> +Date:           March 2021
> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
> +Description:
> +               This file allows user to write a value to the register
> +               address given as argument.The values are entered in the
> +               form of <register_address> <value>.The reason for this
> +               feature of dcc is that for accessing certain registers
> +               it is necessary to set some bits of soe other register.

s/soe/some/?

> +               That is achievable by giving DCC this privelege.

s/privelege/privilege/

> +               Example:
> +               echo 0x80000000 0xFF > /sys/bus/platform/devices/.../config_write
> +
> +What:           /sys/bus/platform/devices/.../config_reset
> +Date:           March 2021
> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
> +Description:
> +               This file is used to reset the configuration of
> +               a dcc driver to the default configuration.
> +               Example:
> +               echo  1 > /sys/bus/platform/devices/.../config_reset
> +

Re: [PATCH V2 1/5] dt-bindings: Added the yaml bindings for DCC

[schowdhu]

On 2021-03-30 01:04, Stephen Boyd wrote:
> Quoting Souradeep Chowdhury (2021-03-25 01:02:32)
>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml 
>> b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
>> new file mode 100644
>> index 0000000..c6e0a9c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
>> @@ -0,0 +1,49 @@
>> +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Data Capture and Compare
>> +
>> +maintainers:
>> +  - Souradeep Chowdhury <schowdhu@codeaurora.org>
>> +
>> +description: |
>> +    DCC (Data Capture and Compare) is a DMA engine which is used to 
>> save
>> +    configuration data or system memory contents during catastrophic 
>> failure
>> +    or SW trigger.DCC is used to capture and store data for debugging 
>> purpose
> 
> Add space between trigger. and DCC?

Ack

> 
>> +
>> +
> 
> Drop double newline?

Ack

> 
>> +properties:
>> +  compatible:
>> +    items:
>> +      - enum:
>> +          - qcom,sm8150-dcc
>> +      - const: qcom,dcc
>> +
>> +  reg:
>> +    items:
>> +      - description: DCC base register region
>> +      - description: DCC RAM base register region
>> +
>> +  reg-names:
>> +    items:
>> +      - const: dcc
>> +      - const: dcc-ram
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
> 
> Do we really need reg names? Seems like we can assume the ordering.

Ack

> 
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    dcc@10a2000{
> 
> dma@10a2000? Or debug@10a2000?

Ack

> 
>> +                compatible = "qcom,sm8150-dcc","qcom,dcc";
>> +                reg = <0x010a2000  0x1000>,
>> +                      <0x010ad000  0x2000>;
>> +                reg-names = "dcc", "dcc-ram";
>> +    };

Re: [PATCH V2 2/5] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)

[schowdhu]

On 2021-03-30 01:35, Stephen Boyd wrote:
> Quoting Souradeep Chowdhury (2021-03-25 01:02:33)
>> The DCC is a DMA Engine designed to capture and store data
>> during system crash or software triggers.The DCC operates
>> based on user inputs via the sysfs interface.The user gives
>> addresses as inputs and these addresses are stored in the
>> form of linkedlists.In case of a system crash or a manual
>> software trigger by the user through the sysfs interface,
>> the dcc captures and stores the values at these addresses.
>> This patch contains the driver which has all the methods
>> pertaining to the sysfs interface, auxiliary functions to
>> support all the four fundamental operations of dcc namely
>> read, write, first read then write and loop.The probe method
>> here instantiates all the resources necessary for dcc to
>> operate mainly the dedicated dcc sram where it stores the
>> values.The DCC driver can be used for debugging purposes
>> without going for a reboot since it can perform manual
>> triggers.
>> 
>> Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
>> ---
>>  drivers/soc/qcom/Kconfig  |    8 +
>>  drivers/soc/qcom/Makefile |    1 +
>>  drivers/soc/qcom/dcc.c    | 1549 
>> +++++++++++++++++++++++++++++++++++++++++++++
> 
> Where's the document for various sysfs attributes in Documentation/ABI?

Will combine the sysfs document with the driver patch as suggested.

> 
>>  3 files changed, 1558 insertions(+)
>>  create mode 100644 drivers/soc/qcom/dcc.c
>> 
>> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
>> index 79b568f..8819e0b 100644
>> --- a/drivers/soc/qcom/Kconfig
>> +++ b/drivers/soc/qcom/Kconfig
>> @@ -69,6 +69,14 @@ config QCOM_LLCC
>>           SDM845. This provides interfaces to clients that use the 
>> LLCC.
>>           Say yes here to enable LLCC slice driver.
>> 
>> +config QCOM_DCC
>> +       tristate "Qualcomm Technologies, Inc. Data Capture and Compare 
>> engine driver"
> 
> Put (DCC) after Compare?

Ack

> 
>> +       depends on ARCH_QCOM || COMPILE_TEST
>> +       help
>> +         This option enables driver for Data Capture and Compare 
>> engine. DCC
>> +         driver provides interface to configure DCC block and read 
>> back
>> +         captured data from DCC's internal SRAM.
>> +
>>  config QCOM_KRYO_L2_ACCESSORS
>>         bool
>>         depends on ARCH_QCOM && ARM64 || COMPILE_TEST
>> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
>> index ad675a6..1b00870 100644
>> --- a/drivers/soc/qcom/Makefile
>> +++ b/drivers/soc/qcom/Makefile
>> @@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
>>  obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
>>  obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
>>  obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=        kryo-l2-accessors.o
>> +obj-$(CONFIG_QCOM_DCC) += dcc.o
> 
> Can this be sorted based on config or file name instead of adding to 
> the
> end of the file and leading to endless conflicts?

Ack

> 
>> diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c
>> new file mode 100644
>> index 0000000..a55d8ca7
>> --- /dev/null
>> +++ b/drivers/soc/qcom/dcc.c
>> @@ -0,0 +1,1549 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2015-2021, The Linux Foundation. All rights 
>> reserved.
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/bitops.h>
>> +#include <linux/cdev.h>
>> +#include <linux/delay.h>
>> +#include <linux/fs.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +#include <linux/uaccess.h>
>> +
>> +
>> +#define TIMEOUT_US             100
>> +
>> +#define dcc_writel(drvdata, val, off)                                 
>>  \
>> +       writel((val), drvdata->base + dcc_offset_conv(drvdata, off))
>> +#define dcc_readl(drvdata, off)                                       
>>          \
>> +       readl(drvdata->base + dcc_offset_conv(drvdata, off))
>> +
>> +#define dcc_sram_readl(drvdata, off)                                  
>>  \
>> +       readl(drvdata->ram_base + off)
>> +
>> +#define DCC_SRAM_NODE "dcc_sram"
>> +
>> +/* DCC registers */
>> +#define DCC_HW_INFO                    0x04
>> +#define DCC_LL_NUM_INFO                        0x10
>> +#define DCC_STATUS                     0x1C
>> +#define DCC_LL_LOCK(m)                 (0x34 + 0x80 * m)
>> +#define DCC_LL_CFG(m)                  (0x38 + 0x80 * m)
>> +#define DCC_LL_BASE(m)                 (0x3c + 0x80 * m)
>> +#define DCC_FD_BASE(m)                 (0x40 + 0x80 * m)
>> +#define DCC_LL_TIMEOUT(m)              (0x44 + 0x80 * m)
>> +#define DCC_LL_INT_ENABLE(m)           (0x4C + 0x80 * m)
>> +#define DCC_LL_INT_STATUS(m)           (0x50 + 0x80 * m)
>> +#define DCC_LL_SW_TRIGGER(m)           (0x60 + 0x80 * m)
>> +#define DCC_LL_BUS_ACCESS_STATUS(m)    (0x64 + 0x80 * m)
>> +
>> +#define DCC_MAP_LEVEL1                 0x18
>> +#define DCC_MAP_LEVEL2                 0x34
>> +#define DCC_MAP_LEVEL3                 0x4C
>> +
>> +#define DCC_MAP_OFFSET1                        0x10
>> +#define DCC_MAP_OFFSET2                        0x18
>> +#define DCC_MAP_OFFSET3                        0x1C
>> +#define DCC_MAP_OFFSET4                        0x8
>> +
>> +#define DCC_FIX_LOOP_OFFSET            16
>> +#define DCC_VER_INFO_BIT               9
>> +
>> +#define DCC_READ                       0
>> +#define DCC_WRITE                      1
>> +#define DCC_LOOP                       2
>> +#define DCC_READ_WRITE                 3
>> +
>> +#define MAX_DCC_OFFSET                 GENMASK(9, 2)
>> +#define MAX_DCC_LEN                    GENMASK(6, 0)
>> +#define MAX_LOOP_CNT                   GENMASK(7, 0)
>> +
>> +#define DCC_ADDR_DESCRIPTOR            0x00
>> +#define DCC_LOOP_DESCRIPTOR            BIT(30)
>> +#define DCC_RD_MOD_WR_DESCRIPTOR       BIT(31)
>> +#define DCC_LINK_DESCRIPTOR            GENMASK(31, 30)
>> +
>> +#define DCC_READ_IND                   0x00
>> +#define DCC_WRITE_IND                  (BIT(28))
>> +
>> +#define DCC_AHB_IND                    0x00
>> +#define DCC_APB_IND                    BIT(29)
>> +
>> +#define DCC_MAX_LINK_LIST              8
>> +#define DCC_INVALID_LINK_LIST          GENMASK(7, 0)
>> +
>> +#define DCC_VER_MASK1                  GENMASK(6, 0)
>> +#define DCC_VER_MASK2                  GENMASK(5, 0)
>> +
>> +#define DCC_RD_MOD_WR_ADDR              0xC105E
>> +
>> +struct qcom_dcc_config {
>> +       const int dcc_ram_offset;
> 
> Why const here? The container structure can be const and then this is
> easier to read.

Ack

> 
>> +};
>> +
>> +enum dcc_descriptor_type {
>> +       DCC_ADDR_TYPE,
>> +       DCC_LOOP_TYPE,
>> +       DCC_READ_WRITE_TYPE,
>> +       DCC_WRITE_TYPE
>> +};
>> +
>> +enum dcc_mem_map_ver {
>> +       DCC_MEM_MAP_VER1 = 1,
>> +       DCC_MEM_MAP_VER2 = 2,
>> +       DCC_MEM_MAP_VER3 = 3
>> +};
>> +
>> +struct dcc_config_entry {
>> +       u32                             base;
>> +       u32                             offset;
>> +       u32                             len;
>> +       u32                             index;
>> +       u32                             loop_cnt;
>> +       u32                             write_val;
>> +       u32                             mask;
>> +       bool                            apb_bus;
>> +       enum dcc_descriptor_type        desc_type;
>> +       struct list_head                list;
>> +};
>> +
>> +struct dcc_drvdata {
> 
> Can we get some kernel doc on this structure?

Ack.

> 
>> +       void __iomem            *base;
>> +       u32                     reg_size;
>> +       struct device           *dev;
>> +       struct mutex            mutex;
> 
> In particular what this mutex is protecting.

Ack. The mutex is used to protect the access as well as manipulation of 
the main instance of dcc_drvdata structure
initialized during probe time. This structure contains the useful driver 
data information and is set using the call
platform_set_drvdata(pdev, drvdata) which links this data to the 
platform device and hence needs to be protected via
mutex locks. The same convention is followed across other similar 
drivers exposing userspace like the llcc driver.

> 
>> +       void __iomem            *ram_base;
>> +       u32                     ram_size;
>> +       u32                     ram_offset;
>> +       enum dcc_mem_map_ver    mem_map_ver;
>> +       u32                     ram_cfg;
>> +       u32                     ram_start;
> 
> phys_addr_t?

Ack

> 
>> +       bool                    *enable;
>> +       bool                    *configured;
>> +       bool                    interrupt_disable;
>> +       char                    *sram_node;
> 
> This is always a define, so why make a struct member?

Ack

> 
>> +       struct cdev             sram_dev;
>> +       struct class            *sram_class;
>> +       struct list_head        *cfg_head;
>> +       u32                     *nr_config;
>> +       u32                     nr_link_list;
> 
> size_t?

Ack

> 
>> +       u8                      curr_list;
>> +       u8                      loopoff;
>> +};
>> +
>> +struct dcc_cfg_attr {
>> +       u32     addr;
>> +       u32     prev_addr;
>> +       u32     prev_off;
>> +       u32     link;
>> +       u32     sram_offset;
>> +};
>> +
>> +struct dcc_cfg_loop_attr {
>> +       u32     loop;
>> +       bool    loop_start;
>> +       u32     loop_cnt;
>> +       u32     loop_len;
>> +       u32     loop_off;
>> +};
>> +
>> +static size_t dcc_offset_conv(struct dcc_drvdata *drvdata, size_t 
>> off)
>> +{
>> +       if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) {
>> +               if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL3)
>> +                       return (off - DCC_MAP_OFFSET3);
> 
> Drop useless parenthesis please.

Ack

> 
>> +               if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
>> +                       return (off - DCC_MAP_OFFSET2);
> 
> Drop useless parenthesis please.

Ack

> 
>> +               else if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL1)
>> +                       return (off - DCC_MAP_OFFSET1);
> 
> Drop useless parenthesis please.

Ack

> 
>> +       } else if (drvdata->mem_map_ver == DCC_MEM_MAP_VER2) {
>> +               if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
>> +                       return (off - DCC_MAP_OFFSET4);
> 
> Drop useless parenthesis please.

Ack

> 
>> +       }
> 
> Newline please.

Ack

> 
>> +       return off;
>> +}
>> +
>> +static int dcc_sram_writel(struct dcc_drvdata *drvdata,
>> +                                       u32 val, u32 off)
>> +{
>> +       if (unlikely(off > (drvdata->ram_size - 4)))
>> +               return -EINVAL;
> 
> Can this be pushed up one level? It would be great if we didn't have to
> track the fact that we've gone off the end of the ram in each writel
> call, instead doing something for every word in the ram and stopping
> that loop higher up.

Ack

> 
>> +
>> +       writel((val), drvdata->ram_base + off);
> 
> Drop useless parenthesis please.

Ack

> 
>> +
>> +       return 0;
>> +}
>> +
>> +static bool dcc_ready(struct dcc_drvdata *drvdata)
>> +{
>> +       u32 val;
>> +
>> +       /* poll until DCC ready */
> 
> Drop useless comment please.

Ack

> 
>> +       if (!readl_poll_timeout((drvdata->base + DCC_STATUS), val,
>> +                               (FIELD_GET(GENMASK(1, 0), val) == 0), 
>> 1, TIMEOUT_US))
>> +               return true;
>> +
>> +       return false;
> 
> return !readl_poll_timeout(...) instead?

Ack.

> 
>> +}
>> +
>> +static int dcc_read_status(struct dcc_drvdata *drvdata)
>> +{
>> +       int curr_list;
>> +       u32 bus_status;
>> +       u32 ll_cfg = 0;
>> +       u32 tmp_ll_cfg = 0;
> 
> Drop assignments as they're overwritten.

Ack

> 
>> +
>> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; 
>> curr_list++) {
>> +               if (!drvdata->enable[curr_list])
>> +                       continue;
>> +
>> +               bus_status = dcc_readl(drvdata, 
>> DCC_LL_BUS_ACCESS_STATUS(curr_list));
>> +
>> +               if (bus_status) {
>> +                       dev_err(drvdata->dev,
>> +                               "Read access error for list %d err: 
>> 0x%x.\n",
>> +                               curr_list, bus_status);
>> +
>> +                       ll_cfg = dcc_readl(drvdata, 
>> DCC_LL_CFG(curr_list));
>> +                       tmp_ll_cfg = ll_cfg & ~BIT(9);
>> +                       dcc_writel(drvdata, tmp_ll_cfg, 
>> DCC_LL_CFG(curr_list));
>> +                       dcc_writel(drvdata, 0x3,
>> +                               DCC_LL_BUS_ACCESS_STATUS(curr_list));
>> +                       dcc_writel(drvdata, ll_cfg, 
>> DCC_LL_CFG(curr_list));
>> +                       return -ENODATA;
>> +               }
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static int dcc_sw_trigger(struct dcc_drvdata *drvdata)
>> +{
>> +       int ret = 0;
>> +       int curr_list;
>> +       u32 ll_cfg = 0;
>> +       u32 tmp_ll_cfg = 0;
> 
> Drop assignments as they're overwritten.

Ack

> 
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; 
>> curr_list++) {
>> +               if (!drvdata->enable[curr_list])
>> +                       continue;
>> +               ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
>> +               tmp_ll_cfg = ll_cfg & ~BIT(9);
>> +               dcc_writel(drvdata, tmp_ll_cfg, 
>> DCC_LL_CFG(curr_list));
>> +               dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
>> +               dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
>> +       }
> 
> Does the mutex need to be held while waiting for ready?

Yes, to maintain consistency because inside the dcc_ready function, 
there is access to dcc_drvdata structure set
on the platform device.

> 
>> +
>> +       if (!dcc_ready(drvdata)) {
>> +               dev_err(drvdata->dev,
>> +                       "DCC is busy after receiving sw tigger.\n");
>> +               ret = -EBUSY;
>> +               goto err;
>> +       }
>> +
>> +       ret = dcc_read_status(drvdata);
>> +
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return ret;
>> +}
>> +
>> +static void _dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg)
>> +{
>> +       cfg->addr = 0x00;
>> +       cfg->link = 0;
>> +       cfg->prev_off = 0;
>> +       cfg->prev_addr = cfg->addr;
>> +}
>> +
>> +static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata,
>> +                                 struct dcc_config_entry *entry,
>> +                                 struct dcc_cfg_attr *cfg)
>> +{
>> +       int ret;
>> +
>> +       if (cfg->link) {
>> +               /*
>> +                * write new offset = 1 to continue
>> +                * processing the list
>> +                */
>> +
>> +               ret = dcc_sram_writel(drvdata, cfg->link, 
>> cfg->sram_offset);
>> +               if (ret)
>> +                       return ret;
>> +               cfg->sram_offset += 4;
>> +               /* Reset link and prev_off */
>> +               _dcc_ll_cfg_reset_link(cfg);
>> +       }
>> +
>> +       cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR;
>> +       ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
>> +       if (ret)
>> +               return ret;
>> +
>> +       cfg->sram_offset += 4;
>> +       ret = dcc_sram_writel(drvdata, entry->mask, cfg->sram_offset);
>> +       if (ret)
>> +               return ret;
>> +
>> +       cfg->sram_offset += 4;
>> +       ret = dcc_sram_writel(drvdata, entry->write_val, 
>> cfg->sram_offset);
>> +       if (ret)
>> +               return ret;
>> +
>> +       cfg->sram_offset += 4;
>> +       cfg->addr = 0;
>> +       return ret;
>> +}
>> +
>> +static int _dcc_ll_cfg_loop(struct dcc_drvdata *drvdata, struct 
>> dcc_config_entry *entry,
>> +                           struct dcc_cfg_attr *cfg,
>> +                           struct dcc_cfg_loop_attr *cfg_loop,
>> +                           u32 *total_len)
>> +{
>> +
>> +       int ret;
>> +
>> +       /* Check if we need to write link of prev entry */
>> +       if (cfg->link) {
>> +               ret = dcc_sram_writel(drvdata, cfg->link, 
>> cfg->sram_offset);
>> +               if (ret)
>> +                       return ret;
>> +               cfg->sram_offset += 4;
>> +       }
>> +
>> +       if (cfg_loop->loop_start) {
>> +               cfg_loop->loop = (cfg->sram_offset - 
>> cfg_loop->loop_off) / 4;
>> +               cfg_loop->loop |= (cfg_loop->loop_cnt << 
>> drvdata->loopoff) &
>> +               GENMASK(27, drvdata->loopoff);
> 
> What is 27? Can it be a define?

Ack. The dcc hardware is designed such that the bits from 27 to 16 of 
the loop descriptor
are used for interpreting the loop value. This loop value is the counter 
which tell the dcc
hardware how many times it should loop across the configured register 
addresses. The details
for this is documented in sysfs descriptors.

> 
>> +               cfg_loop->loop |= DCC_LOOP_DESCRIPTOR;
>> +               *total_len += (*total_len - cfg_loop->loop_len) * 
>> cfg_loop->loop_cnt;
>> +
>> +               ret = dcc_sram_writel(drvdata, cfg_loop->loop, 
>> cfg->sram_offset);
>> +
> 
> Drop newline?

Ack

> 
>> +               if (ret)
>> +                       return ret;
>> +               cfg->sram_offset += 4;
>> +
>> +               cfg_loop->loop_start = false;
>> +               cfg_loop->loop_len = 0;
>> +               cfg_loop->loop_off = 0;
>> +       } else {
>> +               cfg_loop->loop_start = true;
>> +               cfg_loop->loop_cnt = entry->loop_cnt - 1;
>> +               cfg_loop->loop_len = *total_len;
>> +               cfg_loop->loop_off = cfg->sram_offset;
>> +       }
>> +
>> +       /* Reset link and prev_off */
>> +
> 
> Drop newline?

Ack

> 
>> +       _dcc_ll_cfg_reset_link(cfg);
>> +
>> +       return ret;
>> +}
>> +
>> +static int _dcc_ll_cfg_write(struct dcc_drvdata *drvdata,
>> +                            struct dcc_config_entry *entry,
>> +                            struct dcc_cfg_attr *cfg,
>> +                            u32 *total_len)
>> +{
>> +       u32 off;
>> +       int ret;
>> +
>> +       if (cfg->link) {
>> +               /*
>> +                * write new offset = 1 to continue
>> +                * processing the list
>> +                */
>> +               ret = dcc_sram_writel(drvdata, cfg->link, 
>> cfg->sram_offset);
>> +
>> +               if (ret)
>> +                       return ret;
>> +
>> +               cfg->sram_offset += 4;
>> +               /* Reset link and prev_off */
>> +               cfg->addr = 0x00;
>> +               cfg->prev_off = 0;
>> +               cfg->prev_addr = cfg->addr;
>> +       }
>> +
>> +       off = entry->offset/4;
>> +       /* write new offset-length pair to correct position */
>> +       cfg->link |= ((off & GENMASK(7, 0)) | BIT(15) | ((entry->len 
>> << 8) & GENMASK(14, 8)));
>> +       cfg->link |= DCC_LINK_DESCRIPTOR;
>> +
>> +       /* Address type */
>> +       cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
>> +       if (entry->apb_bus)
>> +               cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | 
>> DCC_APB_IND;
>> +       else
>> +               cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | 
>> DCC_AHB_IND;
>> +       ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
>> +
>> +       if (ret)
>> +               return ret;
>> +       cfg->sram_offset += 4;
>> +
>> +       ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
>> +       if (ret)
>> +               return ret;
>> +       cfg->sram_offset += 4;
>> +
>> +       ret = dcc_sram_writel(drvdata, entry->write_val, 
>> cfg->sram_offset);
>> +
>> +       if (ret)
>> +               return ret;
>> +
>> +       cfg->sram_offset += 4;
>> +       cfg->addr = 0x00;
>> +       cfg->link = 0;
>> +       return ret;
>> +}
>> +
>> +static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
>> +                              struct dcc_config_entry *entry,
>> +                              struct dcc_cfg_attr *cfg,
>> +                              u32 *pos, u32 *total_len)
>> +{
>> +       int ret;
>> +       u32 off;
>> +
>> +       cfg->addr = (entry->base >> 4) & GENMASK(27, 0);
> 
> There's 27 again!

Ack. In case of default descriptors, bits 27 to 0 is considered the 
address bits as per DCC hardware.
Will put a define for this as well.

> 
>> +
>> +       if (entry->apb_bus)
>> +               cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | 
>> DCC_APB_IND;
>> +       else
>> +               cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | 
>> DCC_AHB_IND;
>> +
>> +       off = entry->offset/4;
>> +
>> +       *total_len += entry->len * 4;
>> +
>> +       if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || 
>> cfg->prev_off > off) {
>> +               /* Check if we need to write prev link entry */
>> +               if (cfg->link) {
>> +                       ret = dcc_sram_writel(drvdata, cfg->link, 
>> cfg->sram_offset);
>> +                       if (ret)
>> +                               return ret;
>> +                       cfg->sram_offset += 4;
>> +               }
>> +               dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", 
>> cfg->sram_offset);
>> +
>> +               /* Write address */
>> +               ret = dcc_sram_writel(drvdata, cfg->addr, 
>> cfg->sram_offset);
>> +
>> +               if (ret)
>> +                       return ret;
>> +
>> +               cfg->sram_offset += 4;
>> +
>> +               /* Reset link and prev_off */
>> +               cfg->link = 0;
>> +               cfg->prev_off = 0;
>> +       }
>> +
>> +       if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) 
>> {
>> +               dev_err(drvdata->dev, "DCC: Programming error Base: 
>> 0x%x, offset 0x%x\n",
>> +               entry->base, entry->offset);
>> +               ret = -EINVAL;
>> +               return ret;
>> +       }
>> +
>> +       if (cfg->link) {
>> +               /*
>> +                * link already has one offset-length so new
>> +                * offset-length needs to be placed at
>> +                * bits [29:15]
>> +                */
>> +               *pos = 15;
>> +
>> +               /* Clear bits [31:16] */
>> +               cfg->link &= GENMASK(14, 0);
>> +       } else {
>> +               /*
>> +                * link is empty, so new offset-length needs
>> +                * to be placed at bits [15:0]
>> +                */
>> +               *pos = 0;
>> +               cfg->link = 1 << 15;
>> +       }
>> +
>> +       /* write new offset-length pair to correct position */
>> +       cfg->link |= (((off-cfg->prev_off) & GENMASK(7, 0)) |
>> +                    ((entry->len << 8) & GENMASK(14, 8))) << *pos;
> 
> Can this be split to multiple statements? It's crazy hard to read.

Ack

> 
>> +
>> +       cfg->link |= DCC_LINK_DESCRIPTOR;
>> +
>> +       if (*pos) {
>> +               ret = dcc_sram_writel(drvdata, cfg->link, 
>> cfg->sram_offset);
>> +               if (ret)
>> +                       return ret;
>> +               cfg->sram_offset += 4;
>> +               cfg->link = 0;
>> +       }
>> +
>> +       cfg->prev_off  = off + entry->len - 1;
>> +       cfg->prev_addr = cfg->addr;
>> +       return ret;
>> +}
>> +
>> +static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list)
>> +{
>> +       int ret = 0;
>> +       u32 total_len, pos;
>> +       struct dcc_config_entry *entry;
>> +       struct dcc_cfg_attr cfg;
>> +       struct dcc_cfg_loop_attr cfg_loop;
>> +
>> +       memset(&cfg, 0, sizeof(cfg));
>> +       memset(&cfg_loop, 0, sizeof(cfg_loop));
>> +       cfg.sram_offset = drvdata->ram_cfg * 4;
>> +       total_len = 0;
>> +
>> +       list_for_each_entry(entry, &drvdata->cfg_head[curr_list], 
>> list) {
>> +               switch (entry->desc_type) {
>> +               case DCC_READ_WRITE_TYPE:
>> +                       ret = _dcc_ll_cfg_read_write(drvdata, entry, 
>> &cfg);
>> +                       if (ret)
>> +                               goto overstep;
>> +                       break;
>> +
>> +               case DCC_LOOP_TYPE:
>> +                       ret = _dcc_ll_cfg_loop(drvdata, entry, &cfg, 
>> &cfg_loop, &total_len);
>> +                       if (ret)
>> +                               goto overstep;
>> +                       break;
>> +
>> +               case DCC_WRITE_TYPE:
>> +                       ret = _dcc_ll_cfg_write(drvdata, entry, &cfg, 
>> &total_len);
>> +                       if (ret)
>> +                               goto overstep;
>> +                       break;
>> +
>> +               default:
>> +                       ret = _dcc_ll_cfg_default(drvdata, entry, 
>> &cfg, &pos, &total_len);
>> +                       if (ret)
>> +                               goto overstep;
>> +                       break;
>> +               }
>> +       }
>> +
>> +       if (cfg.link) {
>> +               ret = dcc_sram_writel(drvdata, cfg.link, 
>> cfg.sram_offset);
>> +               if (ret)
>> +                       goto overstep;
>> +               cfg.sram_offset += 4;
>> +       }
>> +
>> +       if (cfg_loop.loop_start) {
>> +               dev_err(drvdata->dev, "DCC: Programming error: Loop 
>> unterminated\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       /* Handling special case of list ending with a rd_mod_wr */
>> +       if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) {
>> +               cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0);
>> +               cfg.addr |= DCC_ADDR_DESCRIPTOR;
>> +               ret = dcc_sram_writel(drvdata, cfg.addr, 
>> cfg.sram_offset);
>> +               if (ret)
>> +                       goto overstep;
>> +               cfg.sram_offset += 4;
>> +       }
>> +
>> +       /* Setting zero to indicate end of the list */
>> +       cfg.link = DCC_LINK_DESCRIPTOR;
>> +       ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset);
>> +       if (ret)
>> +               goto overstep;
>> +       cfg.sram_offset += 4;
>> +
>> +       /* Update ram_cfg and check if the data will overstep */
>> +
>> +       drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4;
>> +
>> +       if (cfg.sram_offset + total_len > drvdata->ram_size) {
>> +               cfg.sram_offset += total_len;
>> +               goto overstep;
>> +       }
>> +
>> +       drvdata->ram_start = cfg.sram_offset/4;
>> +       return 0;
>> +overstep:
>> +       ret = -EINVAL;
>> +       memset_io(drvdata->ram_base, 0, drvdata->ram_size);
>> +       dev_err(drvdata->dev, "DCC SRAM oversteps, 0x%x (0x%x)\n",
>> +       cfg.sram_offset, drvdata->ram_size);
>> +
>> +err:
>> +       return ret;
>> +}
>> +
>> +static int dcc_valid_list(struct dcc_drvdata *drvdata, int curr_list)
>> +{
>> +       u32 lock_reg;
>> +
>> +       if (list_empty(&drvdata->cfg_head[curr_list]))
>> +               return -EINVAL;
>> +
>> +       if (drvdata->enable[curr_list]) {
>> +               dev_err(drvdata->dev, "List %d is already enabled\n",
>> +                               curr_list);
>> +               return -EINVAL;
>> +       }
>> +
>> +       lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(curr_list));
>> +       if (lock_reg & 0x1) {
>> +               dev_err(drvdata->dev, "List %d is already locked\n",
>> +                               curr_list);
>> +               return -EINVAL;
>> +       }
>> +
>> +       dev_err(drvdata->dev, "DCC list passed %d\n", curr_list);
>> +       return 0;
>> +}
>> +
>> +static bool is_dcc_enabled(struct dcc_drvdata *drvdata)
>> +{
>> +       bool dcc_enable = false;
>> +       int list;
>> +
>> +       for (list = 0; list < DCC_MAX_LINK_LIST; list++) {
>> +               if (drvdata->enable[list]) {
>> +                       dcc_enable = true;
>> +                       break;
>> +               }
>> +       }
>> +
>> +       return dcc_enable;
>> +}
>> +
>> +static int dcc_enable(struct dcc_drvdata *drvdata)
>> +{
>> +       int ret = 0;
>> +       int list;
>> +       u32 ram_cfg_base;
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       if (!is_dcc_enabled(drvdata)) {
>> +               memset_io(drvdata->ram_base,
>> +                       0xDE, drvdata->ram_size);
>> +       }
>> +
>> +       for (list = 0; list < drvdata->nr_link_list; list++) {
>> +
>> +               if (dcc_valid_list(drvdata, list))
>> +                       continue;
>> +
>> +               /* 1. Take ownership of the list */
>> +               dcc_writel(drvdata, BIT(0), DCC_LL_LOCK(list));
>> +
>> +               /* 2. Program linked-list in the SRAM */
>> +               ram_cfg_base = drvdata->ram_cfg;
>> +               ret = __dcc_ll_cfg(drvdata, list);
>> +               if (ret) {
>> +                       dcc_writel(drvdata, 0, DCC_LL_LOCK(list));
>> +                       dev_info(drvdata->dev, "DCC ram programming 
>> failed\n");
>> +                       goto err;
>> +               }
>> +
>> +               /* 3. program DCC_RAM_CFG reg */
>> +               dcc_writel(drvdata, ram_cfg_base +
>> +                       drvdata->ram_offset/4, DCC_LL_BASE(list));
>> +               dcc_writel(drvdata, drvdata->ram_start +
>> +                       drvdata->ram_offset/4, DCC_FD_BASE(list));
>> +               dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list));
>> +
>> +               /* 4. Clears interrupt status register */
>> +               dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list));
>> +               dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)),
>> +                                       DCC_LL_INT_STATUS(list));
>> +
>> +               dev_info(drvdata->dev, "All values written to 
>> enable.\n");
> 
> Debug print?

Ack

> 
>> +               /* Make sure all config is written in sram */
>> +               mb();
> 
> This won't work as intended.

This was called to prevent instruction reordering if the driver runs on 
multiple
CPU cores. As the hardware manipulation has to be done sequentially 
before the
trigger is set. Kindly let me know the concern in this case.

> 
>> +
>> +               drvdata->enable[list] = true;
>> +
>> +               /* 5. Configure trigger */
>> +               dcc_writel(drvdata, BIT(9), DCC_LL_CFG(list));
>> +       }
>> +
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return ret;
>> +}
>> +
>> +static void dcc_disable(struct dcc_drvdata *drvdata)
>> +{
>> +       int curr_list;
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       if (!dcc_ready(drvdata))
>> +               dev_err(drvdata->dev, "DCC is not ready Disabling 
>> DCC...\n");
> 
> Is that two sentences? And a debug print?

Ack.

> 
>> +
>> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; 
>> curr_list++) {
>> +               if (!drvdata->enable[curr_list])
>> +                       continue;
>> +               dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list));
>> +               dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list));
>> +               dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list));
>> +               dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
>> +               drvdata->enable[curr_list] = false;
>> +       }
>> +       memset_io(drvdata->ram_base, 0, drvdata->ram_size);
>> +       drvdata->ram_cfg = 0;
>> +       drvdata->ram_start = 0;
>> +       mutex_unlock(&drvdata->mutex);
>> +}
>> +
>> +static ssize_t curr_list_show(struct device *dev,
>> +       struct device_attribute *attr, char *buf)
>> +{
>> +       int ret;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +       if (drvdata->curr_list == DCC_INVALID_LINK_LIST) {
>> +               dev_err(dev, "curr_list is not set.\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       ret = scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->curr_list);
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return ret;
>> +}
>> +
>> +static ssize_t curr_list_store(struct device *dev,
>> +                                               struct 
>> device_attribute *attr,
>> +                                               const char *buf, 
>> size_t size)
>> +{
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +       unsigned long val;
>> +       u32 lock_reg;
>> +       bool dcc_enable = false;
>> +
>> +       if (kstrtoul(buf, 16, &val))
>> +               return -EINVAL;
>> +
>> +       if (val >= drvdata->nr_link_list)
>> +               return -EINVAL;
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       dcc_enable = is_dcc_enabled(drvdata);
>> +       if (drvdata->curr_list != DCC_INVALID_LINK_LIST && dcc_enable) 
>> {
>> +               dev_err(drvdata->dev, "DCC is enabled, please disable 
>> it first.\n");
>> +               mutex_unlock(&drvdata->mutex);
>> +               return -EINVAL;
>> +       }
>> +
>> +       lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
>> +       if (lock_reg & 0x1) {
>> +               dev_err(drvdata->dev, "DCC linked list is already 
>> configured\n");
>> +               mutex_unlock(&drvdata->mutex);
>> +               return -EINVAL;
>> +       }
>> +       drvdata->curr_list = val;
>> +       mutex_unlock(&drvdata->mutex);
>> +
>> +       return size;
>> +}
>> +
>> +static DEVICE_ATTR_RW(curr_list);
>> +
>> +
>> +static ssize_t trigger_store(struct device *dev,
>> +                                       struct device_attribute *attr,
>> +                                       const char *buf, size_t size)
>> +{
>> +       int ret = 0;
>> +       unsigned long val;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       if (kstrtoul(buf, 16, &val))
>> +               return -EINVAL;
>> +       if (val != 1)
>> +               return -EINVAL;
>> +
>> +       ret = dcc_sw_trigger(drvdata);
>> +       if (!ret)
>> +               ret = size;
>> +
>> +       return ret;
>> +}
>> +static DEVICE_ATTR_WO(trigger);
>> +
>> +static ssize_t enable_show(struct device *dev,
>> +       struct device_attribute *attr, char *buf)
>> +{
>> +       int ret;
>> +       bool dcc_enable = false;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> +               dev_err(dev, "Select link list to program using 
>> curr_list\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       dcc_enable = is_dcc_enabled(drvdata);
>> +
>> +       ret = scnprintf(buf, PAGE_SIZE, "%u\n",
>> +                               (unsigned int)dcc_enable);
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
> 
> What does the mutex being held serve here?

As mentioned earlier, the mutex has been used while accessing 
dcc_drvdata structure.

> 
>> +       return ret;
>> +}
>> +
>> +static ssize_t enable_store(struct device *dev,
>> +                               struct device_attribute *attr,
>> +                               const char *buf, size_t size)
>> +{
>> +       int ret = 0;
>> +       unsigned long val;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       if (kstrtoul(buf, 16, &val))
>> +               return -EINVAL;
>> +
>> +       if (val)
>> +               ret = dcc_enable(drvdata);
>> +       else
>> +               dcc_disable(drvdata);
>> +
>> +       if (!ret)
>> +               ret = size;
>> +
>> +       return ret;
>> +
>> +}
>> +
>> +static DEVICE_ATTR_RW(enable);
>> +
>> +static ssize_t config_show(struct device *dev,
>> +       struct device_attribute *attr, char *buf)
>> +{
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +       struct dcc_config_entry *entry;
>> +       char local_buf[64];
>> +       int len = 0, count = 0;
>> +
>> +       buf[0] = '\0';
> 
> Why?

The strlcat function is used here to concatenate the buffer with the 
config values.
The strlcat function in C needs a NULL terminated string both as it's 
source and
destination. That's why this has been initialized with NULL termination.


> 
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> +               dev_err(dev, "Select link list to program using 
>> curr_list\n");
>> +               count = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       list_for_each_entry(entry,
>> +       &drvdata->cfg_head[drvdata->curr_list], list) {
>> +               switch (entry->desc_type) {
>> +               case DCC_READ_WRITE_TYPE:
>> +                       len = snprintf(local_buf, 64, "Index: 0x%x, 
>> mask: 0x%x, val: 0x%x\n",
>> +                               entry->index, entry->mask, 
>> entry->write_val);
>> +                       break;
>> +               case DCC_LOOP_TYPE:
>> +                       len = snprintf(local_buf, 64, "Index: 0x%x, 
>> Loop: %d\n",
>> +                               entry->index, entry->loop_cnt);
>> +                       break;
>> +               case DCC_WRITE_TYPE:
>> +                       len = snprintf(local_buf, 64,
>> +                               "Write Index: 0x%x, Base: 0x%x, 
>> Offset: 0x%x, len: 0x%x APB: %d\n",
>> +                               entry->index, entry->base, 
>> entry->offset, entry->len,
>> +                               entry->apb_bus);
>> +                       break;
>> +               default:
>> +                       len = snprintf(local_buf, 64,
>> +                               "Read Index: 0x%x, Base: 0x%x, Offset: 
>> 0x%x, len: 0x%x APB: %d\n",
>> +                               entry->index, entry->base, 
>> entry->offset,
>> +                               entry->len, entry->apb_bus);
>> +               }
>> +
>> +               if ((count + len) > PAGE_SIZE) {
>> +                       dev_err(dev, "DCC: Couldn't write complete 
>> config\n");
>> +                       break;
>> +               }
>> +               strlcat(buf, local_buf, PAGE_SIZE);
>> +               count += len;
>> +       }
>> +
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return count;
>> +}
>> +
>> +static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int 
>> addr,
>> +                               unsigned int len, int apb_bus)
>> +{
>> +       int ret;
>> +       struct dcc_config_entry *entry, *pentry;
>> +       unsigned int base, offset;
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> +               dev_err(drvdata->dev, "Select link list to program 
>> using curr_list\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       if (!len || len > (drvdata->ram_size / 8)) {
> 
> What is 8?

This is to check if the address entered by the user exceeds the allowed 
address ranges as per dcc hardware.
Will add a define for this.

> 
>> +               dev_err(drvdata->dev, "DCC: Invalid length\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       base = addr & GENMASK(31, 4);
> 
> Make a define for the GENMASK?

Ack

> 
>> +
>> +       if (!list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
>> +               pentry = 
>> list_last_entry(&drvdata->cfg_head[drvdata->curr_list],
>> +                       struct dcc_config_entry, list);
>> +
>> +               if (pentry->desc_type == DCC_ADDR_TYPE &&
>> +                               addr >= (pentry->base + 
>> pentry->offset) &&
>> +                               addr <= (pentry->base +
>> +                                       pentry->offset + 
>> MAX_DCC_OFFSET)) {
>> +
>> +                       /* Re-use base address from last entry */
>> +                       base = pentry->base;
>> +
>> +                       if ((pentry->len * 4 + pentry->base + 
>> pentry->offset)
>> +                                       == addr) {
>> +                               len += pentry->len;
>> +
>> +                               if (len > MAX_DCC_LEN)
>> +                                       pentry->len = MAX_DCC_LEN;
>> +                               else
>> +                                       pentry->len = len;
>> +
>> +                               addr = pentry->base + pentry->offset +
>> +                                       pentry->len * 4;
>> +                               len -= pentry->len;
>> +                       }
>> +               }
>> +       }
>> +
>> +       offset = addr - base;
>> +
>> +       while (len) {
>> +               entry = devm_kzalloc(drvdata->dev, sizeof(*entry), 
>> GFP_KERNEL);
>> +               if (!entry) {
>> +                       ret = -ENOMEM;
>> +                       goto err;
>> +               }
>> +
>> +               entry->base = base;
>> +               entry->offset = offset;
>> +               entry->len = min_t(u32, len, MAX_DCC_LEN);
>> +               entry->index = 
>> drvdata->nr_config[drvdata->curr_list]++;
>> +               entry->desc_type = DCC_ADDR_TYPE;
>> +               entry->apb_bus = apb_bus;
>> +               INIT_LIST_HEAD(&entry->list);
>> +               list_add_tail(&entry->list,
>> +                       &drvdata->cfg_head[drvdata->curr_list]);
>> +
>> +               len -= entry->len;
>> +               offset += MAX_DCC_LEN * 4;
>> +       }
>> +
> 
> err:
> 
>> +       mutex_unlock(&drvdata->mutex);
>> +       return 0;
> 
> return ret;
> 
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return ret;
> 
> Remove these three lines.

Ack

> 
>> +}
>> +
>> +static ssize_t config_store(struct device *dev,
>> +                               struct device_attribute *attr,
>> +                               const char *buf, size_t size)
>> +{
>> +       int ret, len, apb_bus;
>> +       unsigned int base;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +       int nval;
>> +
>> +       nval = sscanf(buf, "%x %i %d", &base, &len, &apb_bus);
>> +       if (nval <= 0 || nval > 3)
>> +               return -EINVAL;
>> +
>> +       if (nval == 1) {
>> +               len = 1;
>> +               apb_bus = 0;
>> +       } else if (nval == 2) {
>> +               apb_bus = 0;
>> +       } else {
>> +               apb_bus = 1;
>> +       }
>> +
>> +       ret = dcc_config_add(drvdata, base, len, apb_bus);
>> +       if (ret)
>> +               return ret;
>> +
>> +       return size;
>> +
>> +}
>> +
>> +static DEVICE_ATTR_RW(config);
>> +
>> +static void dcc_config_reset(struct dcc_drvdata *drvdata)
>> +{
>> +       struct dcc_config_entry *entry, *temp;
>> +       int curr_list;
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; 
>> curr_list++) {
>> +               list_for_each_entry_safe(entry, temp,
>> +                       &drvdata->cfg_head[curr_list], list) {
>> +                       list_del(&entry->list);
>> +                       devm_kfree(drvdata->dev, entry);
>> +                       drvdata->nr_config[curr_list]--;
>> +               }
>> +       }
>> +       drvdata->ram_start = 0;
>> +       drvdata->ram_cfg = 0;
>> +       mutex_unlock(&drvdata->mutex);
>> +}
>> +
>> +
>> +static ssize_t config_reset_store(struct device *dev,
>> +       struct device_attribute *attr,
>> +       const char *buf, size_t size)
>> +{
>> +       unsigned long val;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       if (kstrtoul(buf, 16, &val))
>> +               return -EINVAL;
>> +
>> +       if (val)
>> +               dcc_config_reset(drvdata);
>> +
>> +       return size;
>> +}
>> +
>> +static DEVICE_ATTR_WO(config_reset);
>> +
>> +static ssize_t ready_show(struct device *dev,
>> +       struct device_attribute *attr, char *buf)
>> +{
>> +       int ret;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> +               dev_err(dev, "Select link list to program using 
>> curr_list\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       if (!drvdata->enable[drvdata->curr_list]) {
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       ret = scnprintf(buf, PAGE_SIZE, "%u\n",
>> +                       (unsigned int)FIELD_GET(BIT(1), 
>> dcc_readl(drvdata, DCC_STATUS)));
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return ret;
>> +}
>> +
>> +static DEVICE_ATTR_RO(ready);
>> +
>> +static ssize_t interrupt_disable_show(struct device *dev,
>> +                                               struct 
>> device_attribute *attr,
>> +                                               char *buf)
>> +{
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       return scnprintf(buf, PAGE_SIZE, "%u\n",
>> +                               (unsigned 
>> int)drvdata->interrupt_disable);
>> +}
>> +
>> +static ssize_t interrupt_disable_store(struct device *dev,
>> +       struct device_attribute *attr,
>> +       const char *buf, size_t size)
>> +{
>> +       unsigned long val;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       if (kstrtoul(buf, 16, &val))
>> +               return -EINVAL;
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +       drvdata->interrupt_disable = (val ? 1:0);
>> +       mutex_unlock(&drvdata->mutex);
>> +       return size;
>> +}
>> +
>> +static DEVICE_ATTR_RW(interrupt_disable);
>> +
>> +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long 
>> loop_cnt)
>> +{
>> +       struct dcc_config_entry *entry;
>> +
>> +       entry = devm_kzalloc(drvdata->dev, sizeof(*entry), 
>> GFP_KERNEL);
>> +       if (!entry)
>> +               return -ENOMEM;
>> +
>> +       entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT);
>> +       entry->index = drvdata->nr_config[drvdata->curr_list]++;
>> +       entry->desc_type = DCC_LOOP_TYPE;
>> +       INIT_LIST_HEAD(&entry->list);
>> +       list_add_tail(&entry->list, 
>> &drvdata->cfg_head[drvdata->curr_list]);
>> +
>> +       return 0;
>> +}
>> +
>> +static ssize_t loop_store(struct device *dev,
>> +       struct device_attribute *attr,
>> +       const char *buf, size_t size)
>> +{
>> +       int ret;
>> +       unsigned long loop_cnt;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       if (kstrtoul(buf, 16, &loop_cnt)) {
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> +               dev_err(dev, "Select link list to program using 
>> curr_list\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       ret = dcc_add_loop(drvdata, loop_cnt);
>> +       if (ret)
>> +               goto err;
>> +
>> +       mutex_unlock(&drvdata->mutex);
>> +       return size;
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return ret;
>> +}
>> +
>> +static DEVICE_ATTR_WO(loop);
>> +
>> +static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned 
>> int mask,
>> +                               unsigned int val)
>> +{
>> +       int ret = 0;
>> +       struct dcc_config_entry *entry;
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> +               dev_err(drvdata->dev, "Select link list to program 
>> using curr_list\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       if (list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
>> +               dev_err(drvdata->dev, "DCC: No read address 
>> programmed\n");
>> +               ret = -EPERM;
>> +               goto err;
>> +       }
>> +
>> +       entry = devm_kzalloc(drvdata->dev, sizeof(*entry), 
>> GFP_KERNEL);
>> +       if (!entry) {
>> +               ret = -ENOMEM;
>> +               goto err;
>> +       }
>> +
>> +       entry->desc_type = DCC_READ_WRITE_TYPE;
>> +       entry->mask = mask;
>> +       entry->write_val = val;
>> +       entry->index = drvdata->nr_config[drvdata->curr_list]++;
>> +       INIT_LIST_HEAD(&entry->list);
>> +       list_add_tail(&entry->list, 
>> &drvdata->cfg_head[drvdata->curr_list]);
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return ret;
>> +}
>> +
>> +static ssize_t rd_mod_wr_store(struct device *dev,
>> +       struct device_attribute *attr,
>> +       const char *buf, size_t size)
>> +{
>> +       int ret;
>> +       int nval;
>> +       unsigned int mask, val;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       nval = sscanf(buf, "%x %x", &mask, &val);
>> +
>> +       if (nval <= 1 || nval > 2)
>> +               return -EINVAL;
>> +
>> +       ret = dcc_rd_mod_wr_add(drvdata, mask, val);
>> +       if (ret)
>> +               return ret;
>> +
>> +       return size;
>> +
>> +}
>> +
>> +static DEVICE_ATTR_WO(rd_mod_wr);
>> +
>> +static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int 
>> addr,
>> +                               unsigned int write_val, int apb_bus)
>> +{
>> +       struct dcc_config_entry *entry;
>> +
>> +       entry = devm_kzalloc(drvdata->dev, sizeof(*entry), 
>> GFP_KERNEL);
>> +       if (!entry)
>> +               return -ENOMEM;
>> +
>> +       entry->desc_type = DCC_WRITE_TYPE;
>> +       entry->base = addr & GENMASK(31, 4);
>> +       entry->offset = addr - entry->base;
>> +       entry->write_val = write_val;
>> +       entry->index = drvdata->nr_config[drvdata->curr_list]++;
>> +       entry->len = 1;
>> +       entry->apb_bus = apb_bus;
>> +       INIT_LIST_HEAD(&entry->list);
>> +       list_add_tail(&entry->list, 
>> &drvdata->cfg_head[drvdata->curr_list]);
>> +
>> +       return 0;
>> +}
>> +
>> +static ssize_t config_write_store(struct device *dev,
>> +                                               struct 
>> device_attribute *attr,
>> +                                               const char *buf, 
>> size_t size)
>> +{
>> +       int ret;
>> +       int nval;
>> +       unsigned int addr, write_val;
>> +       int apb_bus = 0;
>> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> +
>> +       mutex_lock(&drvdata->mutex);
>> +
>> +       nval = sscanf(buf, "%x %x %d", &addr, &write_val, &apb_bus);
>> +
>> +       if (nval <= 1 || nval > 3) {
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> +               dev_err(dev, "Select link list to program using 
>> curr_list\n");
>> +               ret = -EINVAL;
>> +               goto err;
>> +       }
>> +
>> +       if (nval == 3 && apb_bus != 0)
>> +               apb_bus = 1;
>> +
>> +       ret = dcc_add_write(drvdata, addr, write_val, apb_bus);
>> +       if (ret)
>> +               goto err;
>> +
>> +       mutex_unlock(&drvdata->mutex);
>> +       return size;
>> +err:
>> +       mutex_unlock(&drvdata->mutex);
>> +       return ret;
>> +}
>> +
>> +static DEVICE_ATTR_WO(config_write);
>> +
>> +static const struct device_attribute *dcc_attrs[] = {
>> +       &dev_attr_trigger,
>> +       &dev_attr_enable,
>> +       &dev_attr_config,
>> +       &dev_attr_config_reset,
>> +       &dev_attr_ready,
>> +       &dev_attr_interrupt_disable,
>> +       &dev_attr_loop,
>> +       &dev_attr_rd_mod_wr,
>> +       &dev_attr_curr_list,
>> +       &dev_attr_config_write,
>> +       NULL,
>> +};
>> +
>> +static int dcc_create_files(struct device *dev,
>> +                                       const struct device_attribute 
>> **attrs)
>> +{
>> +       int ret = 0, i;
>> +
>> +       for (i = 0; attrs[i] != NULL; i++) {
>> +               ret = device_create_file(dev, attrs[i]);
>> +               if (ret) {
>> +                       dev_err(dev, "DCC: Couldn't create sysfs 
>> attribute: %s\n",
>> +                               attrs[i]->attr.name);
>> +                       break;
>> +               }
>> +       }
>> +       return ret;
>> +}
>> +
>> +static int dcc_sram_open(struct inode *inode, struct file *file)
>> +{
>> +       struct dcc_drvdata *drvdata = container_of(inode->i_cdev,
>> +               struct dcc_drvdata,
>> +               sram_dev);
>> +       file->private_data = drvdata;
>> +
>> +       return  0;
>> +}
>> +
>> +static ssize_t dcc_sram_read(struct file *file, char __user *data,
>> +                                               size_t len, loff_t 
>> *ppos)
>> +{
>> +       unsigned char *buf;
>> +       struct dcc_drvdata *drvdata = file->private_data;
> 
> const?

Ack.

> 
>> +
>> +       /* EOF check */
>> +       if (drvdata->ram_size <= *ppos)
>> +               return 0;
>> +
>> +       if ((*ppos + len) > drvdata->ram_size)
>> +               len = (drvdata->ram_size - *ppos);
>> +
>> +       buf = kzalloc(len, GFP_KERNEL);
>> +       if (!buf)
>> +               return -ENOMEM;
>> +
>> +       memcpy_fromio(buf, drvdata->ram_base + *ppos, len);
>> +
>> +       if (copy_to_user(data, buf, len)) {
> 
> Is there any sort of memcpy_fromio_to_user() API? That would avoid the
> extra buffer allocation by copying to userspace in the readl loop.

No. For directly copying io data to userspace we need to use direct I/O 
which is used for
special cases like tape drivers. In this case the complexity of using it 
outweighs it's
advantages. Also this is a fixed transfer of data in the form of 
dcc_sram content rather
than bulk transfers.


> 
>> +               dev_err(drvdata->dev, "DCC: Couldn't copy all data to 
>> user\n");
> 
> I think we don't want this sort of error message in userspace
> triggerable copy operations.

Ack.

> 
>> +               kfree(buf);
>> +               return -EFAULT;
>> +       }
>> +
>> +       *ppos += len;
>> +
>> +       kfree(buf);
>> +
>> +       return len;
>> +}
>> +
>> +static const struct file_operations dcc_sram_fops = {
>> +       .owner          = THIS_MODULE,
>> +       .open           = dcc_sram_open,
>> +       .read           = dcc_sram_read,
>> +       .llseek         = no_llseek,
>> +};
>> +
>> +static int dcc_sram_dev_register(struct dcc_drvdata *drvdata)
>> +{
>> +       int ret;
>> +       struct device *device;
>> +       dev_t dev;
>> +
>> +       ret = alloc_chrdev_region(&dev, 0, 1, drvdata->sram_node);
>> +       if (ret)
>> +               goto err_alloc;
>> +
>> +       cdev_init(&drvdata->sram_dev, &dcc_sram_fops);
>> +
>> +       drvdata->sram_dev.owner = THIS_MODULE;
>> +       ret = cdev_add(&drvdata->sram_dev, dev, 1);
>> +       if (ret)
>> +               goto err_cdev_add;
>> +
>> +       drvdata->sram_class = class_create(THIS_MODULE, 
>> drvdata->sram_node);
>> +       if (IS_ERR(drvdata->sram_class)) {
>> +               ret = PTR_ERR(drvdata->sram_class);
>> +               goto err_class_create;
>> +       }
>> +
>> +       device = device_create(drvdata->sram_class, NULL,
>> +                                               drvdata->sram_dev.dev, 
>> drvdata,
>> +                                               drvdata->sram_node);
>> +       if (IS_ERR(device)) {
>> +               ret = PTR_ERR(device);
>> +               goto err_dev_create;
>> +       }
>> +
>> +       return 0;
>> +err_dev_create:
>> +       class_destroy(drvdata->sram_class);
>> +err_class_create:
>> +       cdev_del(&drvdata->sram_dev);
>> +err_cdev_add:
>> +       unregister_chrdev_region(drvdata->sram_dev.dev, 1);
>> +err_alloc:
>> +       return ret;
>> +}
>> +
>> +static void dcc_sram_dev_deregister(struct dcc_drvdata *drvdata)
>> +{
>> +       device_destroy(drvdata->sram_class, drvdata->sram_dev.dev);
>> +       class_destroy(drvdata->sram_class);
>> +       cdev_del(&drvdata->sram_dev);
>> +       unregister_chrdev_region(drvdata->sram_dev.dev, 1);
>> +}
>> +
>> +static int dcc_sram_dev_init(struct dcc_drvdata *drvdata)
>> +{
>> +       int ret = 0;
>> +
>> +       drvdata->sram_node = DCC_SRAM_NODE;
>> +       if (!drvdata->sram_node)
>> +               return -ENOMEM;
>> +
>> +       ret = dcc_sram_dev_register(drvdata);
>> +       if (ret)
>> +               dev_err(drvdata->dev, "DCC: sram node not 
>> registered.\n");
>> +
>> +       return ret;
>> +}
>> +
>> +static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata)
>> +{
>> +       dcc_sram_dev_deregister(drvdata);
>> +}
>> +
>> +static int dcc_probe(struct platform_device *pdev)
>> +{
>> +       int ret = 0, i;
>> +       struct device *dev = &pdev->dev;
>> +       struct dcc_drvdata *dcc;
>> +       struct resource *res;
>> +       const struct qcom_dcc_config *cfg;
>> +
>> +       dcc = devm_kzalloc(dev, sizeof(*dcc), GFP_KERNEL);
>> +       if (!dcc)
>> +               return -ENOMEM;
>> +
>> +       dcc->dev = &pdev->dev;
>> +       platform_set_drvdata(pdev, dcc);
>> +
>> +       dcc->base = devm_platform_ioremap_resource_byname(pdev, 
>> "dcc");
>> +       if (!dcc->base)
>> +               return -ENOMEM;
>> +
>> +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 
>> "dcc-ram");
>> +       if (!res)
>> +               return -EINVAL;
>> +
>> +       dcc->ram_size = resource_size(res);
>> +
>> +       dcc->ram_base = devm_ioremap(dev, res->start, 
>> resource_size(res));
>> +       if (!dcc->ram_base)
>> +               return -ENOMEM;
> 
> How about
> 
> 	dcc->base = devm_platform_ioremap_resource(pdev, 0);
> 	if (IS_ERR(dcc->base))
> 		return PTR_ERR(dcc->base);
> 
> 	dcc->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
> 	if (IS_ERR(dcc->ram_base))
> 		return PTR_ERR(dcc->ram_base);
> 
> 	dcc->ram_size = resource_size(res);

Ack

> 
>> +
>> +       cfg = of_device_get_match_data(&pdev->dev);
> 
> 	if (!cfg)
> 		return -EINVAL;
> 
> 
>> +       dcc->ram_offset = cfg->dcc_ram_offset;
>> +
>> +       if (FIELD_GET(BIT(DCC_VER_INFO_BIT), dcc_readl(dcc, 
>> DCC_HW_INFO))) {
>> +               dcc->mem_map_ver = DCC_MEM_MAP_VER3;
>> +               dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
>> +               if (dcc->nr_link_list == 0)
>> +                       return  -EINVAL;
>> +       } else if ((dcc_readl(dcc, DCC_HW_INFO) & DCC_VER_MASK2) == 
>> DCC_VER_MASK2) {
> 
> Can we u32 val = dcc_readl(dcc, DCC_HW_INFO) once instead of twice?

Ack.

> 
>> +               dcc->mem_map_ver = DCC_MEM_MAP_VER2;
>> +               dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
>> +               if (dcc->nr_link_list == 0)
>> +                       return  -EINVAL;
>> +       } else {
>> +               dcc->mem_map_ver = DCC_MEM_MAP_VER1;
>> +               dcc->nr_link_list = DCC_MAX_LINK_LIST;
>> +       }
>> +
>> +       if ((dcc_readl(dcc, DCC_HW_INFO) & BIT(6)) == BIT(6))
> 
> Err thrice.

Ack

> 
>> +               dcc->loopoff = DCC_FIX_LOOP_OFFSET;
>> +       else
>> +               dcc->loopoff = get_bitmask_order((dcc->ram_size +
>> +                               dcc->ram_offset) / 4 - 1);
>> +
>> +       mutex_init(&dcc->mutex);
>> +       dcc->enable = devm_kcalloc(dev, dcc->nr_link_list,
>> +                       sizeof(bool), GFP_KERNEL);
>> +       if (!dcc->enable)
>> +               return -ENOMEM;
>> +
>> +       dcc->configured = devm_kcalloc(dev, dcc->nr_link_list,
>> +                       sizeof(bool), GFP_KERNEL);
>> +       if (!dcc->configured)
>> +               return -ENOMEM;
>> +
>> +       dcc->nr_config = devm_kcalloc(dev, dcc->nr_link_list,
>> +                       sizeof(u32), GFP_KERNEL);
>> +       if (!dcc->nr_config)
>> +               return -ENOMEM;
>> +
>> +       dcc->cfg_head = devm_kcalloc(dev, dcc->nr_link_list,
>> +                       sizeof(struct list_head), GFP_KERNEL);
>> +       if (!dcc->cfg_head)
>> +               return -ENOMEM;
> 
> These are a lot of allocations. Any chance we can do one instead of 
> this
> many?

All these variable have predefined requirement of sizes
so they need to be allocated separately.

> 
>> +
>> +       for (i = 0; i < dcc->nr_link_list; i++)
>> +               INIT_LIST_HEAD(&dcc->cfg_head[i]);
>> +
>> +
> 
> Drop double newline?

Ack.

> 
>> +       memset_io(dcc->ram_base, 0, dcc->ram_size);
>> +       dcc->curr_list = DCC_INVALID_LINK_LIST;
>> +       ret = dcc_sram_dev_init(dcc);
>> +       if (ret)
>> +               goto out;
> 
> 		return ret;
> 
>> +
>> +       ret = dcc_create_files(dev, dcc_attrs);
>> +       if (ret)
>> +               goto out;
>> +
>> +out:
>> +       return ret;
> 
> Just
> 
> 	return dcc_create_files(...)

Ack

> 
>> +}
>> +
>> +static int dcc_remove(struct platform_device *pdev)
>> +{
>> +       struct dcc_drvdata *drvdata = platform_get_drvdata(pdev);
>> +
>> +       dcc_sram_dev_exit(drvdata);
>> +
>> +       dcc_config_reset(drvdata);
>> +
>> +       return 0;
>> +}
>> +
>> +static const struct qcom_dcc_config sm8150_cfg = {
>> +       .dcc_ram_offset = 0x5000,
>> +};
>> +
>> +static const struct of_device_id dcc_match_table[] = {
>> +       { .compatible = "qcom,sm8150-dcc", .data = &sm8150_cfg },
> 
> Missing a {} terminator.

Ack

> 
>> +};
>> +MODULE_DEVICE_TABLE(of, dcc_match_table);
>> +
>> +static struct platform_driver dcc_driver = {
>> +       .probe                                  = dcc_probe,
>> +       .remove                                 = dcc_remove,
>> +       .driver                                 = {
> 
> This tabbing is very odd. I'd expect
> 
>> +static struct platform_driver dcc_driver = {
>> +       .probe   = dcc_probe,
>> +       .remove  = dcc_remove,
>> +       .driver  = {
> 
> that (ignoring spaces instead of tabs)

Ack

> 
>> +               .name           = "qcom-dcc",
>> +               .of_match_table = dcc_match_table,
>> +       },
>> +};
>> +
>> +module_platform_driver(dcc_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver");
>> +

Re: [PATCH V2 3/5] DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver

[schowdhu]

On 2021-03-30 01:39, Stephen Boyd wrote:
> Quoting Souradeep Chowdhury (2021-03-25 01:02:34)
>> The DCC is a DMA engine designed to store register values either in
>> case of a system crash or in case of software triggers manually done
>> by the user.Using DCC hardware and the sysfs interface of the driver
>> the user can exploit various functionalities of DCC.The user can 
>> specify
>> the register addresses,the values of which is stored by DCC in it's
>> dedicated SRAM.The register addresses can be used either to read from,
>> write to,first read and store value and then write or to loop.All 
>> these
>> options can be exploited using the sysfs interface given to the user.
>> Following are the sysfs interfaces exposed in DCC driver which are
>> documented
>> 1)trigger
>> 2)config
>> 3)config_write
>> 4)config_reset
>> 5)enable
>> 6)rd_mod_wr
>> 7)loop
>> 
>> Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
>> ---
>>  Documentation/ABI/testing/sysfs-driver-dcc | 114 
>> +++++++++++++++++++++++++++++
> 
> Please combine this with the driver patch.

Ack

> 
>>  1 file changed, 114 insertions(+)
>>  create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc
> 
> Perhaps this should be an ioctl interface instead of a sysfs interface?

The reasons for choosing sysfs over ioctl is as follows


i) As can be seen from the sysfs attribute descriptions, most of it does 
basic hardware manipulations like dcc_enable, dcc_disable, config reset 
etc. As a result sysfs is preferred over ioctl as we just need to enter 
a 0 or 1
signal in such cases.

ii) Existing similar debug hardwares are there for which drivers have 
been written using sysfs interface. One such example is the 
coresight-etm-trace driver. Following is the link for reference

https://www.kernel.org/doc/html/latest/trace/coresight/coresight-etm4x-reference.html

> 
>> 
>> diff --git a/Documentation/ABI/testing/sysfs-driver-dcc 
>> b/Documentation/ABI/testing/sysfs-driver-dcc
>> new file mode 100644
>> index 0000000..05d24f0
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/sysfs-driver-dcc
>> @@ -0,0 +1,114 @@
>> +What:           /sys/bus/platform/devices/.../trigger
>> +Date:           March 2021
>> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
>> +Description:
>> +               This is the sysfs interface for manual software
>> +               triggers.The user can simply enter a 1 against
>> +               the sysfs file and enable a manual trigger.
>> +               Example:
>> +               echo  1 > /sys/bus/platform/devices/.../trigger
>> +
>> +What:           /sys/bus/platform/devices/.../enable
>> +Date:           March 2021
>> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
>> +Description:
>> +               This sysfs interface is used for enabling the
>> +               the dcc hardware.Without this being set to 1,
> 
> Space after period please.

Ack

> 
>> +               the dcc hardware ceases to function.
>> +               Example:
>> +               echo  0 > /sys/bus/platform/devices/.../enable
>> +               (disable interface)
>> +               echo  1 > /sys/bus/platform/devices/.../enable
>> +               (enable interface)
>> +
>> +What:           /sys/bus/platform/devices/.../config
>> +Date:           March 2021
>> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
>> +Description:
>> +               This is the most commonly used sysfs interface
>> +               file and this basically stores the addresses of
>> +               the registers which needs to be read in case of
>> +               a hardware crash or manual software triggers.
>> +               Example:
>> +               echo  0x80000010 10 > 
>> /sys/bus/platform/devices/../config
>> +               This specifies that 10 words starting from address
>> +               0x80000010 is to be read.In case there are no words to 
>> be
>> +               specified we can simply enter the address.
>> +
>> +What:           /sys/bus/platform/devices/.../config_write
>> +Date:           March 2021
>> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
>> +Description:
>> +               This file allows user to write a value to the register
>> +               address given as argument.The values are entered in 
>> the
>> +               form of <register_address> <value>.The reason for this
>> +               feature of dcc is that for accessing certain registers
>> +               it is necessary to set some bits of soe other 
>> register.
> 
> s/soe/some/?

Ack

> 
>> +               That is achievable by giving DCC this privelege.
> 
> s/privelege/privilege/

Ack

> 
>> +               Example:
>> +               echo 0x80000000 0xFF > 
>> /sys/bus/platform/devices/.../config_write
>> +
>> +What:           /sys/bus/platform/devices/.../config_reset
>> +Date:           March 2021
>> +Contact:        Souradeep Chowdhury <schowdhu@codeaurora.org>
>> +Description:
>> +               This file is used to reset the configuration of
>> +               a dcc driver to the default configuration.
>> +               Example:
>> +               echo  1 > /sys/bus/platform/devices/.../config_reset
>> +

Re: [PATCH V2 2/5] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)

[Stephen Boyd]

Quoting schowdhu@codeaurora.org (2021-04-01 07:04:07)
> On 2021-03-30 01:35, Stephen Boyd wrote:
> > Quoting Souradeep Chowdhury (2021-03-25 01:02:33)
> >> diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c
> >> new file mode 100644
> >> index 0000000..a55d8ca7
> >> --- /dev/null
> >> +++ b/drivers/soc/qcom/dcc.c
> >> @@ -0,0 +1,1549 @@
[..]
> > 
> >> +       void __iomem            *base;
> >> +       u32                     reg_size;
> >> +       struct device           *dev;
> >> +       struct mutex            mutex;
> > 
> > In particular what this mutex is protecting.
> 
> Ack. The mutex is used to protect the access as well as manipulation of 
> the main instance of dcc_drvdata structure
> initialized during probe time. This structure contains the useful driver 
> data information and is set using the call
> platform_set_drvdata(pdev, drvdata) which links this data to the 
> platform device and hence needs to be protected via
> mutex locks. The same convention is followed across other similar 
> drivers exposing userspace like the llcc driver.

The region that the mutex is protecting seems quite large. That's
probably because I don't understand the driver.

> > 
> >> +
> >> +       mutex_lock(&drvdata->mutex);
> >> +
> >> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; 
> >> curr_list++) {
> >> +               if (!drvdata->enable[curr_list])
> >> +                       continue;
> >> +               ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
> >> +               tmp_ll_cfg = ll_cfg & ~BIT(9);
> >> +               dcc_writel(drvdata, tmp_ll_cfg, 
> >> DCC_LL_CFG(curr_list));
> >> +               dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
> >> +               dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
> >> +       }
> > 
> > Does the mutex need to be held while waiting for ready?
> 
> Yes, to maintain consistency because inside the dcc_ready function, 
> there is access to dcc_drvdata structure set
> on the platform device.

Is the drvdata going to be modified somewhere else?

> >> +
> >> +               dev_info(drvdata->dev, "All values written to 
> >> enable.\n");
> > 
> > Debug print?
> 
> Ack
> 
> > 
> >> +               /* Make sure all config is written in sram */
> >> +               mb();
> > 
> > This won't work as intended.
> 
> This was called to prevent instruction reordering if the driver runs on 
> multiple
> CPU cores. As the hardware manipulation has to be done sequentially 
> before the
> trigger is set. Kindly let me know the concern in this case.

Device I/O with the proper accessors is sequential even if the process
moves to a different CPU. Is that what you're worried about? The comment
says "make sure it is written to sram", which should be achieved by
reading some register back from the device after all the writes so that
the driver knows the writes have been posted to the device. I believe
this mb() is doing nothing.

> 
> > 
> >> +
> >> +               drvdata->enable[list] = true;
> >> +
> >> +               /* 5. Configure trigger */
> >> +               dcc_writel(drvdata, BIT(9), DCC_LL_CFG(list));
> >> +       }
> >> +
> >> +err:
> >> +       mutex_unlock(&drvdata->mutex);
> >> +       return ret;
> >> +}
> >> +
> >> +static void dcc_disable(struct dcc_drvdata *drvdata)
> >> +{
> >> +       int curr_list;
> >> +
> >> +       mutex_lock(&drvdata->mutex);
> >> +
> >> +       if (!dcc_ready(drvdata))
> >> +               dev_err(drvdata->dev, "DCC is not ready Disabling 
> >> DCC...\n");
> > 
> > Is that two sentences? And a debug print?
> 
> Ack.
> 
> > 
> >> +
> >> +       for (curr_list = 0; curr_list < drvdata->nr_link_list; 
> >> curr_list++) {
> >> +               if (!drvdata->enable[curr_list])
> >> +                       continue;
> >> +               dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list));
> >> +               dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list));
> >> +               dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list));
> >> +               dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
> >> +               drvdata->enable[curr_list] = false;
> >> +       }
> >> +       memset_io(drvdata->ram_base, 0, drvdata->ram_size);
> >> +       drvdata->ram_cfg = 0;
> >> +       drvdata->ram_start = 0;
> >> +       mutex_unlock(&drvdata->mutex);
> >> +}
> >> +
> >> +static ssize_t curr_list_show(struct device *dev,
> >> +       struct device_attribute *attr, char *buf)
> >> +{
> >> +       int ret;
> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> >> +
> >> +       mutex_lock(&drvdata->mutex);
> >> +       if (drvdata->curr_list == DCC_INVALID_LINK_LIST) {
> >> +               dev_err(dev, "curr_list is not set.\n");
> >> +               ret = -EINVAL;
> >> +               goto err;
> >> +       }
> >> +
> >> +       ret = scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->curr_list);
> >> +err:
> >> +       mutex_unlock(&drvdata->mutex);
> >> +       return ret;
> >> +}
> >> +
> >> +static ssize_t curr_list_store(struct device *dev,
> >> +                                               struct 
> >> device_attribute *attr,
> >> +                                               const char *buf, 
> >> size_t size)
> >> +{
> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> >> +       unsigned long val;
> >> +       u32 lock_reg;
> >> +       bool dcc_enable = false;
> >> +
> >> +       if (kstrtoul(buf, 16, &val))
> >> +               return -EINVAL;
> >> +
> >> +       if (val >= drvdata->nr_link_list)
> >> +               return -EINVAL;
> >> +
> >> +       mutex_lock(&drvdata->mutex);
> >> +
> >> +       dcc_enable = is_dcc_enabled(drvdata);
> >> +       if (drvdata->curr_list != DCC_INVALID_LINK_LIST && dcc_enable) 
> >> {
> >> +               dev_err(drvdata->dev, "DCC is enabled, please disable 
> >> it first.\n");
> >> +               mutex_unlock(&drvdata->mutex);
> >> +               return -EINVAL;
> >> +       }
> >> +
> >> +       lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
> >> +       if (lock_reg & 0x1) {
> >> +               dev_err(drvdata->dev, "DCC linked list is already 
> >> configured\n");
> >> +               mutex_unlock(&drvdata->mutex);
> >> +               return -EINVAL;
> >> +       }
> >> +       drvdata->curr_list = val;
> >> +       mutex_unlock(&drvdata->mutex);
> >> +
> >> +       return size;
> >> +}
> >> +
> >> +static DEVICE_ATTR_RW(curr_list);
> >> +
> >> +
> >> +static ssize_t trigger_store(struct device *dev,
> >> +                                       struct device_attribute *attr,
> >> +                                       const char *buf, size_t size)
> >> +{
> >> +       int ret = 0;
> >> +       unsigned long val;
> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> >> +
> >> +       if (kstrtoul(buf, 16, &val))
> >> +               return -EINVAL;
> >> +       if (val != 1)
> >> +               return -EINVAL;
> >> +
> >> +       ret = dcc_sw_trigger(drvdata);
> >> +       if (!ret)
> >> +               ret = size;
> >> +
> >> +       return ret;
> >> +}
> >> +static DEVICE_ATTR_WO(trigger);
> >> +
> >> +static ssize_t enable_show(struct device *dev,
> >> +       struct device_attribute *attr, char *buf)
> >> +{
> >> +       int ret;
> >> +       bool dcc_enable = false;
> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> >> +
> >> +       mutex_lock(&drvdata->mutex);
> >> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> >> +               dev_err(dev, "Select link list to program using 
> >> curr_list\n");
> >> +               ret = -EINVAL;
> >> +               goto err;
> >> +       }
> >> +
> >> +       dcc_enable = is_dcc_enabled(drvdata);
> >> +
> >> +       ret = scnprintf(buf, PAGE_SIZE, "%u\n",
> >> +                               (unsigned int)dcc_enable);
> >> +err:
> >> +       mutex_unlock(&drvdata->mutex);
> > 
> > What does the mutex being held serve here?
> 
> As mentioned earlier, the mutex has been used while accessing 
> dcc_drvdata structure.
> 

And what purpose does it serve? I suppose curr_list can be modified? But
then when this function returns it could be disabled before userspace
sees the value so I'm still lost why we care to hold the lock this long.

> > 
> >> +       return ret;
> >> +}
> >> +
> >> +static ssize_t enable_store(struct device *dev,
> >> +                               struct device_attribute *attr,
> >> +                               const char *buf, size_t size)
> >> +{
> >> +       int ret = 0;
> >> +       unsigned long val;
> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> >> +
> >> +       if (kstrtoul(buf, 16, &val))
> >> +               return -EINVAL;
> >> +
> >> +       if (val)
> >> +               ret = dcc_enable(drvdata);
> >> +       else
> >> +               dcc_disable(drvdata);
> >> +
> >> +       if (!ret)
> >> +               ret = size;
> >> +
> >> +       return ret;
> >> +
> >> +}
> >> +
> >> +static DEVICE_ATTR_RW(enable);
> >> +
> >> +static ssize_t config_show(struct device *dev,
> >> +       struct device_attribute *attr, char *buf)
> >> +{
> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
> >> +       struct dcc_config_entry *entry;
> >> +       char local_buf[64];
> >> +       int len = 0, count = 0;
> >> +
> >> +       buf[0] = '\0';
> > 
> > Why?
> 
> The strlcat function is used here to concatenate the buffer with the 
> config values.
> The strlcat function in C needs a NULL terminated string both as it's 
> source and
> destination. That's why this has been initialized with NULL termination.
> 

sysfs files shall be one value per file, i.e. something that a machine
reads. This function looks like a debugfs function.

> 
> > 
> >> +
> >> +       mutex_lock(&drvdata->mutex);
> >> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
> >> +               dev_err(dev, "Select link list to program using 
> >> curr_list\n");
> >> +               count = -EINVAL;
> >> +               goto err;
> >> +       }
> >> +
> >> +       list_for_each_entry(entry,
> >> +       &drvdata->cfg_head[drvdata->curr_list], list) {
> >> +               switch (entry->desc_type) {
> >> +               case DCC_READ_WRITE_TYPE:
> >> +                       len = snprintf(local_buf, 64, "Index: 0x%x, 
> >> mask: 0x%x, val: 0x%x\n",
> >> +                               entry->index, entry->mask, 
> >> entry->write_val);
> >> +                       break;
> >> +               case DCC_LOOP_TYPE:
> >> +                       len = snprintf(local_buf, 64, "Index: 0x%x, 
> >> Loop: %d\n",
> >> +                               entry->index, entry->loop_cnt);
> >> +                       break;
> >> +               case DCC_WRITE_TYPE:
> >> +                       len = snprintf(local_buf, 64,
> >> +                               "Write Index: 0x%x, Base: 0x%x, 
> >> Offset: 0x%x, len: 0x%x APB: %d\n",
> >> +                               entry->index, entry->base, 
> >> entry->offset, entry->len,
> >> +                               entry->apb_bus);
> >> +                       break;
> >> +               default:
> >> +                       len = snprintf(local_buf, 64,
> >> +                               "Read Index: 0x%x, Base: 0x%x, Offset: 
> >> 0x%x, len: 0x%x APB: %d\n",
> >> +                               entry->index, entry->base, 
> >> entry->offset,
> >> +                               entry->len, entry->apb_bus);
> >> +               }
> >> +
> >> +               if ((count + len) > PAGE_SIZE) {
> >> +                       dev_err(dev, "DCC: Couldn't write complete 
> >> config\n");
> >> +                       break;
> >> +               }
> >> +               strlcat(buf, local_buf, PAGE_SIZE);
> >> +               count += len;
> >> +       }
> >> +
> >> +err:
> >> +       mutex_unlock(&drvdata->mutex);
> >> +       return count;
> >> +}
> > 
> >> +
> >> +       /* EOF check */
> >> +       if (drvdata->ram_size <= *ppos)
> >> +               return 0;
> >> +
> >> +       if ((*ppos + len) > drvdata->ram_size)
> >> +               len = (drvdata->ram_size - *ppos);
> >> +
> >> +       buf = kzalloc(len, GFP_KERNEL);
> >> +       if (!buf)
> >> +               return -ENOMEM;
> >> +
> >> +       memcpy_fromio(buf, drvdata->ram_base + *ppos, len);
> >> +
> >> +       if (copy_to_user(data, buf, len)) {
> > 
> > Is there any sort of memcpy_fromio_to_user() API? That would avoid the
> > extra buffer allocation by copying to userspace in the readl loop.
> 
> No. For directly copying io data to userspace we need to use direct I/O 
> which is used for
> special cases like tape drivers. In this case the complexity of using it 
> outweighs it's
> advantages. Also this is a fixed transfer of data in the form of 
> dcc_sram content rather
> than bulk transfers.

Tape drivers? Huh? Can you please look into adding a
memcpy_fromio_to_user() API that does this without allocating memory for
a buffer?

> 
> > 
> >> +               dcc->loopoff = DCC_FIX_LOOP_OFFSET;
> >> +       else
> >> +               dcc->loopoff = get_bitmask_order((dcc->ram_size +
> >> +                               dcc->ram_offset) / 4 - 1);
> >> +
> >> +       mutex_init(&dcc->mutex);
> >> +       dcc->enable = devm_kcalloc(dev, dcc->nr_link_list,
> >> +                       sizeof(bool), GFP_KERNEL);
> >> +       if (!dcc->enable)
> >> +               return -ENOMEM;
> >> +
> >> +       dcc->configured = devm_kcalloc(dev, dcc->nr_link_list,
> >> +                       sizeof(bool), GFP_KERNEL);
> >> +       if (!dcc->configured)
> >> +               return -ENOMEM;
> >> +
> >> +       dcc->nr_config = devm_kcalloc(dev, dcc->nr_link_list,
> >> +                       sizeof(u32), GFP_KERNEL);
> >> +       if (!dcc->nr_config)
> >> +               return -ENOMEM;
> >> +
> >> +       dcc->cfg_head = devm_kcalloc(dev, dcc->nr_link_list,
> >> +                       sizeof(struct list_head), GFP_KERNEL);
> >> +       if (!dcc->cfg_head)
> >> +               return -ENOMEM;
> > 
> > These are a lot of allocations. Any chance we can do one instead of 
> > this
> > many?
> 
> All these variable have predefined requirement of sizes
> so they need to be allocated separately.

Gather requirements, do some addition, and then allocate one chunk of
memory?

Re: [PATCH V2 3/5] DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver

[Stephen Boyd]

Quoting schowdhu@codeaurora.org (2021-04-01 08:42:50)
> On 2021-03-30 01:39, Stephen Boyd wrote:
> > Quoting Souradeep Chowdhury (2021-03-25 01:02:34)
> >> The DCC is a DMA engine designed to store register values either in
> >> case of a system crash or in case of software triggers manually done
> >> by the user.Using DCC hardware and the sysfs interface of the driver
> >> the user can exploit various functionalities of DCC.The user can 
> >> specify
> >> the register addresses,the values of which is stored by DCC in it's
> >> dedicated SRAM.The register addresses can be used either to read from,
> >> write to,first read and store value and then write or to loop.All 
> >> these
> >> options can be exploited using the sysfs interface given to the user.
> >> Following are the sysfs interfaces exposed in DCC driver which are
> >> documented
> >> 1)trigger
> >> 2)config
> >> 3)config_write
> >> 4)config_reset
> >> 5)enable
> >> 6)rd_mod_wr
> >> 7)loop
> >> 
> >> Signed-off-by: Souradeep Chowdhury <schowdhu@codeaurora.org>
> >> ---
> >>  Documentation/ABI/testing/sysfs-driver-dcc | 114 
> >> +++++++++++++++++++++++++++++
> > 
> > Please combine this with the driver patch.
> 
> Ack
> 
> > 
> >>  1 file changed, 114 insertions(+)
> >>  create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc
> > 
> > Perhaps this should be an ioctl interface instead of a sysfs interface?
> 
> The reasons for choosing sysfs over ioctl is as follows

Cool, please add these details to the commit text.

> 
> 
> i) As can be seen from the sysfs attribute descriptions, most of it does 
> basic hardware manipulations like dcc_enable, dcc_disable, config reset 
> etc. As a result sysfs is preferred over ioctl as we just need to enter 
> a 0 or 1
> signal in such cases.
> 
> ii) Existing similar debug hardwares are there for which drivers have 
> been written using sysfs interface. One such example is the 
> coresight-etm-trace driver. Following is the link for reference
> 
> https://www.kernel.org/doc/html/latest/trace/coresight/coresight-etm4x-reference.html

I wasn't deeply involved but I recall that the whole coresight sysfs
interface was disliked and it mostly got rewritten to go through the
perf tool instead. Pointing to the coresight sysfs API is not the best
approach here.

Maybe a closer analog would be the watchdog subsystem, which is ioctl
based and uses a character device like /dev/watchdog. Watchdogs are
simple debug features that reboot the system when everything goes wrong.
This looks like a hardware block that can be used to gather information
when the watchdog fires.

Reading the doc closer it is quite frightening that a device like this
can let you read registers in the hardware on-demand and even store
values of registers over time. This is like /dev/mem on steroids. This
needs to be highly restricted as it sounds like it could be used to
snoop on security keys that are set in the hardware or secrets stored in
memory. Is the hardware restricted at all in what it can read?

Re: [PATCH V2 2/5] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)

[schowdhu]

On 2021-04-02 06:20, Stephen Boyd wrote:
> Quoting schowdhu@codeaurora.org (2021-04-01 07:04:07)
>> On 2021-03-30 01:35, Stephen Boyd wrote:
>> > Quoting Souradeep Chowdhury (2021-03-25 01:02:33)
>> >> diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c
>> >> new file mode 100644
>> >> index 0000000..a55d8ca7
>> >> --- /dev/null
>> >> +++ b/drivers/soc/qcom/dcc.c
>> >> @@ -0,0 +1,1549 @@
> [..]
>> >
>> >> +       void __iomem            *base;
>> >> +       u32                     reg_size;
>> >> +       struct device           *dev;
>> >> +       struct mutex            mutex;
>> >
>> > In particular what this mutex is protecting.
>> 
>> Ack. The mutex is used to protect the access as well as manipulation 
>> of
>> the main instance of dcc_drvdata structure
>> initialized during probe time. This structure contains the useful 
>> driver
>> data information and is set using the call
>> platform_set_drvdata(pdev, drvdata) which links this data to the
>> platform device and hence needs to be protected via
>> mutex locks. The same convention is followed across other similar
>> drivers exposing userspace like the llcc driver.
> 
> The region that the mutex is protecting seems quite large. That's
> probably because I don't understand the driver.
> 
>> >
>> >> +
>> >> +       mutex_lock(&drvdata->mutex);
>> >> +
>> >> +       for (curr_list = 0; curr_list < drvdata->nr_link_list;
>> >> curr_list++) {
>> >> +               if (!drvdata->enable[curr_list])
>> >> +                       continue;
>> >> +               ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
>> >> +               tmp_ll_cfg = ll_cfg & ~BIT(9);
>> >> +               dcc_writel(drvdata, tmp_ll_cfg,
>> >> DCC_LL_CFG(curr_list));
>> >> +               dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
>> >> +               dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
>> >> +       }
>> >
>> > Does the mutex need to be held while waiting for ready?
>> 
>> Yes, to maintain consistency because inside the dcc_ready function,
>> there is access to dcc_drvdata structure set
>> on the platform device.
> 
> Is the drvdata going to be modified somewhere else?

Ack. Not considering holding mutex locks for Read operations.

> 
>> >> +
>> >> +               dev_info(drvdata->dev, "All values written to
>> >> enable.\n");
>> >
>> > Debug print?
>> 
>> Ack
>> 
>> >
>> >> +               /* Make sure all config is written in sram */
>> >> +               mb();
>> >
>> > This won't work as intended.
>> 
>> This was called to prevent instruction reordering if the driver runs 
>> on
>> multiple
>> CPU cores. As the hardware manipulation has to be done sequentially
>> before the
>> trigger is set. Kindly let me know the concern in this case.
> 
> Device I/O with the proper accessors is sequential even if the process
> moves to a different CPU. Is that what you're worried about? The 
> comment
> says "make sure it is written to sram", which should be achieved by
> reading some register back from the device after all the writes so that
> the driver knows the writes have been posted to the device. I believe
> this mb() is doing nothing.

Ack

> 
>> 
>> >
>> >> +
>> >> +               drvdata->enable[list] = true;
>> >> +
>> >> +               /* 5. Configure trigger */
>> >> +               dcc_writel(drvdata, BIT(9), DCC_LL_CFG(list));
>> >> +       }
>> >> +
>> >> +err:
>> >> +       mutex_unlock(&drvdata->mutex);
>> >> +       return ret;
>> >> +}
>> >> +
>> >> +static void dcc_disable(struct dcc_drvdata *drvdata)
>> >> +{
>> >> +       int curr_list;
>> >> +
>> >> +       mutex_lock(&drvdata->mutex);
>> >> +
>> >> +       if (!dcc_ready(drvdata))
>> >> +               dev_err(drvdata->dev, "DCC is not ready Disabling
>> >> DCC...\n");
>> >
>> > Is that two sentences? And a debug print?
>> 
>> Ack.
>> 
>> >
>> >> +
>> >> +       for (curr_list = 0; curr_list < drvdata->nr_link_list;
>> >> curr_list++) {
>> >> +               if (!drvdata->enable[curr_list])
>> >> +                       continue;
>> >> +               dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list));
>> >> +               dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list));
>> >> +               dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list));
>> >> +               dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
>> >> +               drvdata->enable[curr_list] = false;
>> >> +       }
>> >> +       memset_io(drvdata->ram_base, 0, drvdata->ram_size);
>> >> +       drvdata->ram_cfg = 0;
>> >> +       drvdata->ram_start = 0;
>> >> +       mutex_unlock(&drvdata->mutex);
>> >> +}
>> >> +
>> >> +static ssize_t curr_list_show(struct device *dev,
>> >> +       struct device_attribute *attr, char *buf)
>> >> +{
>> >> +       int ret;
>> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> >> +
>> >> +       mutex_lock(&drvdata->mutex);
>> >> +       if (drvdata->curr_list == DCC_INVALID_LINK_LIST) {
>> >> +               dev_err(dev, "curr_list is not set.\n");
>> >> +               ret = -EINVAL;
>> >> +               goto err;
>> >> +       }
>> >> +
>> >> +       ret = scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->curr_list);
>> >> +err:
>> >> +       mutex_unlock(&drvdata->mutex);
>> >> +       return ret;
>> >> +}
>> >> +
>> >> +static ssize_t curr_list_store(struct device *dev,
>> >> +                                               struct
>> >> device_attribute *attr,
>> >> +                                               const char *buf,
>> >> size_t size)
>> >> +{
>> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> >> +       unsigned long val;
>> >> +       u32 lock_reg;
>> >> +       bool dcc_enable = false;
>> >> +
>> >> +       if (kstrtoul(buf, 16, &val))
>> >> +               return -EINVAL;
>> >> +
>> >> +       if (val >= drvdata->nr_link_list)
>> >> +               return -EINVAL;
>> >> +
>> >> +       mutex_lock(&drvdata->mutex);
>> >> +
>> >> +       dcc_enable = is_dcc_enabled(drvdata);
>> >> +       if (drvdata->curr_list != DCC_INVALID_LINK_LIST && dcc_enable)
>> >> {
>> >> +               dev_err(drvdata->dev, "DCC is enabled, please disable
>> >> it first.\n");
>> >> +               mutex_unlock(&drvdata->mutex);
>> >> +               return -EINVAL;
>> >> +       }
>> >> +
>> >> +       lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
>> >> +       if (lock_reg & 0x1) {
>> >> +               dev_err(drvdata->dev, "DCC linked list is already
>> >> configured\n");
>> >> +               mutex_unlock(&drvdata->mutex);
>> >> +               return -EINVAL;
>> >> +       }
>> >> +       drvdata->curr_list = val;
>> >> +       mutex_unlock(&drvdata->mutex);
>> >> +
>> >> +       return size;
>> >> +}
>> >> +
>> >> +static DEVICE_ATTR_RW(curr_list);
>> >> +
>> >> +
>> >> +static ssize_t trigger_store(struct device *dev,
>> >> +                                       struct device_attribute *attr,
>> >> +                                       const char *buf, size_t size)
>> >> +{
>> >> +       int ret = 0;
>> >> +       unsigned long val;
>> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> >> +
>> >> +       if (kstrtoul(buf, 16, &val))
>> >> +               return -EINVAL;
>> >> +       if (val != 1)
>> >> +               return -EINVAL;
>> >> +
>> >> +       ret = dcc_sw_trigger(drvdata);
>> >> +       if (!ret)
>> >> +               ret = size;
>> >> +
>> >> +       return ret;
>> >> +}
>> >> +static DEVICE_ATTR_WO(trigger);
>> >> +
>> >> +static ssize_t enable_show(struct device *dev,
>> >> +       struct device_attribute *attr, char *buf)
>> >> +{
>> >> +       int ret;
>> >> +       bool dcc_enable = false;
>> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> >> +
>> >> +       mutex_lock(&drvdata->mutex);
>> >> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> >> +               dev_err(dev, "Select link list to program using
>> >> curr_list\n");
>> >> +               ret = -EINVAL;
>> >> +               goto err;
>> >> +       }
>> >> +
>> >> +       dcc_enable = is_dcc_enabled(drvdata);
>> >> +
>> >> +       ret = scnprintf(buf, PAGE_SIZE, "%u\n",
>> >> +                               (unsigned int)dcc_enable);
>> >> +err:
>> >> +       mutex_unlock(&drvdata->mutex);
>> >
>> > What does the mutex being held serve here?
>> 
>> As mentioned earlier, the mutex has been used while accessing
>> dcc_drvdata structure.
>> 
> 
> And what purpose does it serve? I suppose curr_list can be modified? 
> But
> then when this function returns it could be disabled before userspace
> sees the value so I'm still lost why we care to hold the lock this 
> long.

Ack.

> 
>> >
>> >> +       return ret;
>> >> +}
>> >> +
>> >> +static ssize_t enable_store(struct device *dev,
>> >> +                               struct device_attribute *attr,
>> >> +                               const char *buf, size_t size)
>> >> +{
>> >> +       int ret = 0;
>> >> +       unsigned long val;
>> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> >> +
>> >> +       if (kstrtoul(buf, 16, &val))
>> >> +               return -EINVAL;
>> >> +
>> >> +       if (val)
>> >> +               ret = dcc_enable(drvdata);
>> >> +       else
>> >> +               dcc_disable(drvdata);
>> >> +
>> >> +       if (!ret)
>> >> +               ret = size;
>> >> +
>> >> +       return ret;
>> >> +
>> >> +}
>> >> +
>> >> +static DEVICE_ATTR_RW(enable);
>> >> +
>> >> +static ssize_t config_show(struct device *dev,
>> >> +       struct device_attribute *attr, char *buf)
>> >> +{
>> >> +       struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
>> >> +       struct dcc_config_entry *entry;
>> >> +       char local_buf[64];
>> >> +       int len = 0, count = 0;
>> >> +
>> >> +       buf[0] = '\0';
>> >
>> > Why?
>> 
>> The strlcat function is used here to concatenate the buffer with the
>> config values.
>> The strlcat function in C needs a NULL terminated string both as it's
>> source and
>> destination. That's why this has been initialized with NULL 
>> termination.
>> 
> 
> sysfs files shall be one value per file, i.e. something that a machine
> reads. This function looks like a debugfs function.

Ack

> 
>> 
>> >
>> >> +
>> >> +       mutex_lock(&drvdata->mutex);
>> >> +       if (drvdata->curr_list >= drvdata->nr_link_list) {
>> >> +               dev_err(dev, "Select link list to program using
>> >> curr_list\n");
>> >> +               count = -EINVAL;
>> >> +               goto err;
>> >> +       }
>> >> +
>> >> +       list_for_each_entry(entry,
>> >> +       &drvdata->cfg_head[drvdata->curr_list], list) {
>> >> +               switch (entry->desc_type) {
>> >> +               case DCC_READ_WRITE_TYPE:
>> >> +                       len = snprintf(local_buf, 64, "Index: 0x%x,
>> >> mask: 0x%x, val: 0x%x\n",
>> >> +                               entry->index, entry->mask,
>> >> entry->write_val);
>> >> +                       break;
>> >> +               case DCC_LOOP_TYPE:
>> >> +                       len = snprintf(local_buf, 64, "Index: 0x%x,
>> >> Loop: %d\n",
>> >> +                               entry->index, entry->loop_cnt);
>> >> +                       break;
>> >> +               case DCC_WRITE_TYPE:
>> >> +                       len = snprintf(local_buf, 64,
>> >> +                               "Write Index: 0x%x, Base: 0x%x,
>> >> Offset: 0x%x, len: 0x%x APB: %d\n",
>> >> +                               entry->index, entry->base,
>> >> entry->offset, entry->len,
>> >> +                               entry->apb_bus);
>> >> +                       break;
>> >> +               default:
>> >> +                       len = snprintf(local_buf, 64,
>> >> +                               "Read Index: 0x%x, Base: 0x%x, Offset:
>> >> 0x%x, len: 0x%x APB: %d\n",
>> >> +                               entry->index, entry->base,
>> >> entry->offset,
>> >> +                               entry->len, entry->apb_bus);
>> >> +               }
>> >> +
>> >> +               if ((count + len) > PAGE_SIZE) {
>> >> +                       dev_err(dev, "DCC: Couldn't write complete
>> >> config\n");
>> >> +                       break;
>> >> +               }
>> >> +               strlcat(buf, local_buf, PAGE_SIZE);
>> >> +               count += len;
>> >> +       }
>> >> +
>> >> +err:
>> >> +       mutex_unlock(&drvdata->mutex);
>> >> +       return count;
>> >> +}
>> >
>> >> +
>> >> +       /* EOF check */
>> >> +       if (drvdata->ram_size <= *ppos)
>> >> +               return 0;
>> >> +
>> >> +       if ((*ppos + len) > drvdata->ram_size)
>> >> +               len = (drvdata->ram_size - *ppos);
>> >> +
>> >> +       buf = kzalloc(len, GFP_KERNEL);
>> >> +       if (!buf)
>> >> +               return -ENOMEM;
>> >> +
>> >> +       memcpy_fromio(buf, drvdata->ram_base + *ppos, len);
>> >> +
>> >> +       if (copy_to_user(data, buf, len)) {
>> >
>> > Is there any sort of memcpy_fromio_to_user() API? That would avoid the
>> > extra buffer allocation by copying to userspace in the readl loop.
>> 
>> No. For directly copying io data to userspace we need to use direct 
>> I/O
>> which is used for
>> special cases like tape drivers. In this case the complexity of using 
>> it
>> outweighs it's
>> advantages. Also this is a fixed transfer of data in the form of
>> dcc_sram content rather
>> than bulk transfers.
> 
> Tape drivers? Huh? Can you please look into adding a
> memcpy_fromio_to_user() API that does this without allocating memory 
> for
> a buffer?

So in case of fixed read and writes, buffered i/o is more efficient than 
direct
i/o. In this case an effort to copy directly from i/o space to user 
space might
introduce latency. Let me know if I am missing anything here.

> 
>> 
>> >
>> >> +               dcc->loopoff = DCC_FIX_LOOP_OFFSET;
>> >> +       else
>> >> +               dcc->loopoff = get_bitmask_order((dcc->ram_size +
>> >> +                               dcc->ram_offset) / 4 - 1);
>> >> +
>> >> +       mutex_init(&dcc->mutex);
>> >> +       dcc->enable = devm_kcalloc(dev, dcc->nr_link_list,
>> >> +                       sizeof(bool), GFP_KERNEL);
>> >> +       if (!dcc->enable)
>> >> +               return -ENOMEM;
>> >> +
>> >> +       dcc->configured = devm_kcalloc(dev, dcc->nr_link_list,
>> >> +                       sizeof(bool), GFP_KERNEL);
>> >> +       if (!dcc->configured)
>> >> +               return -ENOMEM;
>> >> +
>> >> +       dcc->nr_config = devm_kcalloc(dev, dcc->nr_link_list,
>> >> +                       sizeof(u32), GFP_KERNEL);
>> >> +       if (!dcc->nr_config)
>> >> +               return -ENOMEM;
>> >> +
>> >> +       dcc->cfg_head = devm_kcalloc(dev, dcc->nr_link_list,
>> >> +                       sizeof(struct list_head), GFP_KERNEL);
>> >> +       if (!dcc->cfg_head)
>> >> +               return -ENOMEM;
>> >
>> > These are a lot of allocations. Any chance we can do one instead of
>> > this
>> > many?
>> 
>> All these variable have predefined requirement of sizes
>> so they need to be allocated separately.
> 
> Gather requirements, do some addition, and then allocate one chunk of
> memory?

Ack