From: "Heiko Stübner" <heiko@sntech.de>
To: wefu@redhat.com, linux-riscv@lists.infradead.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
gordan.markus@canonical.com, guoren@linux.alibaba.com,
arnd@arndb.de, wens@csie.org, maxime@cerno.tech,
dlustig@nvidia.com, gfavor@ventanamicro.com,
andrea.mondelli@huawei.com, behrensj@mit.edu,
xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr,
allen.baum@esperantotech.com, jscheid@ventanamicro.com,
rtrauben@gmail.com, "Anup Patel" <anup@brainfault.org>,
"Rob Herring" <robh+dt@kernel.org>,
anup.patel@wdc.com, atishp04@gmail.com, palmer@dabbelt.com,
guoren@kernel.org, christoph.muellner@vrull.eu,
philipp.tomsich@vrull.eu, hch@lst.de, liush@allwinnertech.com,
lazyparser@gmail.com, drew@beagleboard.org,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
"Heiko Stübner" <heiko@sntech.de>
Subject: Re: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt
Date: Tue, 30 Nov 2021 13:07:37 +0100 [thread overview]
Message-ID: <1909580.k68io2XIxi@diego> (raw)
In-Reply-To: <9930802.MB9u6SvQ6m@diego>
Am Montag, 29. November 2021, 13:06:23 CET schrieb Heiko Stübner:
> Am Montag, 29. November 2021, 09:54:39 CET schrieb Heinrich Schuchardt:
> > On 11/29/21 02:40, wefu@redhat.com wrote:
> > > From: Wei Fu <wefu@redhat.com>
> > >
> > > Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt"
> > > in the DT mmu node. Update dt-bindings related property here.
> > >
> > > Signed-off-by: Wei Fu <wefu@redhat.com>
> > > Co-developed-by: Guo Ren <guoren@kernel.org>
> > > Signed-off-by: Guo Ren <guoren@kernel.org>
> > > Cc: Anup Patel <anup@brainfault.org>
> > > Cc: Palmer Dabbelt <palmer@dabbelt.com>
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > ---
> > > Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > index aa5fb64d57eb..9ff9cbdd8a85 100644
> > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > @@ -63,6 +63,16 @@ properties:
> > > - riscv,sv48
> > > - riscv,none
> > >
> > > + mmu:
> >
> > Shouldn't we keep the items be in alphabetic order, i.e. mmu before
> > mmu-type?
> >
> > > + description:
> > > + Describes the CPU's MMU Standard Extensions support.
> > > + These values originate from the RISC-V Privileged
> > > + Specification document, available from
> > > + https://riscv.org/specifications/
> > > + $ref: '/schemas/types.yaml#/definitions/string'
> > > + enum:
> > > + - riscv,svpmbt
> >
> > The privileged specification has multiple MMU related extensions:
> > Svnapot, Svpbmt, Svinval. Shall they all be modeled in this enum?
>
> I remember in some earlier version some way back there was the
> suggestion of using a sub-node instead and then adding boolean
> properties for the supported extensions.
>
> Aka something like
> mmu {
> riscv,svpbmt;
> };
For the record, I'm talking about the mail from september
https://lore.kernel.org/linux-riscv/CAAeLtUChjjzG+P8yg45GLZMJy5UR2K5RRBoLFVZhtOaZ5pPtEA@mail.gmail.com/
So having a sub-node would make adding future extensions
way nicer.
>
> Which I guess would be a lot nicer. Also right now there is string-
> comparison done on the code side, which would look way easier
> when just looking for booleans in the dt instead.
>
> Also isn't an enum a "one-of" selection, so wouldn't work directly
> for multiple extensions?
>
>
> Heiko
>
>
> >
> > Best regards
> >
> > Heinrich
> >
> > > +
> > > riscv,isa:
> > > description:
> > > Identifies the specific RISC-V instruction set architecture
> > >
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
>
>
>
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
next prev parent reply other threads:[~2021-11-30 12:07 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-29 1:40 [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports wefu
2021-11-29 1:40 ` [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt wefu
2021-11-29 8:54 ` Heinrich Schuchardt
2021-11-29 12:06 ` Heiko Stübner
2021-11-30 12:07 ` Heiko Stübner [this message]
2021-11-30 13:17 ` Jessica Clarke
2021-11-30 13:27 ` Heiko Stübner
2021-11-30 13:59 ` Jessica Clarke
2021-11-30 15:01 ` Philipp Tomsich
2021-11-30 16:12 ` Jessica Clarke
2021-12-01 1:21 ` Atish Patra
2021-12-01 3:06 ` Tsukasa OI
2021-12-01 8:15 ` Atish Patra
2021-12-01 8:30 ` Heiko Stübner
[not found] ` <CAELrHRDb9oeu_FokyhUFQ+Yu27=4xqvPdz4=08MXQzh3Bj2Myw@mail.gmail.com>
2021-12-01 10:20 ` Heiko Stübner
2021-12-01 11:05 ` Philipp Tomsich
2021-12-01 13:39 ` Jessica Clarke
2021-12-02 1:31 ` Tsukasa OI
2021-12-02 1:55 ` Atish Patra
2021-12-01 13:28 ` Heiko Stübner
2021-12-02 1:59 ` Atish Patra
2021-11-30 18:45 ` Heiko Stübner
2021-12-01 2:58 ` Wei Fu
2021-11-29 1:40 ` [PATCH V4 2/2] riscv: add RISC-V Svpbmt extension supports wefu
2021-11-29 10:48 ` Alexandre Ghiti
2021-11-29 13:36 ` Jisheng Zhang
2021-12-01 5:05 ` Wei Fu
2021-12-01 6:18 ` Anup Patel
2021-12-01 13:29 ` Jisheng Zhang
2021-12-03 9:12 ` Wei Fu
2021-11-30 10:18 ` Guo Ren
2021-12-01 3:03 ` Wei Fu
2021-11-30 18:46 ` Heiko Stübner
2021-12-01 3:00 ` Wei Fu
2021-11-29 13:33 ` [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Jisheng Zhang
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