From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934141AbcHDTLI (ORCPT ); Thu, 4 Aug 2016 15:11:08 -0400 Received: from gloria.sntech.de ([95.129.55.99]:46998 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932168AbcHDTLF (ORCPT ); Thu, 4 Aug 2016 15:11:05 -0400 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Xing Zheng Cc: linux-rockchip@lists.infradead.org, dianders@chromium.org, briannorris@chromium.org, huangtao@rock-chips.com, zhangqing@rock-chips.com, frank.wang@rock-chips.com, wulf@rock-chips.com, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/7] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Date: Thu, 04 Aug 2016 21:10:47 +0200 Message-ID: <1918977.W0kRfKbZsD@diego> User-Agent: KMail/4.14.10 (Linux/4.6.0-1-amd64; KDE/4.14.22; x86_64; ; ) In-Reply-To: <1470122401-31934-3-git-send-email-zhengxing@rock-chips.com> References: <1470122401-31934-1-git-send-email-zhengxing@rock-chips.com> <1470122401-31934-3-git-send-email-zhengxing@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Xing, Am Dienstag, 2. August 2016, 15:19:56 schrieb Xing Zheng: > Export these source clocks for usbphy. > > Signed-off-by: Xing Zheng can you please provide a rationale why you need manual control over that intermediate clock? The two usbphys seem to use the clk_usb2phyX_ref clocks, generate the 480m clocks, but do not seem to need the clk_usbphyX_480m_src gates. The clk_usbphyX_480m_src clocks on the other hand only lead to the clk_usbphy_480m mux, so I'd like some explanation on what you want to achieve here :-) Thanks Heiko