RE: [PATCH v4 4/7] tpm: tpm_tis: Fix expected bit handling and send all bytes in one shot without last byte in exception

From: Benoit HOUYERE <benoit.houyere@st.com>
To: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>,
	"amirmizi6@gmail.com" <amirmizi6@gmail.com>
Cc: "Eyal.Cohen@nuvoton.com" <Eyal.Cohen@nuvoton.com>,
	"oshrialkoby85@gmail.com" <oshrialkoby85@gmail.com>,
	"alexander.steffen@infineon.com" <alexander.steffen@infineon.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"peterhuewe@gmx.de" <peterhuewe@gmx.de>,
	"jgg@ziepe.ca" <jgg@ziepe.ca>, "arnd@arndb.de" <arnd@arndb.de>,
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-integrity@vger.kernel.org"
	<linux-integrity@vger.kernel.org>,
	"oshri.alkoby@nuvoton.com" <oshri.alkoby@nuvoton.com>,
	"tmaimon77@gmail.com" <tmaimon77@gmail.com>,
	"gcwilson@us.ibm.com" <gcwilson@us.ibm.com>,
	"kgoldman@us.ibm.com" <kgoldman@us.ibm.com>,
	"Dan.Morav@nuvoton.com" <Dan.Morav@nuvoton.com>,
	"oren.tanami@nuvoton.com" <oren.tanami@nuvoton.com>,
	"shmulik.hager@nuvoton.com" <shmulik.hager@nuvoton.com>,
	"amir.mizinski@nuvoton.com" <amir.mizinski@nuvoton.com>,
	Olivier COLLART <olivier.collart@st.com>,
	Yves MAGNAUD <yves.magnaud@st.com>
Subject: RE: [PATCH v4 4/7] tpm: tpm_tis: Fix expected bit handling and send all bytes in one shot without last byte in exception
Date: Tue, 31 Mar 2020 21:34:28 +0000	[thread overview]
Message-ID: <19c8ae3023404ae9affcb1ce04b7ee4b@SFHDAG3NODE3.st.com> (raw)
In-Reply-To: <20200331121720.GB9284@linux.intel.com>

> On Tue, Mar 31, 2020 at 02:32:04PM +0300, amirmizi6@gmail.com wrote:
> > From: Amir Mizinski <amirmizi6@gmail.com>
> > 
> > Today, actual implementation for send massage is not correct. We check 
> > and loop only on TPM_STS.stsValid bit and next we single check 
> > TPM_STS.expect bit value.
> > TPM_STS.expected bit shall be checked in the same time of 
> > TPM_STS.stsValid, and should be repeated until timeout_A.
> > To aquire that, "wait_for_tpm_stat" function is modified to 
> > "wait_for_tpm_stat_result". this function read regulary status 
> > register and check bit defined by "mask" to reach value defined in "mask_result"
> > (that way a bit in mask can be checked if reached 1 or 0).
> > 
> > Respectively, to send message as defined in 
> >  TCG_DesignPrinciples_TPM2p0Driver_vp24_pubrev.pdf, all bytes should be 
> > sent in one shot instead of sending last byte in exception.
> > 
> > This improvment was suggested by Benoit Houyere.

>Use suggested-by tag.

>Also if something is not correct, please provide a fixes tag.

> You are speaking now in theoretical level, which we don't really care that much. Is this causing you real issues? If the answer is yes, please report them. If the > >answer is no, we don't need this.

> /Jarkko

I2C TPM specification introduce CRC calculation on TPM command bytes. CRC calculation take place from last byte acquired to  TPM_STS.expected bit reset (=0) .It introduces latency and actual incorrect implementation becomes visible now under I2C on the contrary before that's all. 
The case where TPM keeps TPM_STS.expected bit set  with TPM_STS.stsValid set after last byte reception is possible and is not an issue. It's not theoretical level, it's practical level now.