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Nikolaus Schaller" In-Reply-To: <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> Date: Wed, 22 Apr 2020 09:10:57 +0200 Cc: Tony Lindgren , Philipp Rossak , Jonathan Bakker , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , =?utf-8?Q?Beno=C3=AEt_Cousson?= , Paul Cercueil , Ralf Baechle , Paul Burton , James Hogan , Kukjin Kim , Krzysztof Kozlowski , Chen-Yu Tsai , Thomas Bogendoerfer , "open list:DRM PANEL DRIVERS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , linux-omap , OpenPVRSGX Linux Driver Group , Discussions about the Letux Kernel , kernel@pyra-handheld.com, linux-mips@vger.kernel.org, arm-soc , linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <1AA57A0C-48E6-49BB-BB9A-2AAFFB371BCD@goldelico.com> References: <20200415101008.zxzxca2vlfsefpdv@gilmour.lan> <2E3401F1-A106-4396-8FE6-51CAB72926A4@goldelico.com> <20200415130233.rgn7xrtwqicptke2@gilmour.lan> <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> <20200420073842.nx4xb3zqvu23arkc@gilmour.lan> <20200421112129.zjmkmzo3aftksgka@gilmour.lan> <20200421141543.GU37466@atomide.com> <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> To: Maxime Ripard X-Mailer: Apple Mail (2.3124) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Maxime, > Am 22.04.2020 um 08:58 schrieb Maxime Ripard : >=20 > On Tue, Apr 21, 2020 at 07:29:32PM +0200, H. Nikolaus Schaller wrote: >>=20 >>> Am 21.04.2020 um 16:15 schrieb Tony Lindgren : >>>=20 >>> * Maxime Ripard [200421 11:22]: >>>> On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote: >>>>> I had a look on genpd and I'm not really sure if that fits. >>>>>=20 >>>>> It is basically some bit that verify that the clocks should be = enabled or >>>>> disabled. >>>>=20 >>>> No, it can do much more than that. It's a framework to control the = SoCs power >>>> domains, so clocks might be a part of it, but most of the time it's = going to be >>>> about powering up a particular device. >>>=20 >>> Note that on omaps there are actually SoC module specific registers. >>=20 >> Ah, I see. This is of course a difference that the TI glue logic has >> its own registers in the same address range as the sgx and this can't >> be easily handled by a common sgx driver. >>=20 >> This indeed seems to be unique with omap. >>=20 >>> And there can be multiple devices within a single target module on >>> omaps. So the extra dts node and device is justified there. >>>=20 >>> For other SoCs, the SGX clocks are probably best handled directly >>> in pvr-drv.c PM runtime functions unless a custom hardware wrapper >>> with SoC specific registers exists. >>=20 >> That is why we need to evaluate what the better strategy is. >>=20 >> So we have >> a) omap which has a custom wrapper around the sgx >> b) others without, i.e. an empty (or pass-through) wrapper >>=20 >> Which one do we make the "standard" and which one the "exception"? >> What are good reasons for either one? >>=20 >>=20 >> I am currently in strong favour of a) being standard because it >> makes the pvr-drv.c simpler and really generic (independent of >> wrapping into any SoC). >>=20 >> This will likely avoid problems if we find more SoC with yet another >> scheme how the SGX clocks are wrapped. >>=20 >> It also allows to handle different number of clocks (A31 seems to >> need 4, Samsung, A83 and JZ4780 one) without changing the sgx = bindings >> or making big lists of conditionals. This variance would be handled >> outside the sgx core bindings and driver. >=20 > I disagree. Every other GPU binding and driver is handling that just = fine, and > the SGX is not special in any case here. Can you please better explain this? With example or a description or a proposal? I simply do not have your experience with "every other GPU" as you have. And I admit that I can't read from your statement what we should do to bring this topic forward. So please make a proposal how it should be in your view. BR and thanks, Nikolaus