* [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
@ 2012-09-04 13:09 Hebbar, Gururaja
2012-09-12 7:48 ` Hebbar, Gururaja
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Hebbar, Gururaja @ 2012-09-04 13:09 UTC (permalink / raw)
To: linux-omap, linux-mmc, svenkatr
Cc: rob.herring, linux-kernel, grant.likely, cjb, nsekhar,
sudhakar.raj, gururaja.hebbar
HSMMC IP on AM33xx need a special setting to handle High-speed cards.
Other platforms like TI81xx, OMAP4 may need this as-well. This depends
on the HSMMC IP timing closure done for the high speed cards.
>From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
The MMC/SD/SDIO output signals can be driven on either falling edge or
rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
to reach better timing performance, and thus to increase data transfer
frequency.
There are few pre-requisites for enabling the HSPE bit
- Controller should support High-Speed-Enable Bit and
- Controller should not be using DDR Mode and
- Controller should advertise that it supports High Speed in
capabilities register and
- MMC/SD clock coming out of controller > 25MHz
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
---
:100644 100644 be76a23... ed271fc... M Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
:100644 100644 eb3e4d5... 00c658b... M arch/arm/plat-omap/include/plat/mmc.h
:100644 100644 c3e96a2... 0e14834... M drivers/mmc/host/omap_hsmmc.c
.../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 1 +
arch/arm/plat-omap/include/plat/mmc.h | 1 +
drivers/mmc/host/omap_hsmmc.c | 30 +++++++++++++++++++-
3 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index be76a23..ed271fc 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -19,6 +19,7 @@ ti,dual-volt: boolean, supports dual voltage cards
"supply-name" examples are "vmmc", "vmmc_aux" etc
ti,non-removable: non-removable slot (like eMMC)
ti,needs-special-reset: Requires a special softreset sequence
+ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
Example:
mmc1: mmc@0x4809c000 {
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index eb3e4d5..00c658b 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -127,6 +127,7 @@ struct omap_mmc_platform_data {
/* we can put the features above into this variable */
#define HSMMC_HAS_PBIAS (1 << 0)
#define HSMMC_HAS_UPDATED_RESET (1 << 1)
+#define HSMMC_HAS_HSPE_SUPPORT (1 << 2)
unsigned features;
int switch_pin; /* gpio (card detect) */
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index c3e96a2..0e14834 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -63,6 +63,7 @@
#define VS18 (1 << 26)
#define VS30 (1 << 25)
+#define HSS (1 << 21)
#define SDVS18 (0x5 << 9)
#define SDVS30 (0x6 << 9)
#define SDVS33 (0x7 << 9)
@@ -90,6 +91,7 @@
#define MSBS (1 << 5)
#define BCE (1 << 1)
#define FOUR_BIT (1 << 1)
+#define HSPE (1 << 2)
#define DDR (1 << 19)
#define DW8 (1 << 5)
#define CC 0x1
@@ -490,6 +492,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
struct mmc_ios *ios = &host->mmc->ios;
unsigned long regval;
unsigned long timeout;
+ unsigned long clkdiv;
dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
@@ -497,7 +500,8 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
regval = OMAP_HSMMC_READ(host->base, SYSCTL);
regval = regval & ~(CLKD_MASK | DTO_MASK);
- regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
+ clkdiv = calc_divisor(host, ios);
+ regval = regval | (clkdiv << 6) | (DTO << 16);
OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
OMAP_HSMMC_WRITE(host->base, SYSCTL,
OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
@@ -508,6 +512,27 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
&& time_before(jiffies, timeout))
cpu_relax();
+ /*
+ * Enable High-Speed Support
+ * Pre-Requisites
+ * - Controller should support High-Speed-Enable Bit
+ * - Controller should not be using DDR Mode
+ * - Controller should advertise that it supports High Speed
+ * in capabilities register
+ * - MMC/SD clock coming out of controller > 25MHz
+ */
+ if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
+ (ios->timing != MMC_TIMING_UHS_DDR50) &&
+ ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
+ regval = OMAP_HSMMC_READ(host->base, HCTL);
+ if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
+ regval |= HSPE;
+ else
+ regval &= ~HSPE;
+
+ OMAP_HSMMC_WRITE(host->base, HCTL, regval);
+ }
+
omap_hsmmc_start_clock(host);
}
@@ -1701,6 +1726,9 @@ static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
if (of_find_property(np, "ti,needs-special-reset", NULL))
pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+ if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
+ pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
+
return pdata;
}
#else
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* RE: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
2012-09-04 13:09 [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards Hebbar, Gururaja
@ 2012-09-12 7:48 ` Hebbar, Gururaja
2012-09-12 8:49 ` S, Venkatraman
2012-09-12 9:21 ` T Krishnamoorthy, Balaji
2 siblings, 0 replies; 9+ messages in thread
From: Hebbar, Gururaja @ 2012-09-12 7:48 UTC (permalink / raw)
To: linux-omap, linux-mmc, S, Venkatraman
Cc: rob.herring, linux-kernel, grant.likely, cjb, Nori, Sekhar,
Rajashekhara, Sudhakar
On Tue, Sep 04, 2012 at 18:39:11, Hebbar, Gururaja wrote:
> HSMMC IP on AM33xx need a special setting to handle High-speed cards.
> Other platforms like TI81xx, OMAP4 may need this as-well. This depends
> on the HSMMC IP timing closure done for the high speed cards.
>
> From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
>
> The MMC/SD/SDIO output signals can be driven on either falling edge or
> rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
> to reach better timing performance, and thus to increase data transfer
> frequency.
>
> There are few pre-requisites for enabling the HSPE bit
> - Controller should support High-Speed-Enable Bit and
> - Controller should not be using DDR Mode and
> - Controller should advertise that it supports High Speed in
> capabilities register and
> - MMC/SD clock coming out of controller > 25MHz
Gentle Ping. Is there any update on this patch?. If not, can this be pulled in.
>
> Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
> ---
> :100644 100644 be76a23... ed271fc... M Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> :100644 100644 eb3e4d5... 00c658b... M arch/arm/plat-omap/include/plat/mmc.h
> :100644 100644 c3e96a2... 0e14834... M drivers/mmc/host/omap_hsmmc.c
> .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 1 +
> arch/arm/plat-omap/include/plat/mmc.h | 1 +
> drivers/mmc/host/omap_hsmmc.c | 30 +++++++++++++++++++-
> 3 files changed, 31 insertions(+), 1 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> index be76a23..ed271fc 100644
> --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> @@ -19,6 +19,7 @@ ti,dual-volt: boolean, supports dual voltage cards
> "supply-name" examples are "vmmc", "vmmc_aux" etc
> ti,non-removable: non-removable slot (like eMMC)
> ti,needs-special-reset: Requires a special softreset sequence
> +ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
>
> Example:
> mmc1: mmc@0x4809c000 {
> diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
> index eb3e4d5..00c658b 100644
> --- a/arch/arm/plat-omap/include/plat/mmc.h
> +++ b/arch/arm/plat-omap/include/plat/mmc.h
> @@ -127,6 +127,7 @@ struct omap_mmc_platform_data {
> /* we can put the features above into this variable */
> #define HSMMC_HAS_PBIAS (1 << 0)
> #define HSMMC_HAS_UPDATED_RESET (1 << 1)
> +#define HSMMC_HAS_HSPE_SUPPORT (1 << 2)
> unsigned features;
>
> int switch_pin; /* gpio (card detect) */
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index c3e96a2..0e14834 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -63,6 +63,7 @@
>
> #define VS18 (1 << 26)
> #define VS30 (1 << 25)
> +#define HSS (1 << 21)
> #define SDVS18 (0x5 << 9)
> #define SDVS30 (0x6 << 9)
> #define SDVS33 (0x7 << 9)
> @@ -90,6 +91,7 @@
> #define MSBS (1 << 5)
> #define BCE (1 << 1)
> #define FOUR_BIT (1 << 1)
> +#define HSPE (1 << 2)
> #define DDR (1 << 19)
> #define DW8 (1 << 5)
> #define CC 0x1
> @@ -490,6 +492,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
> struct mmc_ios *ios = &host->mmc->ios;
> unsigned long regval;
> unsigned long timeout;
> + unsigned long clkdiv;
>
> dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
>
> @@ -497,7 +500,8 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
>
> regval = OMAP_HSMMC_READ(host->base, SYSCTL);
> regval = regval & ~(CLKD_MASK | DTO_MASK);
> - regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
> + clkdiv = calc_divisor(host, ios);
> + regval = regval | (clkdiv << 6) | (DTO << 16);
> OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
> OMAP_HSMMC_WRITE(host->base, SYSCTL,
> OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
> @@ -508,6 +512,27 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
> && time_before(jiffies, timeout))
> cpu_relax();
>
> + /*
> + * Enable High-Speed Support
> + * Pre-Requisites
> + * - Controller should support High-Speed-Enable Bit
> + * - Controller should not be using DDR Mode
> + * - Controller should advertise that it supports High Speed
> + * in capabilities register
> + * - MMC/SD clock coming out of controller > 25MHz
> + */
> + if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
> + (ios->timing != MMC_TIMING_UHS_DDR50) &&
> + ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
> + regval = OMAP_HSMMC_READ(host->base, HCTL);
> + if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
> + regval |= HSPE;
> + else
> + regval &= ~HSPE;
> +
> + OMAP_HSMMC_WRITE(host->base, HCTL, regval);
> + }
> +
> omap_hsmmc_start_clock(host);
> }
>
> @@ -1701,6 +1726,9 @@ static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
> if (of_find_property(np, "ti,needs-special-reset", NULL))
> pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
>
> + if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
> + pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
> +
> return pdata;
> }
> #else
> --
> 1.7.1
>
>
Regards,
Gururaja
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
2012-09-04 13:09 [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards Hebbar, Gururaja
2012-09-12 7:48 ` Hebbar, Gururaja
@ 2012-09-12 8:49 ` S, Venkatraman
2012-09-12 12:02 ` Hebbar, Gururaja
2012-09-26 11:37 ` Hebbar, Gururaja
2012-09-12 9:21 ` T Krishnamoorthy, Balaji
2 siblings, 2 replies; 9+ messages in thread
From: S, Venkatraman @ 2012-09-12 8:49 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: linux-omap, linux-mmc, rob.herring, linux-kernel, grant.likely,
cjb, nsekhar, sudhakar.raj
On Tue, Sep 4, 2012 at 6:39 PM, Hebbar, Gururaja <gururaja.hebbar@ti.com> wrote:
> HSMMC IP on AM33xx need a special setting to handle High-speed cards.
> Other platforms like TI81xx, OMAP4 may need this as-well. This depends
> on the HSMMC IP timing closure done for the high speed cards.
>
> From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
>
> The MMC/SD/SDIO output signals can be driven on either falling edge or
> rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
> to reach better timing performance, and thus to increase data transfer
> frequency.
>
> There are few pre-requisites for enabling the HSPE bit
> - Controller should support High-Speed-Enable Bit and
> - Controller should not be using DDR Mode and
> - Controller should advertise that it supports High Speed in
> capabilities register and
> - MMC/SD clock coming out of controller > 25MHz
>
The patch is well written. But then, I don't see a need for a DT
binding for this feature.
By definition, HS implies 25MHz or above, so that check seems to be
redundant as well.
Meanwhile, I'll check with HSPE enabled on OMAP.
Regards,
Venkat.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
2012-09-04 13:09 [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards Hebbar, Gururaja
2012-09-12 7:48 ` Hebbar, Gururaja
2012-09-12 8:49 ` S, Venkatraman
@ 2012-09-12 9:21 ` T Krishnamoorthy, Balaji
2012-09-12 11:41 ` Hebbar, Gururaja
2 siblings, 1 reply; 9+ messages in thread
From: T Krishnamoorthy, Balaji @ 2012-09-12 9:21 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: linux-omap, linux-mmc, svenkatr, rob.herring, linux-kernel,
grant.likely, cjb, nsekhar, sudhakar.raj
On Tue, Sep 4, 2012 at 6:39 PM, Hebbar, Gururaja <gururaja.hebbar@ti.com> wrote:
> HSMMC IP on AM33xx need a special setting to handle High-speed cards.
> Other platforms like TI81xx, OMAP4 may need this as-well. This depends
> on the HSMMC IP timing closure done for the high speed cards.
>
> From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
>
> The MMC/SD/SDIO output signals can be driven on either falling edge or
> rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
> to reach better timing performance, and thus to increase data transfer
> frequency.
Is this specific to some boards or all board with TI81xx ?
What is the side-effect if not done ?
>
> There are few pre-requisites for enabling the HSPE bit
> - Controller should support High-Speed-Enable Bit and
> - Controller should not be using DDR Mode and
> - Controller should advertise that it supports High Speed in
> capabilities register and
> - MMC/SD clock coming out of controller > 25MHz
>
> Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
> ---
> :100644 100644 be76a23... ed271fc... M Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> :100644 100644 eb3e4d5... 00c658b... M arch/arm/plat-omap/include/plat/mmc.h
> :100644 100644 c3e96a2... 0e14834... M drivers/mmc/host/omap_hsmmc.c
> .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 1 +
> arch/arm/plat-omap/include/plat/mmc.h | 1 +
> drivers/mmc/host/omap_hsmmc.c | 30 +++++++++++++++++++-
> 3 files changed, 31 insertions(+), 1 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> index be76a23..ed271fc 100644
> --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> @@ -19,6 +19,7 @@ ti,dual-volt: boolean, supports dual voltage cards
> "supply-name" examples are "vmmc", "vmmc_aux" etc
> ti,non-removable: non-removable slot (like eMMC)
> ti,needs-special-reset: Requires a special softreset sequence
> +ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
>
> Example:
> mmc1: mmc@0x4809c000 {
> diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
> index eb3e4d5..00c658b 100644
> --- a/arch/arm/plat-omap/include/plat/mmc.h
> +++ b/arch/arm/plat-omap/include/plat/mmc.h
> @@ -127,6 +127,7 @@ struct omap_mmc_platform_data {
> /* we can put the features above into this variable */
> #define HSMMC_HAS_PBIAS (1 << 0)
> #define HSMMC_HAS_UPDATED_RESET (1 << 1)
> +#define HSMMC_HAS_HSPE_SUPPORT (1 << 2)
> unsigned features;
>
> int switch_pin; /* gpio (card detect) */
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index c3e96a2..0e14834 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -63,6 +63,7 @@
>
> #define VS18 (1 << 26)
> #define VS30 (1 << 25)
> +#define HSS (1 << 21)
> #define SDVS18 (0x5 << 9)
> #define SDVS30 (0x6 << 9)
> #define SDVS33 (0x7 << 9)
> @@ -90,6 +91,7 @@
> #define MSBS (1 << 5)
> #define BCE (1 << 1)
> #define FOUR_BIT (1 << 1)
> +#define HSPE (1 << 2)
> #define DDR (1 << 19)
> #define DW8 (1 << 5)
> #define CC 0x1
> @@ -490,6 +492,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
> struct mmc_ios *ios = &host->mmc->ios;
> unsigned long regval;
> unsigned long timeout;
> + unsigned long clkdiv;
>
> dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
>
> @@ -497,7 +500,8 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
>
> regval = OMAP_HSMMC_READ(host->base, SYSCTL);
> regval = regval & ~(CLKD_MASK | DTO_MASK);
> - regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
> + clkdiv = calc_divisor(host, ios);
> + regval = regval | (clkdiv << 6) | (DTO << 16);
> OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
> OMAP_HSMMC_WRITE(host->base, SYSCTL,
> OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
> @@ -508,6 +512,27 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
> && time_before(jiffies, timeout))
> cpu_relax();
>
> + /*
> + * Enable High-Speed Support
> + * Pre-Requisites
> + * - Controller should support High-Speed-Enable Bit
> + * - Controller should not be using DDR Mode
> + * - Controller should advertise that it supports High Speed
> + * in capabilities register
> + * - MMC/SD clock coming out of controller > 25MHz
> + */
> + if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
> + (ios->timing != MMC_TIMING_UHS_DDR50) &&
> + ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
> + regval = OMAP_HSMMC_READ(host->base, HCTL);
> + if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
I think clkdiv is not needed
clk_get_rate(host->fclk)/clkdiv is same as ios->clock
> + regval |= HSPE;
> + else
> + regval &= ~HSPE;
> +
> + OMAP_HSMMC_WRITE(host->base, HCTL, regval);
> + }
> +
> omap_hsmmc_start_clock(host);
> }
>
> @@ -1701,6 +1726,9 @@ static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
> if (of_find_property(np, "ti,needs-special-reset", NULL))
> pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
>
> + if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
> + pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
> +
> return pdata;
> }
> #else
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
2012-09-12 9:21 ` T Krishnamoorthy, Balaji
@ 2012-09-12 11:41 ` Hebbar, Gururaja
0 siblings, 0 replies; 9+ messages in thread
From: Hebbar, Gururaja @ 2012-09-12 11:41 UTC (permalink / raw)
To: Krishnamoorthy, Balaji T
Cc: linux-omap, linux-mmc, S, Venkatraman, rob.herring, linux-kernel,
grant.likely, cjb, Nori, Sekhar, Rajashekhara, Sudhakar
On Wed, Sep 12, 2012 at 14:51:34, Krishnamoorthy, Balaji T wrote:
> On Tue, Sep 4, 2012 at 6:39 PM, Hebbar, Gururaja <gururaja.hebbar@ti.com> wrote:
> > HSMMC IP on AM33xx need a special setting to handle High-speed cards.
> > Other platforms like TI81xx, OMAP4 may need this as-well. This depends
> > on the HSMMC IP timing closure done for the high speed cards.
> >
> > From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
> >
> > The MMC/SD/SDIO output signals can be driven on either falling edge or
> > rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
> > to reach better timing performance, and thus to increase data transfer
> > frequency.
>
> Is this specific to some boards or all board with TI81xx ?
> What is the side-effect if not done ?
Platforms like (AM335x) needed this bit to be set in order to sustain high
speed transfers. This was concluded after HSMMC IP timing closure was
completed for High speed Cards.
This was confirmed on high speed cards with very low setup/hold delay (in the
order of nsec) was tested. For AM335x, this bit was to be set to meet setup
requirement and hold requirement for MMC/SD HS cards.
>
> >
> > There are few pre-requisites for enabling the HSPE bit
> > - Controller should support High-Speed-Enable Bit and
> > - Controller should not be using DDR Mode and
> > - Controller should advertise that it supports High Speed in
> > capabilities register and
> > - MMC/SD clock coming out of controller > 25MHz
> >
> > Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
> > ---
> > :100644 100644 be76a23... ed271fc... M Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> > :100644 100644 eb3e4d5... 00c658b... M arch/arm/plat-omap/include/plat/mmc.h
> > :100644 100644 c3e96a2... 0e14834... M drivers/mmc/host/omap_hsmmc.c
..snip..
..snip..
..snip..
> >
> > + /*
> > + * Enable High-Speed Support
> > + * Pre-Requisites
> > + * - Controller should support High-Speed-Enable Bit
> > + * - Controller should not be using DDR Mode
> > + * - Controller should advertise that it supports High Speed
> > + * in capabilities register
> > + * - MMC/SD clock coming out of controller > 25MHz
> > + */
> > + if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
> > + (ios->timing != MMC_TIMING_UHS_DDR50) &&
> > + ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
> > + regval = OMAP_HSMMC_READ(host->base, HCTL);
> > + if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
>
> I think clkdiv is not needed
> clk_get_rate(host->fclk)/clkdiv is same as ios->clock
There are chances that the platform is not supporting Clock output from HSMMC
IP greater than 25 MHz even if the card is High Speed. So it would be better
to check host->fclk than ios->clock.
Kindly correct me if I am wrong.
>
> > + regval |= HSPE;
> > + else
> > + regval &= ~HSPE;
> > +
> > + OMAP_HSMMC_WRITE(host->base, HCTL, regval);
> > + }
> > +
> > omap_hsmmc_start_clock(host);
> > }
> >
> > @@ -1701,6 +1726,9 @@ static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
> > if (of_find_property(np, "ti,needs-special-reset", NULL))
> > pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
> >
> > + if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
> > + pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
> > +
> > return pdata;
> > }
> > #else
> > --
> > 1.7.1
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
>
Regards,
Gururaja
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
2012-09-12 8:49 ` S, Venkatraman
@ 2012-09-12 12:02 ` Hebbar, Gururaja
2012-09-26 11:37 ` Hebbar, Gururaja
1 sibling, 0 replies; 9+ messages in thread
From: Hebbar, Gururaja @ 2012-09-12 12:02 UTC (permalink / raw)
To: S, Venkatraman
Cc: linux-omap, linux-mmc, rob.herring, linux-kernel, grant.likely,
cjb, Nori, Sekhar, Rajashekhara, Sudhakar
On Wed, Sep 12, 2012 at 14:19:51, S, Venkatraman wrote:
> On Tue, Sep 4, 2012 at 6:39 PM, Hebbar, Gururaja <gururaja.hebbar@ti.com> wrote:
> > HSMMC IP on AM33xx need a special setting to handle High-speed cards.
> > Other platforms like TI81xx, OMAP4 may need this as-well. This depends
> > on the HSMMC IP timing closure done for the high speed cards.
> >
> > From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
> >
> > The MMC/SD/SDIO output signals can be driven on either falling edge or
> > rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
> > to reach better timing performance, and thus to increase data transfer
> > frequency.
> >
> > There are few pre-requisites for enabling the HSPE bit
> > - Controller should support High-Speed-Enable Bit and
> > - Controller should not be using DDR Mode and
> > - Controller should advertise that it supports High Speed in
> > capabilities register and
> > - MMC/SD clock coming out of controller > 25MHz
> >
>
> The patch is well written. But then, I don't see a need for a DT
> binding for this feature.
My reasons for DT Binding
1. Not all platforms using this driver has this bit (OMAP2)
2. Not all platforms using this driver needs this bit to be enabled (OMAP4)
3. Platforms which require this bit this to be set needs a method to inform
driver.
In order to not disturb old/unsupported platforms, I chose this DT method.
> By definition, HS implies 25MHz or above, so that check seems to be
> redundant as well.
There are chances that the platform Max Clock output from HSMMC IP is < than
25 MHz even if the card is High Speed. In such cases it would be better to
Confirm that the Clock output is actually > 25 MHz
Kindly correct me if I am wrong.
> Meanwhile, I'll check with HSPE enabled on OMAP.
>
> Regards,
> Venkat.
>
Regards,
Gururaja
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
2012-09-12 8:49 ` S, Venkatraman
2012-09-12 12:02 ` Hebbar, Gururaja
@ 2012-09-26 11:37 ` Hebbar, Gururaja
2012-09-27 11:01 ` Koen Kooi
1 sibling, 1 reply; 9+ messages in thread
From: Hebbar, Gururaja @ 2012-09-26 11:37 UTC (permalink / raw)
To: S, Venkatraman
Cc: linux-omap, linux-mmc, rob.herring, linux-kernel, grant.likely,
cjb, Nori, Sekhar, Rajashekhara, Sudhakar
On Wed, Sep 12, 2012 at 17:32:38, Hebbar, Gururaja wrote:
> On Wed, Sep 12, 2012 at 14:19:51, S, Venkatraman wrote:
> > On Tue, Sep 4, 2012 at 6:39 PM, Hebbar, Gururaja <gururaja.hebbar@ti.com> wrote:
> > > HSMMC IP on AM33xx need a special setting to handle High-speed cards.
> > > Other platforms like TI81xx, OMAP4 may need this as-well. This depends
> > > on the HSMMC IP timing closure done for the high speed cards.
> > >
> > > From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
> > >
> > > The MMC/SD/SDIO output signals can be driven on either falling edge or
> > > rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
> > > to reach better timing performance, and thus to increase data transfer
> > > frequency.
> > >
> > > There are few pre-requisites for enabling the HSPE bit
> > > - Controller should support High-Speed-Enable Bit and
> > > - Controller should not be using DDR Mode and
> > > - Controller should advertise that it supports High Speed in
> > > capabilities register and
> > > - MMC/SD clock coming out of controller > 25MHz
> > >
> >
> > The patch is well written. But then, I don't see a need for a DT
> > binding for this feature.
>
> My reasons for DT Binding
> 1. Not all platforms using this driver has this bit (OMAP2)
> 2. Not all platforms using this driver needs this bit to be enabled (OMAP4)
> 3. Platforms which require this bit this to be set needs a method to inform
> driver.
>
> In order to not disturb old/unsupported platforms, I chose this DT method.
>
> > By definition, HS implies 25MHz or above, so that check seems to be
> > redundant as well.
>
> There are chances that the platform Max Clock output from HSMMC IP is < than
> 25 MHz even if the card is High Speed. In such cases it would be better to
> Confirm that the Clock output is actually > 25 MHz
>
> Kindly correct me if I am wrong.
>
> > Meanwhile, I'll check with HSPE enabled on OMAP.
> >
Gentle Ping.
Matt Poter recently submitted EDMA related patches as RFC. He confirmed that
basic mmc is working on AM335x with his edma patches.
Above patch is required to get High-speed cards working on AM335x.
I haven't seen any review comments for this. Can this be pulled in for 3.7?
> > Regards,
> > Venkat.
> >
>
>
> Regards,
> Gururaja
>
Regards,
Gururaja
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
2012-09-26 11:37 ` Hebbar, Gururaja
@ 2012-09-27 11:01 ` Koen Kooi
2012-09-27 11:35 ` Hebbar, Gururaja
0 siblings, 1 reply; 9+ messages in thread
From: Koen Kooi @ 2012-09-27 11:01 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: S, Venkatraman, linux-omap, linux-mmc, rob.herring, linux-kernel,
grant.likely, cjb, Nori, Sekhar, Rajashekhara, Sudhakar
Op 26 sep. 2012, om 13:37 heeft "Hebbar, Gururaja" <gururaja.hebbar@ti.com> het volgende geschreven:
> On Wed, Sep 12, 2012 at 17:32:38, Hebbar, Gururaja wrote:
>> On Wed, Sep 12, 2012 at 14:19:51, S, Venkatraman wrote:
>>> On Tue, Sep 4, 2012 at 6:39 PM, Hebbar, Gururaja <gururaja.hebbar@ti.com> wrote:
>>>> HSMMC IP on AM33xx need a special setting to handle High-speed cards.
>>>> Other platforms like TI81xx, OMAP4 may need this as-well. This depends
>>>> on the HSMMC IP timing closure done for the high speed cards.
>>>>
>>>> From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
>>>>
>>>> The MMC/SD/SDIO output signals can be driven on either falling edge or
>>>> rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
>>>> to reach better timing performance, and thus to increase data transfer
>>>> frequency.
>>>>
>>>> There are few pre-requisites for enabling the HSPE bit
>>>> - Controller should support High-Speed-Enable Bit and
>>>> - Controller should not be using DDR Mode and
>>>> - Controller should advertise that it supports High Speed in
>>>> capabilities register and
>>>> - MMC/SD clock coming out of controller > 25MHz
>>>>
>>>
>>> The patch is well written. But then, I don't see a need for a DT
>>> binding for this feature.
>>
>> My reasons for DT Binding
>> 1. Not all platforms using this driver has this bit (OMAP2)
>> 2. Not all platforms using this driver needs this bit to be enabled (OMAP4)
>> 3. Platforms which require this bit this to be set needs a method to inform
>> driver.
>>
>> In order to not disturb old/unsupported platforms, I chose this DT method.
>>
>>> By definition, HS implies 25MHz or above, so that check seems to be
>>> redundant as well.
>>
>> There are chances that the platform Max Clock output from HSMMC IP is < than
>> 25 MHz even if the card is High Speed. In such cases it would be better to
>> Confirm that the Clock output is actually > 25 MHz
>>
>> Kindly correct me if I am wrong.
>>
>>> Meanwhile, I'll check with HSPE enabled on OMAP.
>>>
>
> Gentle Ping.
>
> Matt Poter recently submitted EDMA related patches as RFC. He confirmed that
> basic mmc is working on AM335x with his edma patches.
>
> Above patch is required to get High-speed cards working on AM335x.
>
> I haven't seen any review comments for this. Can this be pulled in for 3.7?
I had trouble applying this to 3.6-rc7, is that a known problem and should I try linux-next?
regards,
Koen
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
2012-09-27 11:01 ` Koen Kooi
@ 2012-09-27 11:35 ` Hebbar, Gururaja
0 siblings, 0 replies; 9+ messages in thread
From: Hebbar, Gururaja @ 2012-09-27 11:35 UTC (permalink / raw)
To: Koen Kooi
Cc: S, Venkatraman, linux-omap, linux-mmc, rob.herring, linux-kernel,
grant.likely, cjb, Nori, Sekhar, Rajashekhara, Sudhakar
On Thu, Sep 27, 2012 at 16:31:14, Koen Kooi wrote:
>
> Op 26 sep. 2012, om 13:37 heeft "Hebbar, Gururaja" <gururaja.hebbar@ti.com> het volgende geschreven:
>
> > On Wed, Sep 12, 2012 at 17:32:38, Hebbar, Gururaja wrote:
> >> On Wed, Sep 12, 2012 at 14:19:51, S, Venkatraman wrote:
> >>> On Tue, Sep 4, 2012 at 6:39 PM, Hebbar, Gururaja <gururaja.hebbar@ti.com> wrote:
> >>>> HSMMC IP on AM33xx need a special setting to handle High-speed cards.
> >>>> Other platforms like TI81xx, OMAP4 may need this as-well. This depends
> >>>> on the HSMMC IP timing closure done for the high speed cards.
> >>>>
> >>>> From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation)
> >>>>
> >>>> The MMC/SD/SDIO output signals can be driven on either falling edge or
> >>>> rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows
> >>>> to reach better timing performance, and thus to increase data transfer
> >>>> frequency.
> >>>>
> >>>> There are few pre-requisites for enabling the HSPE bit
> >>>> - Controller should support High-Speed-Enable Bit and
> >>>> - Controller should not be using DDR Mode and
> >>>> - Controller should advertise that it supports High Speed in
> >>>> capabilities register and
> >>>> - MMC/SD clock coming out of controller > 25MHz
> >>>>
> >>>
> >>> The patch is well written. But then, I don't see a need for a DT
> >>> binding for this feature.
> >>
> >> My reasons for DT Binding
> >> 1. Not all platforms using this driver has this bit (OMAP2)
> >> 2. Not all platforms using this driver needs this bit to be enabled (OMAP4)
> >> 3. Platforms which require this bit this to be set needs a method to inform
> >> driver.
> >>
> >> In order to not disturb old/unsupported platforms, I chose this DT method.
> >>
> >>> By definition, HS implies 25MHz or above, so that check seems to be
> >>> redundant as well.
> >>
> >> There are chances that the platform Max Clock output from HSMMC IP is < than
> >> 25 MHz even if the card is High Speed. In such cases it would be better to
> >> Confirm that the Clock output is actually > 25 MHz
> >>
> >> Kindly correct me if I am wrong.
> >>
> >>> Meanwhile, I'll check with HSPE enabled on OMAP.
> >>>
> >
> > Gentle Ping.
> >
> > Matt Poter recently submitted EDMA related patches as RFC. He confirmed that
> > basic mmc is working on AM335x with his edma patches.
> >
> > Above patch is required to get High-speed cards working on AM335x.
> >
> > I haven't seen any review comments for this. Can this be pulled in for 3.7?
>
> I had trouble applying this to 3.6-rc7, is that a known problem and should I try linux-next?
I just applied it applied it on Linux-next/master (locally merged with linux-omap-dt branch).
It applied without any issues.
>
> regards,
>
> Koen
Regards,
Gururaja
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2012-09-27 11:35 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-09-04 13:09 [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards Hebbar, Gururaja
2012-09-12 7:48 ` Hebbar, Gururaja
2012-09-12 8:49 ` S, Venkatraman
2012-09-12 12:02 ` Hebbar, Gururaja
2012-09-26 11:37 ` Hebbar, Gururaja
2012-09-27 11:01 ` Koen Kooi
2012-09-27 11:35 ` Hebbar, Gururaja
2012-09-12 9:21 ` T Krishnamoorthy, Balaji
2012-09-12 11:41 ` Hebbar, Gururaja
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