From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C29C5C433F5 for ; Wed, 22 Sep 2021 12:55:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ACDBE611CA for ; Wed, 22 Sep 2021 12:55:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236186AbhIVM5D (ORCPT ); Wed, 22 Sep 2021 08:57:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236093AbhIVM46 (ORCPT ); Wed, 22 Sep 2021 08:56:58 -0400 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77D99C061757 for ; Wed, 22 Sep 2021 05:55:28 -0700 (PDT) Received: by mail-qk1-x72e.google.com with SMTP id c7so9382724qka.2 for ; Wed, 22 Sep 2021 05:55:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ndufresne-ca.20210112.gappssmtp.com; s=20210112; h=message-id:subject:from:to:cc:date:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=Xl1LKKaIiXIR37FrSULq1gxTEDagbmid3RKiTF/dDZo=; b=ucMCz1XsSXa4jVLaWDpBuCtPqr2LWu/82E7qUfIQGQLQeCEQIcLYCkmcvbIo8Vd12J dXjOvKLpQWgJbZUowNSVw+g/l+EYxoiFv4BxA2HLgvKNh0cb2d/pZR7XVFuP0GvPKQWb 2bu4ISk5Nmcmm3pEAFHiHWXuBvrDrXoHf3Nt5t3uuMwYvTJ72kiYqe2YVOvf8mERrWLh OGBnpgZ8P/K0+XcGVw0T66qA7G24cJW1MevbPf0KzDvcuo/ly5Rz7GHulb8+sz8Tzw9N 9hAeuF1/JBR6uokvd617IVMSUT8tGGjMAT8nRk8bEU44pAjHN70WhBc6b0gwPKAg6fVm WJcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:subject:from:to:cc:date:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=Xl1LKKaIiXIR37FrSULq1gxTEDagbmid3RKiTF/dDZo=; b=NR4Xns2KpVpvJvi2UA6FPLsREJO9lJPvZXdDmsp4mDPENNlSc8fd3tM42r7otEdrJg JIrbdtrn2xPy8e4IHKDCzhHY76/OI1sNwuamNnOX7/Mq8SGBkpAfPqezHPZAbwyEYWwG O4rLiwXkcK1LWkdaQ2BmHxiQQkb8ZfIrBAqOyGSQAKicEw4NpyJ0R/emsfii6zsRlQ4a iDAEnt1fh5SWSt5z9NHkvAyMk5F/XRfh3/tdK8iGtFZmurXoBgecXXwQOvddsZsnKpAF c4xXWx41zzWgCzhppaoXMYUI9fqj3TG+u2/1HmzmRfgc0pl+6MS4NvF49RW/RvgVrLKi SffQ== X-Gm-Message-State: AOAM531CZ/P9qJytZ08juUJZ7XWHJ6QdQgnTeIulZldA+otX9jxd3vGq fKd7kDPyaZrLF6xoLhO0/gc28w== X-Google-Smtp-Source: ABdhPJwgt0W5YMkkw7w3IhC4ynEqGmVa7i1e+ILuzKPG99+rs1dt2aElAFlEbCssUzyHtm/Ulr/qbw== X-Received: by 2002:a05:620a:c53:: with SMTP id u19mr34147027qki.144.1632315327587; Wed, 22 Sep 2021 05:55:27 -0700 (PDT) Received: from nicolas-tpx395.localdomain (173-246-12-168.qc.cable.ebox.net. [173.246.12.168]) by smtp.gmail.com with ESMTPSA id h5sm1725958qke.1.2021.09.22.05.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Sep 2021 05:55:27 -0700 (PDT) Message-ID: <1a454107661fced1adfd8a76a20a819d75b882d4.camel@ndufresne.ca> Subject: Re: [PATCH v9 11/13] ARM64: dts: freescale: imx8q: add imx vpu codec entries From: Nicolas Dufresne To: Ming Qian , mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Date: Wed, 22 Sep 2021 08:55:25 -0400 In-Reply-To: <620081ca2f6441de6307792dbb7797da148cf04c.1631521295.git.ming.qian@nxp.com> References: <620081ca2f6441de6307792dbb7797da148cf04c.1631521295.git.ming.qian@nxp.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Ming, Le lundi 13 septembre 2021 à 17:11 +0800, Ming Qian a écrit : > Add the Video Processing Unit node for IMX8Q SoC. Just to let you know that this patch no longer apply on 5.15-rc2. Please let us know which was your base. > > Signed-off-by: Ming Qian > Signed-off-by: Shijie Qin > Signed-off-by: Zhou Peng > --- > .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +++++ > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 24 +++++++ > 3 files changed, 113 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi > new file mode 100644 > index 000000000000..f2dde6d14ca3 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi > @@ -0,0 +1,72 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2021 NXP > + * Dong Aisheng > + */ > + > +vpu: vpu@2c000000 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; > + reg = <0 0x2c000000 0 0x1000000>; > + power-domains = <&pd IMX_SC_R_VPU>; > + status = "disabled"; > + > + mu_m0: mailbox@2d000000 { > + compatible = "fsl,imx6sx-mu"; > + reg = <0x2d000000 0x20000>; > + interrupts = ; > + #mbox-cells = <2>; > + power-domains = <&pd IMX_SC_R_VPU_MU_0>; > + status = "okay"; > + }; > + > + mu1_m0: mailbox@2d020000 { > + compatible = "fsl,imx6sx-mu"; > + reg = <0x2d020000 0x20000>; > + interrupts = ; > + #mbox-cells = <2>; > + power-domains = <&pd IMX_SC_R_VPU_MU_1>; > + status = "okay"; > + }; > + > + mu2_m0: mailbox@2d040000 { > + compatible = "fsl,imx6sx-mu"; > + reg = <0x2d040000 0x20000>; > + interrupts = ; > + #mbox-cells = <2>; > + power-domains = <&pd IMX_SC_R_VPU_MU_2>; > + status = "disabled"; > + }; > + > + vpu_core0: vpu_core@2d080000 { > + reg = <0x2d080000 0x10000>; > + compatible = "nxp,imx8q-vpu-decoder"; > + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; > + mbox-names = "tx0", "tx1", "rx"; > + mboxes = <&mu_m0 0 0>, > + <&mu_m0 0 1>, > + <&mu_m0 1 0>; > + status = "disabled"; > + }; > + vpu_core1: vpu_core@2d090000 { > + reg = <0x2d090000 0x10000>; > + compatible = "nxp,imx8q-vpu-encoder"; > + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; > + mbox-names = "tx0", "tx1", "rx"; > + mboxes = <&mu1_m0 0 0>, > + <&mu1_m0 0 1>, > + <&mu1_m0 1 0>; > + status = "disabled"; > + }; > + vpu_core2: vpu_core@2d0a0000 { > + reg = <0x2d0a0000 0x10000>; > + compatible = "nxp,imx8q-vpu-encoder"; > + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; > + mbox-names = "tx0", "tx1", "rx"; > + mboxes = <&mu2_m0 0 0>, > + <&mu2_m0 0 1>, > + <&mu2_m0 1 0>; > + status = "disabled"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts > index 863232a47004..05495b60beb8 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts > @@ -196,6 +196,23 @@ &usdhc2 { > status = "okay"; > }; > > +&vpu { > + compatible = "nxp,imx8qxp-vpu"; > + status = "okay"; > +}; > + > +&vpu_core0 { > + reg = <0x2d040000 0x10000>; > + memory-region = <&decoder_boot>, <&decoder_rpc>; > + status = "okay"; > +}; > + > +&vpu_core1 { > + reg = <0x2d050000 0x10000>; > + memory-region = <&encoder_boot>, <&encoder_rpc>; > + status = "okay"; > +}; > + > &iomuxc { > pinctrl_fec1: fec1grp { > fsl,pins = < > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > index 1e6b4995091e..6b421cfa5534 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > @@ -46,6 +46,9 @@ aliases { > serial1 = &lpuart1; > serial2 = &lpuart2; > serial3 = &lpuart3; > + vpu_core0 = &vpu_core0; > + vpu_core1 = &vpu_core1; > + vpu_core2 = &vpu_core2; > }; > > cpus { > @@ -134,10 +137,30 @@ reserved-memory { > #size-cells = <2>; > ranges; > > + decoder_boot: decoder-boot@84000000 { > + reg = <0 0x84000000 0 0x2000000>; > + no-map; > + }; > + > + encoder_boot: encoder-boot@86000000 { > + reg = <0 0x86000000 0 0x200000>; > + no-map; > + }; > + > + decoder_rpc: decoder-rpc@0x92000000 { > + reg = <0 0x92000000 0 0x100000>; > + no-map; > + }; > + > dsp_reserved: dsp@92400000 { > reg = <0 0x92400000 0 0x2000000>; > no-map; > }; > + > + encoder_rpc: encoder-rpc@0x94400000 { > + reg = <0 0x94400000 0 0x700000>; > + no-map; > + }; > }; > > pmu { > @@ -258,6 +281,7 @@ map0 { > }; > > /* sorted in register address */ > + #include "imx8-ss-vpu.dtsi" > #include "imx8-ss-adma.dtsi" > #include "imx8-ss-conn.dtsi" > #include "imx8-ss-ddr.dtsi"