From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764654AbdAJO0D (ORCPT ); Tue, 10 Jan 2017 09:26:03 -0500 Received: from foss.arm.com ([217.140.101.70]:54940 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752445AbdAJO0B (ORCPT ); Tue, 10 Jan 2017 09:26:01 -0500 Subject: Re: [PATCH v4 7/9] arm64: cpufeature: Track user visible fields To: Catalin Marinas References: <1483982912-27215-1-git-send-email-suzuki.poulose@arm.com> <1483982912-27215-8-git-send-email-suzuki.poulose@arm.com> <20170110142427.GA23051@e104818-lin.cambridge.arm.com> Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, ryan.arnold@linaro.org, sid@reserved-bit.com, aph@redhat.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, adhemerval.zanella@linaro.org, dave.martin@arm.com From: Suzuki K Poulose Message-ID: <1a8ef423-75a9-b3e9-27d8-cf289274613a@arm.com> Date: Tue, 10 Jan 2017 14:25:57 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <20170110142427.GA23051@e104818-lin.cambridge.arm.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/01/17 14:24, Catalin Marinas wrote: > On Mon, Jan 09, 2017 at 05:28:30PM +0000, Suzuki K. Poulose wrote: >> Changes since V3: >> - Mark ID_AA64ISAR0_EL1:RDM visible > [...] >> static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { >> - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), > > As I said in an earlier reply, I'd like the RDM exposing to come > together with a patch presenting the corresponding HWCAP bit. But it's > fine by me if you add the HWCAP separately from this patch, in which > case my ack still stands. Catalin, Yes, I have a separate patch for that. Thanks Suzuki