linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v3 0/6] Improve clock support for Actions S500 SoC
@ 2021-06-10 20:05 Cristian Ciocaltea
  2021-06-10 20:05 ` [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl " Cristian Ciocaltea
                   ` (6 more replies)
  0 siblings, 7 replies; 15+ messages in thread
From: Cristian Ciocaltea @ 2021-06-10 20:05 UTC (permalink / raw)
  To: Stephen Boyd, Rob Herring, Manivannan Sadhasivam,
	Andreas Färber, Michael Turquette, Edgar Bernardi Righi
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

While working on a driver to support the Actions Semi Owl Ethernet MAC,
I found and fixed some issues on the existing implementation of the S500
SoC clock subsystem and, additionally, I added two missing clocks.

Thanks,
Cristi

Changes in v3:
- Fixed swapped flags between "ahbprediv_clk" and "ahb_clk" in patch 4/6
- Added Reviewed-by tags from Mani
- Rebased patch series on v5.13-rc5

Changes in v2 (according to Mani's review):
- Re-added entry "{ 24, 1, 25 }" to sd_factor_table, according to the
  datasheet (V1.8+), this is a valid divider
- Re-added OWL_GATE_HW to SENSOR[0-1], according to the datasheet they
  are gated, even though the vendor implementation states the opposite
- Reverted the addition of the clock div table for H clock to support the
  '1' divider (according to the datasheet), even though the vendor
  implementation marks it as reserved
- Reordered "nic_clk_mux_p" after "ahbprediv_clk_mux_p" to follow the reg
  field ordering
- Rebased patch series on v5.13-rc3

Cristian Ciocaltea (6):
  clk: actions: Fix UART clock dividers on Owl S500 SoC
  clk: actions: Fix SD clocks factor table on Owl S500 SoC
  clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC
  clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
  dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC
  clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC

 drivers/clk/actions/owl-s500.c               | 92 +++++++++++++-------
 include/dt-bindings/clock/actions,s500-cmu.h |  6 +-
 2 files changed, 65 insertions(+), 33 deletions(-)

-- 
2.32.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl S500 SoC
  2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
@ 2021-06-10 20:05 ` Cristian Ciocaltea
  2021-06-28  1:46   ` Stephen Boyd
  2021-06-10 20:05 ` [PATCH v3 2/6] clk: actions: Fix SD clocks factor table " Cristian Ciocaltea
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 15+ messages in thread
From: Cristian Ciocaltea @ 2021-06-10 20:05 UTC (permalink / raw)
  To: Stephen Boyd, Rob Herring, Manivannan Sadhasivam,
	Andreas Färber, Michael Turquette, Edgar Bernardi Righi
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

Use correct divider registers for the Actions Semi Owl S500 SoC's UART
clocks.

Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v3:
 - None

Changes in v2:
 - Added Reviewed-by from Mani

 drivers/clk/actions/owl-s500.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 61bb224f6330..75b7186185b0 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -305,7 +305,7 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
 static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
 			OWL_MUX_HW(CMU_UART0CLK, 16, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
-			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+			OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 			CLK_IGNORE_UNUSED);
 
 static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
@@ -317,31 +317,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
 static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
 			OWL_MUX_HW(CMU_UART2CLK, 16, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
-			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+			OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 			CLK_IGNORE_UNUSED);
 
 static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
 			OWL_MUX_HW(CMU_UART3CLK, 16, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
-			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+			OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 			CLK_IGNORE_UNUSED);
 
 static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
 			OWL_MUX_HW(CMU_UART4CLK, 16, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
-			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+			OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 			CLK_IGNORE_UNUSED);
 
 static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
 			OWL_MUX_HW(CMU_UART5CLK, 16, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
-			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+			OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 			CLK_IGNORE_UNUSED);
 
 static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
 			OWL_MUX_HW(CMU_UART6CLK, 16, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
-			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+			OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 			CLK_IGNORE_UNUSED);
 
 static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
-- 
2.32.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH v3 2/6] clk: actions: Fix SD clocks factor table on Owl S500 SoC
  2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
  2021-06-10 20:05 ` [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl " Cristian Ciocaltea
@ 2021-06-10 20:05 ` Cristian Ciocaltea
  2021-06-28  1:47   ` Stephen Boyd
  2021-06-10 20:05 ` [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks " Cristian Ciocaltea
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 15+ messages in thread
From: Cristian Ciocaltea @ 2021-06-10 20:05 UTC (permalink / raw)
  To: Stephen Boyd, Rob Herring, Manivannan Sadhasivam,
	Andreas Färber, Michael Turquette, Edgar Bernardi Righi
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

Drop the unsupported entries in the factor table used for the SD[0-2]
clocks definitions on the Actions Semi Owl S500 SoC.

Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v3:
 - Added Reviewed-by tag from Mani

Changes in v2:
 - Re-added entry "{ 24, 1, 25 }" to sd_factor_table, according to the
   datasheet (V1.8+), this is a valid divider

 drivers/clk/actions/owl-s500.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 75b7186185b0..42abdf964044 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -127,8 +127,7 @@ static struct clk_factor_table sd_factor_table[] = {
 	{ 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
 	{ 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
 	{ 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
-	{ 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
-	{ 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
+	{ 24, 1, 25 },
 
 	/* bit8: /128 */
 	{ 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
@@ -137,8 +136,7 @@ static struct clk_factor_table sd_factor_table[] = {
 	{ 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
 	{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
 	{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
-	{ 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
-	{ 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
+	{ 280, 1, 25 * 128 },
 	{ 0, 0, 0 },
 };
 
-- 
2.32.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC
  2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
  2021-06-10 20:05 ` [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl " Cristian Ciocaltea
  2021-06-10 20:05 ` [PATCH v3 2/6] clk: actions: Fix SD clocks factor table " Cristian Ciocaltea
@ 2021-06-10 20:05 ` Cristian Ciocaltea
  2021-06-28  1:47   ` Stephen Boyd
  2021-06-10 20:05 ` [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain " Cristian Ciocaltea
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 15+ messages in thread
From: Cristian Ciocaltea @ 2021-06-10 20:05 UTC (permalink / raw)
  To: Stephen Boyd, Rob Herring, Manivannan Sadhasivam,
	Andreas Färber, Michael Turquette, Edgar Bernardi Righi
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

The following clocks of the Actions Semi Owl S500 SoC have been defined
to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE,
VDE, BISP, SENSOR[0-1]

There are several issues involved in this approach:

* 'bisp_factor_table[]' describes the configuration of a regular 8-rates
  divider, so its usage is redundant. Additionally, judging by the BISP
  clock context, it is incomplete since it maps only 8 out of 12
  possible entries.

* The clocks mentioned above are not identical in terms of the available
  rates, therefore cannot rely on the same factor table. Specifically,
  BISP and SENSOR* are standard 12-rate dividers so their configuration
  should rely on a proper clock div table, while VCE and VDE require a
  factor table that is a actually a subset of the one needed for DE[1-2]
  clocks.

Let's fix this by implementing the following:

* Add new factor tables 'de_factor_table' and 'hde_factor_table' to
  properly handle DE[1-2], VCE and VDE clocks.

* Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1]
  clocks converted to OWL_COMP_DIV.

* Drop the now unused 'bisp_factor_table[]'.

Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since
there is no reason to always keep ON those clocks.

Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v3:
 - Added Reviewed-by tag from Mani

Changes in v2:
 - Re-added OWL_GATE_HW to SENSOR[0-1], according to the datasheet they
   are gated, even though the vendor implementation states the opposite

 drivers/clk/actions/owl-s500.c | 44 ++++++++++++++++++++++------------
 1 file changed, 29 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 42abdf964044..42d6899755e6 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -140,9 +140,16 @@ static struct clk_factor_table sd_factor_table[] = {
 	{ 0, 0, 0 },
 };
 
-static struct clk_factor_table bisp_factor_table[] = {
-	{ 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
-	{ 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
+static struct clk_factor_table de_factor_table[] = {
+	{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
+	{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
+	{ 8, 1, 12 },
+	{ 0, 0, 0 },
+};
+
+static struct clk_factor_table hde_factor_table[] = {
+	{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
+	{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
 	{ 0, 0, 0 },
 };
 
@@ -156,6 +163,13 @@ static struct clk_div_table rmii_ref_div_table[] = {
 	{ 0, 0 },
 };
 
+static struct clk_div_table std12rate_div_table[] = {
+	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
+	{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
+	{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
+	{ 0, 0 },
+};
+
 static struct clk_div_table i2s_div_table[] = {
 	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
 	{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
@@ -191,39 +205,39 @@ static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNE
 
 /* factor clocks */
 static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
-static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
-static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
+static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
+static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
 
 /* composite clocks */
 static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
 			OWL_MUX_HW(CMU_VCECLK, 4, 2),
 			OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
-			OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
+			OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
 			0);
 
 static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
 			OWL_MUX_HW(CMU_VDECLK, 4, 2),
 			OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
-			OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
+			OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
 			0);
 
-static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
+static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p,
 			OWL_MUX_HW(CMU_BISPCLK, 4, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
-			OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
+			OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
 			0);
 
-static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
+static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
 			OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
-			OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table),
-			CLK_IGNORE_UNUSED);
+			OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
+			0);
 
-static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
+static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
 			OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
-			OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table),
-			CLK_IGNORE_UNUSED);
+			OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
+			0);
 
 static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
 			OWL_MUX_HW(CMU_SD0CLK, 9, 1),
-- 
2.32.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
  2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
                   ` (2 preceding siblings ...)
  2021-06-10 20:05 ` [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks " Cristian Ciocaltea
@ 2021-06-10 20:05 ` Cristian Ciocaltea
  2021-06-11  4:11   ` Manivannan Sadhasivam
  2021-06-28  1:47   ` Stephen Boyd
  2021-06-10 20:05 ` [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions " Cristian Ciocaltea
                   ` (2 subsequent siblings)
  6 siblings, 2 replies; 15+ messages in thread
From: Cristian Ciocaltea @ 2021-06-10 20:05 UTC (permalink / raw)
  To: Stephen Boyd, Rob Herring, Manivannan Sadhasivam,
	Andreas Färber, Michael Turquette, Edgar Bernardi Righi
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

There are a few issues with the setup of the Actions Semi Owl S500 SoC's
clock chain involving AHPPREDIV, H and AHB clocks:

* AHBPREDIV clock is defined as a muxer only, although it also acts as
  a divider.
* H clock is using a wrong divider register offset
* AHB is defined as a multi-rate factor clock, but it is actually just
  a fixed pass clock.

Let's provide the following fixes:

* Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition.
* Use the correct register shift value in the OWL_DIVIDER definition
  for H clock
* Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an
  ungated OWL_COMP_FIXED_FACTOR definition.

Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
Changes in v3:
 - Fixed the swapped flags between "ahbprediv_clk" and "ahb_clk" as noticed
   by Mani

Changes in v2:
 - Reverted the addition of the clock div table for H clock to support the
   '1' divider (according to the datasheet), even though the vendor
   implementation marks it as reserved
 
 drivers/clk/actions/owl-s500.c | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 42d6899755e6..cbeb51c804eb 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -153,11 +153,6 @@ static struct clk_factor_table hde_factor_table[] = {
 	{ 0, 0, 0 },
 };
 
-static struct clk_factor_table ahb_factor_table[] = {
-	{ 1, 1, 2 }, { 2, 1, 3 },
-	{ 0, 0, 0 },
-};
-
 static struct clk_div_table rmii_ref_div_table[] = {
 	{ 0, 4 }, { 1, 10 },
 	{ 0, 0 },
@@ -186,7 +181,6 @@ static struct clk_div_table nand_div_table[] = {
 
 /* mux clock */
 static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
-static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
 
 /* gate clocks */
 static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
@@ -199,16 +193,25 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
 static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
 
 /* divider clocks */
-static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
 static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
 static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
 
 /* factor clocks */
-static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
 static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
 static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
 
 /* composite clocks */
+static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
+			OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
+			{ 0 },
+			OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
+			CLK_SET_RATE_PARENT);
+
+static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
+			{ 0 },
+			1, 1, 0);
+
 static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
 			OWL_MUX_HW(CMU_VCECLK, 4, 2),
 			OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
-- 
2.32.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC
  2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
                   ` (3 preceding siblings ...)
  2021-06-10 20:05 ` [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain " Cristian Ciocaltea
@ 2021-06-10 20:05 ` Cristian Ciocaltea
  2021-06-28  1:47   ` Stephen Boyd
  2021-06-10 20:05 ` [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support " Cristian Ciocaltea
  2021-06-16 16:06 ` [PATCH v3 0/6] Improve " Cristian Ciocaltea
  6 siblings, 1 reply; 15+ messages in thread
From: Cristian Ciocaltea @ 2021-06-10 20:05 UTC (permalink / raw)
  To: Stephen Boyd, Rob Herring, Manivannan Sadhasivam,
	Andreas Färber, Michael Turquette, Edgar Bernardi Righi
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel,
	devicetree, Rob Herring

Add the missing NIC and ETHERNET clock bindings constants for Actions
Semi Owl S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v3:
 - Added Reviewed-by tag from Mani

Changes in v2:
 - Added Acked-by tag from Rob

 include/dt-bindings/clock/actions,s500-cmu.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h
index a250a52a6192..a237eb26accb 100644
--- a/include/dt-bindings/clock/actions,s500-cmu.h
+++ b/include/dt-bindings/clock/actions,s500-cmu.h
@@ -74,10 +74,12 @@
 #define CLK_RMII_REF		54
 #define CLK_GPIO		55
 
-/* system clock (part 2) */
+/* additional clocks */
 #define CLK_APB			56
 #define CLK_DMAC		57
+#define CLK_NIC			58
+#define CLK_ETHERNET		59
 
-#define CLK_NR_CLKS		(CLK_DMAC + 1)
+#define CLK_NR_CLKS		(CLK_ETHERNET + 1)
 
 #endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */
-- 
2.32.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC
  2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
                   ` (4 preceding siblings ...)
  2021-06-10 20:05 ` [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions " Cristian Ciocaltea
@ 2021-06-10 20:05 ` Cristian Ciocaltea
  2021-06-28  1:47   ` Stephen Boyd
  2021-06-16 16:06 ` [PATCH v3 0/6] Improve " Cristian Ciocaltea
  6 siblings, 1 reply; 15+ messages in thread
From: Cristian Ciocaltea @ 2021-06-10 20:05 UTC (permalink / raw)
  To: Stephen Boyd, Rob Herring, Manivannan Sadhasivam,
	Andreas Färber, Michael Turquette, Edgar Bernardi Righi
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

Add support for the missing NIC and ETHERNET clocks in the Actions Semi
Owl S500 SoC clock driver.

Additionally, change APB clock parent from AHB to the newly added NIC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v3:
 - Added Reviewed-by tag from Mani

Changes in v2:
 - Reordered "nic_clk_mux_p" after "ahbprediv_clk_mux_p" to follow the reg
   field ordering

 drivers/clk/actions/owl-s500.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index cbeb51c804eb..57d06e183dff 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -113,6 +113,7 @@ static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
 static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
 static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
 static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
+static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
 static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
 static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
 static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
@@ -194,7 +195,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
 
 /* divider clocks */
 static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
-static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
+static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
 static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
 
 /* factor clocks */
@@ -202,6 +203,12 @@ static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table
 static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
 
 /* composite clocks */
+static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p,
+			OWL_MUX_HW(CMU_BUSCLK1, 4, 3),
+			{ 0 },
+			OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL),
+			0);
+
 static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
 			OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
 			{ 0 },
@@ -317,6 +324,10 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
 			OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
 			1, 5, 0);
 
+static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk",
+			OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
+			1, 20, 0);
+
 static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
 			OWL_MUX_HW(CMU_UART0CLK, 16, 1),
 			OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
@@ -451,6 +462,8 @@ static struct owl_clk_common *s500_clks[] = {
 	&apb_clk.common,
 	&dmac_clk.common,
 	&gpio_clk.common,
+	&nic_clk.common,
+	&ethernet_clk.common,
 };
 
 static struct clk_hw_onecell_data s500_hw_clks = {
@@ -510,6 +523,8 @@ static struct clk_hw_onecell_data s500_hw_clks = {
 		[CLK_APB]		= &apb_clk.common.hw,
 		[CLK_DMAC]		= &dmac_clk.common.hw,
 		[CLK_GPIO]		= &gpio_clk.common.hw,
+		[CLK_NIC]		= &nic_clk.common.hw,
+		[CLK_ETHERNET]		= &ethernet_clk.common.hw,
 	},
 	.num = CLK_NR_CLKS,
 };
-- 
2.32.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
  2021-06-10 20:05 ` [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain " Cristian Ciocaltea
@ 2021-06-11  4:11   ` Manivannan Sadhasivam
  2021-06-28  1:47   ` Stephen Boyd
  1 sibling, 0 replies; 15+ messages in thread
From: Manivannan Sadhasivam @ 2021-06-11  4:11 UTC (permalink / raw)
  To: Cristian Ciocaltea
  Cc: Stephen Boyd, Rob Herring, Andreas Färber,
	Michael Turquette, Edgar Bernardi Righi, linux-clk,
	linux-arm-kernel, linux-actions, linux-kernel, devicetree

On Thu, Jun 10, 2021 at 11:05:24PM +0300, Cristian Ciocaltea wrote:
> There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> clock chain involving AHPPREDIV, H and AHB clocks:
> 
> * AHBPREDIV clock is defined as a muxer only, although it also acts as
>   a divider.
> * H clock is using a wrong divider register offset
> * AHB is defined as a multi-rate factor clock, but it is actually just
>   a fixed pass clock.
> 
> Let's provide the following fixes:
> 
> * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition.
> * Use the correct register shift value in the OWL_DIVIDER definition
>   for H clock
> * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an
>   ungated OWL_COMP_FIXED_FACTOR definition.
> 
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
> Changes in v3:
>  - Fixed the swapped flags between "ahbprediv_clk" and "ahb_clk" as noticed
>    by Mani
> 
> Changes in v2:
>  - Reverted the addition of the clock div table for H clock to support the
>    '1' divider (according to the datasheet), even though the vendor
>    implementation marks it as reserved
>  
>  drivers/clk/actions/owl-s500.c | 19 +++++++++++--------
>  1 file changed, 11 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index 42d6899755e6..cbeb51c804eb 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -153,11 +153,6 @@ static struct clk_factor_table hde_factor_table[] = {
>  	{ 0, 0, 0 },
>  };
>  
> -static struct clk_factor_table ahb_factor_table[] = {
> -	{ 1, 1, 2 }, { 2, 1, 3 },
> -	{ 0, 0, 0 },
> -};
> -
>  static struct clk_div_table rmii_ref_div_table[] = {
>  	{ 0, 4 }, { 1, 10 },
>  	{ 0, 0 },
> @@ -186,7 +181,6 @@ static struct clk_div_table nand_div_table[] = {
>  
>  /* mux clock */
>  static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
> -static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
>  
>  /* gate clocks */
>  static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
> @@ -199,16 +193,25 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
>  static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
>  
>  /* divider clocks */
> -static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
>  static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
>  static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
>  
>  /* factor clocks */
> -static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
>  static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
>  static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
>  
>  /* composite clocks */
> +static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
> +			OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
> +			{ 0 },
> +			OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
> +			CLK_SET_RATE_PARENT);
> +
> +static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
> +			{ 0 },
> +			1, 1, 0);
> +
>  static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
>  			OWL_MUX_HW(CMU_VCECLK, 4, 2),
>  			OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
> -- 
> 2.32.0
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v3 0/6] Improve clock support for Actions S500 SoC
  2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
                   ` (5 preceding siblings ...)
  2021-06-10 20:05 ` [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support " Cristian Ciocaltea
@ 2021-06-16 16:06 ` Cristian Ciocaltea
  6 siblings, 0 replies; 15+ messages in thread
From: Cristian Ciocaltea @ 2021-06-16 16:06 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Rob Herring, Manivannan Sadhasivam, Andreas Färber,
	Michael Turquette, Edgar Bernardi Righi, linux-clk,
	linux-arm-kernel, linux-actions, linux-kernel, devicetree

Hi Stephen,

Could you please pick up this patch series since there are some more
patches ready for merging which depend on it?

Thanks,
Cristi

On Thu, Jun 10, 2021 at 11:05:20PM +0300, Cristian Ciocaltea wrote:
> While working on a driver to support the Actions Semi Owl Ethernet MAC,
> I found and fixed some issues on the existing implementation of the S500
> SoC clock subsystem and, additionally, I added two missing clocks.
> 
> Thanks,
> Cristi
> 
> Changes in v3:
> - Fixed swapped flags between "ahbprediv_clk" and "ahb_clk" in patch 4/6
> - Added Reviewed-by tags from Mani
> - Rebased patch series on v5.13-rc5
> 
> Changes in v2 (according to Mani's review):
> - Re-added entry "{ 24, 1, 25 }" to sd_factor_table, according to the
>   datasheet (V1.8+), this is a valid divider
> - Re-added OWL_GATE_HW to SENSOR[0-1], according to the datasheet they
>   are gated, even though the vendor implementation states the opposite
> - Reverted the addition of the clock div table for H clock to support the
>   '1' divider (according to the datasheet), even though the vendor
>   implementation marks it as reserved
> - Reordered "nic_clk_mux_p" after "ahbprediv_clk_mux_p" to follow the reg
>   field ordering
> - Rebased patch series on v5.13-rc3
> 
> Cristian Ciocaltea (6):
>   clk: actions: Fix UART clock dividers on Owl S500 SoC
>   clk: actions: Fix SD clocks factor table on Owl S500 SoC
>   clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC
>   clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
>   dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC
>   clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC
> 
>  drivers/clk/actions/owl-s500.c               | 92 +++++++++++++-------
>  include/dt-bindings/clock/actions,s500-cmu.h |  6 +-
>  2 files changed, 65 insertions(+), 33 deletions(-)
> 
> -- 
> 2.32.0
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl S500 SoC
  2021-06-10 20:05 ` [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl " Cristian Ciocaltea
@ 2021-06-28  1:46   ` Stephen Boyd
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2021-06-28  1:46 UTC (permalink / raw)
  To: Andreas Färber, Cristian Ciocaltea, Edgar Bernardi Righi,
	Manivannan Sadhasivam, Michael Turquette, Rob Herring
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

Quoting Cristian Ciocaltea (2021-06-10 13:05:21)
> Use correct divider registers for the Actions Semi Owl S500 SoC's UART
> clocks.
> 
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v3 2/6] clk: actions: Fix SD clocks factor table on Owl S500 SoC
  2021-06-10 20:05 ` [PATCH v3 2/6] clk: actions: Fix SD clocks factor table " Cristian Ciocaltea
@ 2021-06-28  1:47   ` Stephen Boyd
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2021-06-28  1:47 UTC (permalink / raw)
  To: Andreas Färber, Cristian Ciocaltea, Edgar Bernardi Righi,
	Manivannan Sadhasivam, Michael Turquette, Rob Herring
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

Quoting Cristian Ciocaltea (2021-06-10 13:05:22)
> Drop the unsupported entries in the factor table used for the SD[0-2]
> clocks definitions on the Actions Semi Owl S500 SoC.
> 
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC
  2021-06-10 20:05 ` [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks " Cristian Ciocaltea
@ 2021-06-28  1:47   ` Stephen Boyd
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2021-06-28  1:47 UTC (permalink / raw)
  To: Andreas Färber, Cristian Ciocaltea, Edgar Bernardi Righi,
	Manivannan Sadhasivam, Michael Turquette, Rob Herring
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

Quoting Cristian Ciocaltea (2021-06-10 13:05:23)
> The following clocks of the Actions Semi Owl S500 SoC have been defined
> to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE,
> VDE, BISP, SENSOR[0-1]
> 
> There are several issues involved in this approach:
> 
> * 'bisp_factor_table[]' describes the configuration of a regular 8-rates
>   divider, so its usage is redundant. Additionally, judging by the BISP
>   clock context, it is incomplete since it maps only 8 out of 12
>   possible entries.
> 
> * The clocks mentioned above are not identical in terms of the available
>   rates, therefore cannot rely on the same factor table. Specifically,
>   BISP and SENSOR* are standard 12-rate dividers so their configuration
>   should rely on a proper clock div table, while VCE and VDE require a
>   factor table that is a actually a subset of the one needed for DE[1-2]
>   clocks.
> 
> Let's fix this by implementing the following:
> 
> * Add new factor tables 'de_factor_table' and 'hde_factor_table' to
>   properly handle DE[1-2], VCE and VDE clocks.
> 
> * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1]
>   clocks converted to OWL_COMP_DIV.
> 
> * Drop the now unused 'bisp_factor_table[]'.
> 
> Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since
> there is no reason to always keep ON those clocks.
> 
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
  2021-06-10 20:05 ` [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain " Cristian Ciocaltea
  2021-06-11  4:11   ` Manivannan Sadhasivam
@ 2021-06-28  1:47   ` Stephen Boyd
  1 sibling, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2021-06-28  1:47 UTC (permalink / raw)
  To: Andreas Färber, Cristian Ciocaltea, Edgar Bernardi Righi,
	Manivannan Sadhasivam, Michael Turquette, Rob Herring
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

Quoting Cristian Ciocaltea (2021-06-10 13:05:24)
> There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> clock chain involving AHPPREDIV, H and AHB clocks:
> 
> * AHBPREDIV clock is defined as a muxer only, although it also acts as
>   a divider.
> * H clock is using a wrong divider register offset
> * AHB is defined as a multi-rate factor clock, but it is actually just
>   a fixed pass clock.
> 
> Let's provide the following fixes:
> 
> * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition.
> * Use the correct register shift value in the OWL_DIVIDER definition
>   for H clock
> * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an
>   ungated OWL_COMP_FIXED_FACTOR definition.
> 
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC
  2021-06-10 20:05 ` [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions " Cristian Ciocaltea
@ 2021-06-28  1:47   ` Stephen Boyd
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2021-06-28  1:47 UTC (permalink / raw)
  To: Andreas Färber, Cristian Ciocaltea, Edgar Bernardi Righi,
	Manivannan Sadhasivam, Michael Turquette, Rob Herring
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel,
	devicetree, Rob Herring

Quoting Cristian Ciocaltea (2021-06-10 13:05:25)
> Add the missing NIC and ETHERNET clock bindings constants for Actions
> Semi Owl S500 SoC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC
  2021-06-10 20:05 ` [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support " Cristian Ciocaltea
@ 2021-06-28  1:47   ` Stephen Boyd
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2021-06-28  1:47 UTC (permalink / raw)
  To: Andreas Färber, Cristian Ciocaltea, Edgar Bernardi Righi,
	Manivannan Sadhasivam, Michael Turquette, Rob Herring
  Cc: linux-clk, linux-arm-kernel, linux-actions, linux-kernel, devicetree

Quoting Cristian Ciocaltea (2021-06-10 13:05:26)
> Add support for the missing NIC and ETHERNET clocks in the Actions Semi
> Owl S500 SoC clock driver.
> 
> Additionally, change APB clock parent from AHB to the newly added NIC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2021-06-28  1:47 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
2021-06-10 20:05 ` [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl " Cristian Ciocaltea
2021-06-28  1:46   ` Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 2/6] clk: actions: Fix SD clocks factor table " Cristian Ciocaltea
2021-06-28  1:47   ` Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks " Cristian Ciocaltea
2021-06-28  1:47   ` Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain " Cristian Ciocaltea
2021-06-11  4:11   ` Manivannan Sadhasivam
2021-06-28  1:47   ` Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions " Cristian Ciocaltea
2021-06-28  1:47   ` Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support " Cristian Ciocaltea
2021-06-28  1:47   ` Stephen Boyd
2021-06-16 16:06 ` [PATCH v3 0/6] Improve " Cristian Ciocaltea

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).