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[94.29.10.250]) by smtp.googlemail.com with ESMTPSA id q27sm6080287lfn.96.2019.10.29.05.50.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Oct 2019 05:50:23 -0700 (PDT) Subject: Re: [PATCH v2 1/2] clk: tegra: divider: Add missing check for enable-bit on rate's recalculation From: Dmitry Osipenko To: Peter De Schrijver Cc: Michael Turquette , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Stephen Boyd , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190723025245.27754-1-digetx@gmail.com> <20191028142753.GC27141@pdeschrijver-desktop.Nvidia.com> <62c375bd-09ae-e09f-6ca2-c1395eebc5fa@gmail.com> Message-ID: <1dfd0270-b8d7-da22-46dd-7efc907d5655@gmail.com> Date: Tue, 29 Oct 2019 15:50:22 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <62c375bd-09ae-e09f-6ca2-c1395eebc5fa@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 29.10.2019 03:14, Dmitry Osipenko пишет: > 28.10.2019 17:27, Peter De Schrijver пишет: >> On Tue, Jul 23, 2019 at 05:52:44AM +0300, Dmitry Osipenko wrote: >>> Unset "enable" bit means that divider is in bypass mode, hence it doesn't >>> have any effect in that case. Please note that there are no known bugs >>> caused by the missing check. >>> >> >> Technically this is not quite true, but for the purposes of CCF you can >> treat it that way. This bits defines if the value in the lower 16 bits >> of the divider register is used to configure the divider or if the >> contents of the UART DLM/DLL registers is used. So the divider isn't >> actually bypassed, it's just configured differently. >> In practice this bit is only set when the divider is non-zero when doing >> set rate. So the extra test isn't strictly needed as long as the sw >> running before the kernel also ensures the bit is only set when the >> divider is non-zero. >> >> Acked-by: Peter De Schrijver > > Thank you for the clarification. I hope that bootloader doesn't enable > the divider because it looks like standard 8250 driver won't be ready > for that. But serial-tegra driver seems should be good. Actually, it should be good because I missed that UART clocks are per-initialized in the clk driver init table. I'll update commit's message and send a new version of this patch.