From: Jeremy Kerr <jk@ozlabs.org>
To: Joel Stanley <joel@jms.id.au>, Oskar Senft <osk@google.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
stable@vger.kernel.org
Subject: Re: [PATCH] ARM: aspeed: g5: Do not set sirq polarity
Date: Thu, 27 Aug 2020 14:27:02 +0800 [thread overview]
Message-ID: <1e56af7945b93a22e31ba6d81da82cbdb1b237b6.camel@ozlabs.org> (raw)
In-Reply-To: <20200812112400.2406734-1-joel@jms.id.au>
Hi Joel,
> A feature was added to the aspeed vuart driver to configure the vuart
> interrupt (sirq) polarity according to the LPC/eSPI strapping register.
>
> Systems that depend on a active low behaviour (sirq_polarity set to 0)
> such as OpenPower boxes also use LPC, so this relationship does not
> hold.
>
> The property was added for a Tyan S7106 system which is not supported
> in the kernel tree. Should this or other systems wish to use this
> feature of the driver they should add it to the machine specific device
> tree.
>
> Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...")
> Cc: stable@vger.kernel.org
> Signed-off-by: Joel Stanley <joel@jms.id.au>
LGTM. I've tested this on the s2600st, which is strapped for eSPI. All
good there too, as expected.
Tested-by: Jeremy Kerr <jk@ozlabs.org>
and/or:
Reviewed-by: Jeremy Kerr <jk@ozlabs.org>
Cheers,
Jeremy
next prev parent reply other threads:[~2020-08-27 6:27 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-12 11:24 [PATCH] ARM: aspeed: g5: Do not set sirq polarity Joel Stanley
2020-08-27 6:27 ` Jeremy Kerr [this message]
2020-09-09 7:22 ` Joel Stanley
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