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* [PATCH 0/3] PCI: J721E: Fix Broken DT w.r.t SYSCON DT
@ 2020-11-16 17:31 Kishon Vijay Abraham I
  2020-11-16 17:31 ` [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Kishon Vijay Abraham I
                   ` (2 more replies)
  0 siblings, 3 replies; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-11-16 17:31 UTC (permalink / raw)
  To: Tero Kristo, Nishanth Menon, Rob Herring, Tom Joseph,
	Lorenzo Pieralisi, Bjorn Helgaas
  Cc: linux-omap, Kishon Vijay Abraham I, linux-arm-kernel, devicetree,
	linux-pci, linux-kernel

Previously a subnode to syscon node was added which has the
exact memory mapped address of pcie_ctrl but based on review comment
provided by Rob [1], the offset is now being passed as argument to
"ti,syscon-pcie-ctrl" phandle.

This series has both driver change and DT change and both has to
get in together in the -rc cycle.

[1] -> Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Kishon Vijay Abraham I (3):
  dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl"
    phandle arg
  arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
    pcieX_ctrl

 .../bindings/pci/ti,j721e-pci-ep.yaml         | 12 +++--
 .../bindings/pci/ti,j721e-pci-host.yaml       | 12 +++--
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 48 ++++---------------
 drivers/pci/controller/cadence/pci-j721e.c    | 28 +++++++----
 4 files changed, 43 insertions(+), 57 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  2020-11-16 17:31 [PATCH 0/3] PCI: J721E: Fix Broken DT w.r.t SYSCON DT Kishon Vijay Abraham I
@ 2020-11-16 17:31 ` Kishon Vijay Abraham I
  2020-11-18 21:11   ` Rob Herring
  2020-11-19 13:41   ` [PATCH 1/3] dt-bindings: pci: ti, j721e: Fix "ti, syscon-pcie-ctrl" " Rob Herring
  2020-11-16 17:31 ` [PATCH 2/3] PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg Kishon Vijay Abraham I
  2020-11-16 17:31 ` [PATCH 3/3] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl Kishon Vijay Abraham I
  2 siblings, 2 replies; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-11-16 17:31 UTC (permalink / raw)
  To: Tero Kristo, Nishanth Menon, Rob Herring, Tom Joseph,
	Lorenzo Pieralisi, Bjorn Helgaas
  Cc: linux-omap, Kishon Vijay Abraham I, linux-arm-kernel, devicetree,
	linux-pci, linux-kernel

Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
argument. The argument is the register offset within "syscon" used to
configure PCIe controller.

Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
 .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 3ae3e1a2d4b0..e9685c0bdc3e 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -29,9 +29,13 @@ properties:
       - const: mem
 
   ti,syscon-pcie-ctrl:
-    description: Phandle to the SYSCON entry required for configuring PCIe mode
-                 and link speed.
-    $ref: /schemas/types.yaml#/definitions/phandle
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle-array
+      - items:
+          - items:
+            - description: Phandle to the SYSCON entry
+            - description: pcie_ctrl register offset within SYSCON
+    description: Specifier for configuring PCIe mode and link speed.
 
   power-domains:
     maxItems: 1
@@ -80,7 +84,7 @@ examples:
                  <0x00 0x0d000000 0x00 0x00800000>,
                  <0x00 0x10000000 0x00 0x08000000>;
            reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-           ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
            max-link-speed = <3>;
            num-lanes = <2>;
            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index ee7a8eade3f6..a3b82992bcfa 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -29,9 +29,13 @@ properties:
       - const: cfg
 
   ti,syscon-pcie-ctrl:
-    description: Phandle to the SYSCON entry required for configuring PCIe mode
-      and link speed.
-    $ref: /schemas/types.yaml#/definitions/phandle
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle-array
+      - items:
+          - items:
+            - description: Phandle to the SYSCON entry
+            - description: pcie_ctrl register offset within SYSCON
+    description: Specifier for configuring PCIe mode and link speed.
 
   power-domains:
     maxItems: 1
@@ -90,7 +94,7 @@ examples:
                   <0x00 0x0d000000 0x00 0x00800000>,
                   <0x00 0x10000000 0x00 0x00001000>;
             reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
-            ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
             max-link-speed = <3>;
             num-lanes = <2>;
             power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 2/3] PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
  2020-11-16 17:31 [PATCH 0/3] PCI: J721E: Fix Broken DT w.r.t SYSCON DT Kishon Vijay Abraham I
  2020-11-16 17:31 ` [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Kishon Vijay Abraham I
@ 2020-11-16 17:31 ` Kishon Vijay Abraham I
  2020-11-16 17:31 ` [PATCH 3/3] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl Kishon Vijay Abraham I
  2 siblings, 0 replies; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-11-16 17:31 UTC (permalink / raw)
  To: Tero Kristo, Nishanth Menon, Rob Herring, Tom Joseph,
	Lorenzo Pieralisi, Bjorn Helgaas
  Cc: linux-omap, Kishon Vijay Abraham I, linux-arm-kernel, devicetree,
	linux-pci, linux-kernel

Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl"
phandle. Previously a subnode to "syscon" node was added which has the
exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl
within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl"
phandle.

Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 28 +++++++++++++++-------
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 586b9d69fa5e..d615e6313252 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -12,6 +12,7 @@
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/mfd/syscon.h>
+#include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_irq.h>
 #include <linux/pci.h>
@@ -153,7 +154,8 @@ static const struct cdns_pcie_ops j721e_pcie_ops = {
 	.link_up = j721e_pcie_link_up,
 };
 
-static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
+static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
+			       unsigned int offset)
 {
 	struct device *dev = pcie->dev;
 	u32 mask = J721E_MODE_RC;
@@ -164,7 +166,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
 	if (mode == PCI_MODE_RC)
 		val = J721E_MODE_RC;
 
-	ret = regmap_update_bits(syscon, 0, mask, val);
+	ret = regmap_update_bits(syscon, offset, mask, val);
 	if (ret)
 		dev_err(dev, "failed to set pcie mode\n");
 
@@ -172,7 +174,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
 }
 
 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
-				     struct regmap *syscon)
+				     struct regmap *syscon, unsigned int offset)
 {
 	struct device *dev = pcie->dev;
 	struct device_node *np = dev->of_node;
@@ -185,7 +187,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
 		link_speed = 2;
 
 	val = link_speed - 1;
-	ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val);
+	ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
 	if (ret)
 		dev_err(dev, "failed to set link speed\n");
 
@@ -193,7 +195,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
 }
 
 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
-				     struct regmap *syscon)
+				     struct regmap *syscon, unsigned int offset)
 {
 	struct device *dev = pcie->dev;
 	u32 lanes = pcie->num_lanes;
@@ -201,7 +203,7 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
 	int ret;
 
 	val = LANE_COUNT(lanes - 1);
-	ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val);
+	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
 	if (ret)
 		dev_err(dev, "failed to set link count\n");
 
@@ -212,6 +214,7 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	struct device_node *node = dev->of_node;
+	struct of_phandle_args args;
 	struct regmap *syscon;
 	int ret;
 
@@ -221,19 +224,26 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
 		return PTR_ERR(syscon);
 	}
 
-	ret = j721e_pcie_set_mode(pcie, syscon);
+	ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
+					       0, &args);
+	if (ret) {
+		dev_err(dev, "failed to parse ti,syscon-pcie-ctrl\n");
+		return ret;
+	}
+
+	ret = j721e_pcie_set_mode(pcie, syscon, args.args[0]);
 	if (ret < 0) {
 		dev_err(dev, "Failed to set pci mode\n");
 		return ret;
 	}
 
-	ret = j721e_pcie_set_link_speed(pcie, syscon);
+	ret = j721e_pcie_set_link_speed(pcie, syscon, args.args[0]);
 	if (ret < 0) {
 		dev_err(dev, "Failed to set link speed\n");
 		return ret;
 	}
 
-	ret = j721e_pcie_set_lane_count(pcie, syscon);
+	ret = j721e_pcie_set_lane_count(pcie, syscon, args.args[0]);
 	if (ret < 0) {
 		dev_err(dev, "Failed to set num-lanes\n");
 		return ret;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 3/3] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl
  2020-11-16 17:31 [PATCH 0/3] PCI: J721E: Fix Broken DT w.r.t SYSCON DT Kishon Vijay Abraham I
  2020-11-16 17:31 ` [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Kishon Vijay Abraham I
  2020-11-16 17:31 ` [PATCH 2/3] PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg Kishon Vijay Abraham I
@ 2020-11-16 17:31 ` Kishon Vijay Abraham I
  2020-11-18 21:14   ` Rob Herring
  2 siblings, 1 reply; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-11-16 17:31 UTC (permalink / raw)
  To: Tero Kristo, Nishanth Menon, Rob Herring, Tom Joseph,
	Lorenzo Pieralisi, Bjorn Helgaas
  Cc: linux-omap, Kishon Vijay Abraham I, linux-arm-kernel, devicetree,
	linux-pci, linux-kernel

Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node
point to the parent with an offset argument.

Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ++++-------------------
 1 file changed, 8 insertions(+), 40 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 620e69e42974..23a0024dda79 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -28,38 +28,6 @@
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x00100000 0x1c000>;
 
-		pcie0_ctrl: syscon@4070 {
-			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
-			reg = <0x00004070 0x4>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x4070 0x4070 0x4>;
-		};
-
-		pcie1_ctrl: syscon@4074 {
-			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
-			reg = <0x00004074 0x4>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x4074 0x4074 0x4>;
-		};
-
-		pcie2_ctrl: syscon@4078 {
-			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
-			reg = <0x00004078 0x4>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x4078 0x4078 0x4>;
-		};
-
-		pcie3_ctrl: syscon@407c {
-			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
-			reg = <0x0000407c 0x4>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x407c 0x407c 0x4>;
-		};
-
 		serdes_ln_ctrl: mux@4080 {
 			compatible = "mmio-mux";
 			reg = <0x00004080 0x50>;
@@ -619,7 +587,7 @@
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
 		device_type = "pci";
-		ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
@@ -646,7 +614,7 @@
 		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
-		ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
@@ -668,7 +636,7 @@
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 		device_type = "pci";
-		ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
@@ -695,7 +663,7 @@
 		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
-		ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
@@ -717,7 +685,7 @@
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
 		device_type = "pci";
-		ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
@@ -744,7 +712,7 @@
 		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
-		ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
@@ -766,7 +734,7 @@
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
 		device_type = "pci";
-		ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
@@ -793,7 +761,7 @@
 		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
-		ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  2020-11-16 17:31 ` [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Kishon Vijay Abraham I
@ 2020-11-18 21:11   ` Rob Herring
  2020-11-20  5:09     ` Kishon Vijay Abraham I
  2020-11-19 13:41   ` [PATCH 1/3] dt-bindings: pci: ti, j721e: Fix "ti, syscon-pcie-ctrl" " Rob Herring
  1 sibling, 1 reply; 10+ messages in thread
From: Rob Herring @ 2020-11-18 21:11 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: Tero Kristo, Nishanth Menon, Tom Joseph, Lorenzo Pieralisi,
	Bjorn Helgaas, linux-omap, linux-arm-kernel, devicetree,
	linux-pci, linux-kernel

On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
> argument. The argument is the register offset within "syscon" used to
> configure PCIe controller.
> 
> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Link: Link: ?

AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1 
Link would be okay though.

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
>  2 files changed, 16 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> index 3ae3e1a2d4b0..e9685c0bdc3e 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> @@ -29,9 +29,13 @@ properties:
>        - const: mem
>  
>    ti,syscon-pcie-ctrl:
> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
> -                 and link speed.
> -    $ref: /schemas/types.yaml#/definitions/phandle
> +    allOf:

You no longer need allOf here.

> +      - $ref: /schemas/types.yaml#/definitions/phandle-array
> +      - items:
> +          - items:
> +            - description: Phandle to the SYSCON entry
> +            - description: pcie_ctrl register offset within SYSCON
> +    description: Specifier for configuring PCIe mode and link speed.
>  
>    power-domains:
>      maxItems: 1
> @@ -80,7 +84,7 @@ examples:
>                   <0x00 0x0d000000 0x00 0x00800000>,
>                   <0x00 0x10000000 0x00 0x08000000>;
>             reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> -           ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
> +           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
>             max-link-speed = <3>;
>             num-lanes = <2>;
>             power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> index ee7a8eade3f6..a3b82992bcfa 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> @@ -29,9 +29,13 @@ properties:
>        - const: cfg
>  
>    ti,syscon-pcie-ctrl:
> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
> -      and link speed.
> -    $ref: /schemas/types.yaml#/definitions/phandle
> +    allOf:
> +      - $ref: /schemas/types.yaml#/definitions/phandle-array
> +      - items:
> +          - items:
> +            - description: Phandle to the SYSCON entry
> +            - description: pcie_ctrl register offset within SYSCON
> +    description: Specifier for configuring PCIe mode and link speed.
>  
>    power-domains:
>      maxItems: 1
> @@ -90,7 +94,7 @@ examples:
>                    <0x00 0x0d000000 0x00 0x00800000>,
>                    <0x00 0x10000000 0x00 0x00001000>;
>              reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> -            ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
> +            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
>              max-link-speed = <3>;
>              num-lanes = <2>;
>              power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 3/3] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl
  2020-11-16 17:31 ` [PATCH 3/3] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl Kishon Vijay Abraham I
@ 2020-11-18 21:14   ` Rob Herring
  0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-11-18 21:14 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: Tero Kristo, Nishanth Menon, Tom Joseph, Lorenzo Pieralisi,
	Bjorn Helgaas, linux-omap, linux-arm-kernel, devicetree,
	linux-pci, linux-kernel

On Mon, Nov 16, 2020 at 11:01:41PM +0530, Kishon Vijay Abraham I wrote:
> Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node
> point to the parent with an offset argument.

This should say breaks compatibility, but that fine because ????. It 
only landed in 5.9 and a new platform I suppose. 

> 
> Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Should have a Fixes tag IMO.

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ++++-------------------
>  1 file changed, 8 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 620e69e42974..23a0024dda79 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -28,38 +28,6 @@
>  		#size-cells = <1>;
>  		ranges = <0x0 0x0 0x00100000 0x1c000>;
>  
> -		pcie0_ctrl: syscon@4070 {
> -			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
> -			reg = <0x00004070 0x4>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges = <0x4070 0x4070 0x4>;
> -		};
> -
> -		pcie1_ctrl: syscon@4074 {
> -			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
> -			reg = <0x00004074 0x4>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges = <0x4074 0x4074 0x4>;
> -		};
> -
> -		pcie2_ctrl: syscon@4078 {
> -			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
> -			reg = <0x00004078 0x4>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges = <0x4078 0x4078 0x4>;
> -		};
> -
> -		pcie3_ctrl: syscon@407c {
> -			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
> -			reg = <0x0000407c 0x4>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges = <0x407c 0x407c 0x4>;
> -		};
> -
>  		serdes_ln_ctrl: mux@4080 {
>  			compatible = "mmio-mux";
>  			reg = <0x00004080 0x50>;
> @@ -619,7 +587,7 @@
>  		interrupt-names = "link_state";
>  		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
>  		device_type = "pci";
> -		ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
> +		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
>  		max-link-speed = <3>;
>  		num-lanes = <2>;
>  		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> @@ -646,7 +614,7 @@
>  		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>  		interrupt-names = "link_state";
>  		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
> -		ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
> +		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
>  		max-link-speed = <3>;
>  		num-lanes = <2>;
>  		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> @@ -668,7 +636,7 @@
>  		interrupt-names = "link_state";
>  		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>  		device_type = "pci";
> -		ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
> +		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>  		max-link-speed = <3>;
>  		num-lanes = <2>;
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> @@ -695,7 +663,7 @@
>  		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>  		interrupt-names = "link_state";
>  		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> -		ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
> +		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>  		max-link-speed = <3>;
>  		num-lanes = <2>;
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> @@ -717,7 +685,7 @@
>  		interrupt-names = "link_state";
>  		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
>  		device_type = "pci";
> -		ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
> +		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
>  		max-link-speed = <3>;
>  		num-lanes = <2>;
>  		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
> @@ -744,7 +712,7 @@
>  		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>  		interrupt-names = "link_state";
>  		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
> -		ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
> +		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
>  		max-link-speed = <3>;
>  		num-lanes = <2>;
>  		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
> @@ -766,7 +734,7 @@
>  		interrupt-names = "link_state";
>  		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
>  		device_type = "pci";
> -		ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
> +		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
>  		max-link-speed = <3>;
>  		num-lanes = <2>;
>  		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
> @@ -793,7 +761,7 @@
>  		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>  		interrupt-names = "link_state";
>  		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
> -		ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
> +		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
>  		max-link-speed = <3>;
>  		num-lanes = <2>;
>  		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/3] dt-bindings: pci: ti, j721e: Fix "ti, syscon-pcie-ctrl" to take argument
  2020-11-16 17:31 ` [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Kishon Vijay Abraham I
  2020-11-18 21:11   ` Rob Herring
@ 2020-11-19 13:41   ` Rob Herring
  1 sibling, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-11-19 13:41 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: Tero Kristo, Rob Herring, Tom Joseph, Bjorn Helgaas,
	linux-arm-kernel, linux-kernel, Nishanth Menon, linux-pci,
	linux-omap, devicetree, Lorenzo Pieralisi

On Mon, 16 Nov 2020 23:01:39 +0530, Kishon Vijay Abraham I wrote:
> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
> argument. The argument is the register offset within "syscon" used to
> configure PCIe controller.
> 
> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
>  2 files changed, 16 insertions(+), 8 deletions(-)
> 


My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:36:13: [warning] wrong indentation: expected 14 but found 12 (indentation)
./Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml:36:13: [warning] wrong indentation: expected 14 but found 12 (indentation)

dtschema/dtc warnings/errors:


See https://patchwork.ozlabs.org/patch/1401067

The base for the patch is generally the last rc1. Any dependencies
should be noted.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  2020-11-18 21:11   ` Rob Herring
@ 2020-11-20  5:09     ` Kishon Vijay Abraham I
  2020-11-26 12:53       ` Kishon Vijay Abraham I
  0 siblings, 1 reply; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-11-20  5:09 UTC (permalink / raw)
  To: Rob Herring, Lorenzo Pieralisi
  Cc: Tero Kristo, Nishanth Menon, Tom Joseph, Bjorn Helgaas,
	linux-omap, linux-arm-kernel, devicetree, linux-pci,
	linux-kernel

Hi Rob,

On 19/11/20 2:41 am, Rob Herring wrote:
> On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
>> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
>> argument. The argument is the register offset within "syscon" used to
>> configure PCIe controller.
>>
>> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
> 
> Link: Link: ?
> 
> AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1 
> Link would be okay though.

Two Links was a typo, will fix it in the next revision. Nishanth as well
was asking about using "Link:" tag for a mailing list discussion.

I started using it after Lorenzo had asked me to use Link tag for
mailing list discussion here sometime back.

https://patchwork.kernel.org/project/linux-pci/patch/20171219083627.7904-1-kishon@ti.com/#21350261

> 
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
>>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
>>  2 files changed, 16 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> index 3ae3e1a2d4b0..e9685c0bdc3e 100644
>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> @@ -29,9 +29,13 @@ properties:
>>        - const: mem
>>  
>>    ti,syscon-pcie-ctrl:
>> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
>> -                 and link speed.
>> -    $ref: /schemas/types.yaml#/definitions/phandle
>> +    allOf:
> 
> You no longer need allOf here.

hmm, don't we need it for specifying phandle with fixed cells? FWIW, I
was referring

https://github.com/devicetree-org/dt-schema/blob/master/test/schemas/good-example.yaml#L187

Thank You,
Kishon

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  2020-11-20  5:09     ` Kishon Vijay Abraham I
@ 2020-11-26 12:53       ` Kishon Vijay Abraham I
  2020-11-30 16:12         ` Rob Herring
  0 siblings, 1 reply; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-11-26 12:53 UTC (permalink / raw)
  To: Rob Herring, Lorenzo Pieralisi
  Cc: Tero Kristo, Nishanth Menon, Tom Joseph, Bjorn Helgaas,
	linux-omap, linux-arm-kernel, devicetree, linux-pci,
	linux-kernel

Hi Rob,

On 20/11/20 10:39 am, Kishon Vijay Abraham I wrote:
> Hi Rob,
> 
> On 19/11/20 2:41 am, Rob Herring wrote:
>> On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
>>> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
>>> argument. The argument is the register offset within "syscon" used to
>>> configure PCIe controller.
>>>
>>> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
>>
>> Link: Link: ?
>>
>> AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1 
>> Link would be okay though.
> 
> Two Links was a typo, will fix it in the next revision. Nishanth as well
> was asking about using "Link:" tag for a mailing list discussion.
> 
> I started using it after Lorenzo had asked me to use Link tag for
> mailing list discussion here sometime back.
> 
> https://patchwork.kernel.org/project/linux-pci/patch/20171219083627.7904-1-kishon@ti.com/#21350261
> 
>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> ---
>>>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
>>>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
>>>  2 files changed, 16 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>>> index 3ae3e1a2d4b0..e9685c0bdc3e 100644
>>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>>> @@ -29,9 +29,13 @@ properties:
>>>        - const: mem
>>>  
>>>    ti,syscon-pcie-ctrl:
>>> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
>>> -                 and link speed.
>>> -    $ref: /schemas/types.yaml#/definitions/phandle
>>> +    allOf:
>>
>> You no longer need allOf here.
> 
> hmm, don't we need it for specifying phandle with fixed cells? FWIW, I
> was referring
> 
> https://github.com/devicetree-org/dt-schema/blob/master/test/schemas/good-example.yaml#L187

Can you clarify this please?

Thank You,
Kishon

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  2020-11-26 12:53       ` Kishon Vijay Abraham I
@ 2020-11-30 16:12         ` Rob Herring
  0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-11-30 16:12 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: Lorenzo Pieralisi, Tero Kristo, Nishanth Menon, Tom Joseph,
	Bjorn Helgaas, linux-omap, linux-arm-kernel, devicetree, PCI,
	linux-kernel

On Thu, Nov 26, 2020 at 5:53 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Hi Rob,
>
> On 20/11/20 10:39 am, Kishon Vijay Abraham I wrote:
> > Hi Rob,
> >
> > On 19/11/20 2:41 am, Rob Herring wrote:
> >> On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
> >>> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
> >>> argument. The argument is the register offset within "syscon" used to
> >>> configure PCIe controller.
> >>>
> >>> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
> >>
> >> Link: Link: ?
> >>
> >> AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1
> >> Link would be okay though.
> >
> > Two Links was a typo, will fix it in the next revision. Nishanth as well
> > was asking about using "Link:" tag for a mailing list discussion.
> >
> > I started using it after Lorenzo had asked me to use Link tag for
> > mailing list discussion here sometime back.
> >
> > https://patchwork.kernel.org/project/linux-pci/patch/20171219083627.7904-1-kishon@ti.com/#21350261
> >
> >>
> >>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >>> ---
> >>>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
> >>>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
> >>>  2 files changed, 16 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> >>> index 3ae3e1a2d4b0..e9685c0bdc3e 100644
> >>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> >>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> >>> @@ -29,9 +29,13 @@ properties:
> >>>        - const: mem
> >>>
> >>>    ti,syscon-pcie-ctrl:
> >>> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
> >>> -                 and link speed.
> >>> -    $ref: /schemas/types.yaml#/definitions/phandle
> >>> +    allOf:
> >>
> >> You no longer need allOf here.
> >
> > hmm, don't we need it for specifying phandle with fixed cells? FWIW, I
> > was referring
> >
> > https://github.com/devicetree-org/dt-schema/blob/master/test/schemas/good-example.yaml#L187
>
> Can you clarify this please?

We are now using json-schema v2019.09 syntax which doesn't ignore
keywords in addition to a $ref as draft7 and earlier did. The old way
with 'allOf' still works though. I just haven't updated the above test
cases.

Rob

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2020-11-30 16:13 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-16 17:31 [PATCH 0/3] PCI: J721E: Fix Broken DT w.r.t SYSCON DT Kishon Vijay Abraham I
2020-11-16 17:31 ` [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Kishon Vijay Abraham I
2020-11-18 21:11   ` Rob Herring
2020-11-20  5:09     ` Kishon Vijay Abraham I
2020-11-26 12:53       ` Kishon Vijay Abraham I
2020-11-30 16:12         ` Rob Herring
2020-11-19 13:41   ` [PATCH 1/3] dt-bindings: pci: ti, j721e: Fix "ti, syscon-pcie-ctrl" " Rob Herring
2020-11-16 17:31 ` [PATCH 2/3] PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg Kishon Vijay Abraham I
2020-11-16 17:31 ` [PATCH 3/3] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl Kishon Vijay Abraham I
2020-11-18 21:14   ` Rob Herring

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