[PATCH 1/2] clk: imx: imx6ul: Move csi_sel mux to correct base register

[PATCH 1/2] clk: imx: imx6ul: Move csi_sel mux to correct base register

[Stefan Riedmueller]

The csi_sel mux register is located in the CCM register base and not the
CCM_ANALOG register base. So move it to the correct position in code.

Otherwise changing the parent of the csi clock can lead to a complete
system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely
modified.

Also remove the SET_RATE_PARENT flag since one possible supply for the
csi_sel mux is the system PLL which we don't want to modify.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 5dbb6a937732..206e4c43f68f 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -161,7 +161,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	hws[IMX6UL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
 	hws[IMX6UL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
 	hws[IMX6UL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX6UL_CLK_CSI_SEL] = imx_clk_hw_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT);
 
 	/* Do not bypass PLLs initially */
 	clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk);
@@ -270,6 +269,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	hws[IMX6UL_CLK_ECSPI_SEL]	  = imx_clk_hw_mux("ecspi_sel",	base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
 	hws[IMX6UL_CLK_LCDIF_PRE_SEL]	  = imx_clk_hw_mux_flags("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels), CLK_SET_RATE_PARENT);
 	hws[IMX6UL_CLK_LCDIF_SEL]	  = imx_clk_hw_mux("lcdif_sel",	base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
+	hws[IMX6UL_CLK_CSI_SEL]		  = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
 
 	hws[IMX6UL_CLK_LDB_DI0_DIV_SEL]  = imx_clk_hw_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
 	hws[IMX6UL_CLK_LDB_DI1_DIV_SEL]  = imx_clk_hw_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
-- 
2.25.1

[PATCH 2/2] clk: imx: imx6ul: Fix csi clk gate register

[Stefan Riedmueller]

According to the imx6ul Reference Manual the csi clk gate register is
CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the
csi clk gate which is the current setting.

Tests have shown though that the correct csi clk gate register for the
imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct
register for both platforms.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 206e4c43f68f..5dd222fab01b 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -380,7 +380,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 		hws[IMX6ULL_CLK_ESAI_IPG]	= imx_clk_hw_gate2_shared("esai_ipg",	"ahb",		base + 0x70,	0, &share_count_esai);
 		hws[IMX6ULL_CLK_ESAI_MEM]	= imx_clk_hw_gate2_shared("esai_mem",	"ahb",		base + 0x70,	0, &share_count_esai);
 	}
-	hws[IMX6UL_CLK_CSI]		= imx_clk_hw_gate2("csi",		"csi_podf",		base + 0x70,	2);
 	hws[IMX6UL_CLK_I2C1]		= imx_clk_hw_gate2("i2c1",		"perclk",	base + 0x70,	6);
 	hws[IMX6UL_CLK_I2C2]		= imx_clk_hw_gate2("i2c2",		"perclk",	base + 0x70,	8);
 	hws[IMX6UL_CLK_I2C3]		= imx_clk_hw_gate2("i2c3",		"perclk",	base + 0x70,	10);
@@ -391,6 +390,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	hws[IMX6UL_CLK_PXP]		= imx_clk_hw_gate2("pxp",		"axi",		base + 0x70,	30);
 
 	/* CCGR3 */
+	hws[IMX6UL_CLK_CSI]		= imx_clk_hw_gate2("csi",	"csi_podf",	base + 0x74,	0);
 	hws[IMX6UL_CLK_UART5_IPG]	= imx_clk_hw_gate2("uart5_ipg",	"ipg",		base + 0x74,	2);
 	hws[IMX6UL_CLK_UART5_SERIAL]	= imx_clk_hw_gate2("uart5_serial",	"uart_podf",	base + 0x74,	2);
 	if (clk_on_imx6ul()) {
-- 
2.25.1

Re: [PATCH 2/2] clk: imx: imx6ul: Fix csi clk gate register

[Fabio Estevam]

Hi Stefan,

On Thu, Aug 26, 2021 at 12:20 PM Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
>
> According to the imx6ul Reference Manual the csi clk gate register is
> CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
> Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the
> csi clk gate which is the current setting.
>
> Tests have shown though that the correct csi clk gate register for the
> imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct
> register for both platforms.
>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>

I tested the series on an imx6ull-evk with an OV5640 sensor:

Tested-by: Fabio Estevam <festevam@gmail.com>

but in my case, I did not see the problem even without your patch.

Most likely because the bootloader turned on the CSI clock.

> ---
>  drivers/clk/imx/clk-imx6ul.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index 206e4c43f68f..5dd222fab01b 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -380,7 +380,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
>                 hws[IMX6ULL_CLK_ESAI_IPG]       = imx_clk_hw_gate2_shared("esai_ipg",   "ahb",          base + 0x70,    0, &share_count_esai);
>                 hws[IMX6ULL_CLK_ESAI_MEM]       = imx_clk_hw_gate2_shared("esai_mem",   "ahb",          base + 0x70,    0, &share_count_esai);
>         }
> -       hws[IMX6UL_CLK_CSI]             = imx_clk_hw_gate2("csi",               "csi_podf",             base + 0x70,    2);
>         hws[IMX6UL_CLK_I2C1]            = imx_clk_hw_gate2("i2c1",              "perclk",       base + 0x70,    6);
>         hws[IMX6UL_CLK_I2C2]            = imx_clk_hw_gate2("i2c2",              "perclk",       base + 0x70,    8);
>         hws[IMX6UL_CLK_I2C3]            = imx_clk_hw_gate2("i2c3",              "perclk",       base + 0x70,    10);
> @@ -391,6 +390,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
>         hws[IMX6UL_CLK_PXP]             = imx_clk_hw_gate2("pxp",               "axi",          base + 0x70,    30);
>
>         /* CCGR3 */

It would be nice to put a comment here explaining the imx6ull
Reference Manual mismatch.

Maybe Abel could help to check internally at NXP?

> +       hws[IMX6UL_CLK_CSI]             = imx_clk_hw_gate2("csi",       "csi_podf",     base + 0x74,    0);

Thanks

Re: [PATCH 2/2] clk: imx: imx6ul: Fix csi clk gate register

[Stefan Riedmüller]

Hi Fabio,

On Thu, 2021-08-26 at 17:10 -0300, Fabio Estevam wrote:
> Hi Stefan,
> 
> On Thu, Aug 26, 2021 at 12:20 PM Stefan Riedmueller
> <s.riedmueller@phytec.de> wrote:
> > According to the imx6ul Reference Manual the csi clk gate register is
> > CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
> > Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the
> > csi clk gate which is the current setting.
> > 
> > Tests have shown though that the correct csi clk gate register for the
> > imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct
> > register for both platforms.
> > 
> > Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> 
> I tested the series on an imx6ull-evk with an OV5640 sensor:
> 
> Tested-by: Fabio Estevam <festevam@gmail.com>
> 
> but in my case, I did not see the problem even without your patch.
> 
> Most likely because the bootloader turned on the CSI clock.

thanks for your testing and review.

You're right, the csi clock is enabled by default and thus the issue only
arises when you try to disable the clock e.g. to save power on a connected
sensor.

> 
> > ---
> >  drivers/clk/imx/clk-imx6ul.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> > index 206e4c43f68f..5dd222fab01b 100644
> > --- a/drivers/clk/imx/clk-imx6ul.c
> > +++ b/drivers/clk/imx/clk-imx6ul.c
> > @@ -380,7 +380,6 @@ static void __init imx6ul_clocks_init(struct
> > device_node *ccm_node)
> >                 hws[IMX6ULL_CLK_ESAI_IPG]       =
> > imx_clk_hw_gate2_shared("esai_ipg",   "ahb",          base + 0x70,    0,
> > &share_count_esai);
> >                 hws[IMX6ULL_CLK_ESAI_MEM]       =
> > imx_clk_hw_gate2_shared("esai_mem",   "ahb",          base + 0x70,    0,
> > &share_count_esai);
> >         }
> > -       hws[IMX6UL_CLK_CSI]             =
> > imx_clk_hw_gate2("csi",               "csi_podf",             base +
> > 0x70,    2);
> >         hws[IMX6UL_CLK_I2C1]            =
> > imx_clk_hw_gate2("i2c1",              "perclk",       base + 0x70,    6);
> >         hws[IMX6UL_CLK_I2C2]            =
> > imx_clk_hw_gate2("i2c2",              "perclk",       base + 0x70,    8);
> >         hws[IMX6UL_CLK_I2C3]            =
> > imx_clk_hw_gate2("i2c3",              "perclk",       base + 0x70,    10);
> > @@ -391,6 +390,7 @@ static void __init imx6ul_clocks_init(struct
> > device_node *ccm_node)
> >         hws[IMX6UL_CLK_PXP]             =
> > imx_clk_hw_gate2("pxp",               "axi",          base + 0x70,    30);
> > 
> >         /* CCGR3 */
> 
> It would be nice to put a comment here explaining the imx6ull
> Reference Manual mismatch.

Sure I will prepare something.

> 
> Maybe Abel could help to check internally at NXP?

Yes, that would be nice!

Regards,
Stefan

> 
> > +       hws[IMX6UL_CLK_CSI]             =
> > imx_clk_hw_gate2("csi",       "csi_podf",     base + 0x74,    0);
> 
> Thanks