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Received: from [193.209.96.43] (helo=[10.21.26.144]) by mail.kapsi.fi with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1fiE0c-0004In-Md; Wed, 25 Jul 2018 10:14:54 +0300 Subject: Re: [PATCH 04/10] mmc: tegra: Disable card clock during pad calibration To: Aapo Vienamo , Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <1532442591-5640-1-git-send-email-avienamo@nvidia.com> <1532442865-6391-1-git-send-email-avienamo@nvidia.com> <1532442865-6391-3-git-send-email-avienamo@nvidia.com> From: Mikko Perttunen Message-ID: <1f70fd07-f952-63c9-8727-e6dacf52da73@kapsi.fi> Date: Wed, 25 Jul 2018 10:14:54 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <1532442865-6391-3-git-send-email-avienamo@nvidia.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 193.209.96.43 X-SA-Exim-Mail-From: cyndis@kapsi.fi X-SA-Exim-Scanned: No (on mail.kapsi.fi); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24.07.2018 17:34, Aapo Vienamo wrote: > Disable the card clock during automatic pad drive strength calibration > and re-enable it aftewards. s/aftewards/afterwards/. > > Signed-off-by: Aapo Vienamo > --- > drivers/mmc/host/sdhci-tegra.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 61067b7..0de74f4 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -52,6 +52,7 @@ > #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 > #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f > #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 > +#define SDHCI_TEGRA_PAD_E_INPUT_OR_E_PWRD BIT(31) Looks like this should be in the previous patch. > > #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec > #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) > @@ -226,11 +227,35 @@ static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) > udelay(1); > } > > +static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) > +{ > + bool orig_enabled; > + u32 reg; > + > + reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > + orig_enabled = reg & SDHCI_CLOCK_CARD_EN; I would do !!(reg & SDHCI_CLOCK_CARD_EN) here. > + > + if (orig_enabled == enable) > + return orig_enabled; > + > + if (enable) > + reg |= SDHCI_CLOCK_CARD_EN; > + else > + reg &= ~SDHCI_CLOCK_CARD_EN; > + > + sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); > + > + return orig_enabled; > +} > + > static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) > { > unsigned timeout = 10; > + bool card_clk_enabled; > u32 reg; > > + card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); > + > tegra_sdhci_configure_cal_pad(host, true); > > reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); > @@ -248,6 +273,8 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) > > tegra_sdhci_configure_cal_pad(host, false); > > + tegra_sdhci_configure_card_clk(host, card_clk_enabled); > + > if (timeout == 0) > dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); > } >