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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id q3-20020a1ce903000000b003a61306d79dsm8616834wmc.41.2022.08.29.02.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 02:45:26 -0700 (PDT) References: <20220805085716.5635-1-yu.tu@amlogic.com> <20220805085716.5635-3-yu.tu@amlogic.com> <19654574-bdc0-9fa5-6465-fc88b20e20c5@linaro.org> <1jmtccz0f4.fsf@starbuckisacylon.baylibre.com> User-agent: mu4e 1.8.7; emacs 28.1 From: Jerome Brunet To: Yu Tu , Krzysztof Kozlowski , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Neil Armstrong , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl Subject: Re: [PATCH V3 2/6] arm64: dts: meson: add S4 Soc PLL clock controller in DT Date: Mon, 29 Aug 2022 11:43:43 +0200 In-reply-to: Message-ID: <1j1qszv0wa.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon 15 Aug 2022 at 14:17, Yu Tu wrote: > Hi Jerome=EF=BC=8C > > On 2022/8/10 21:32, Jerome Brunet wrote: >> [ EXTERNAL EMAIL ] >> On Fri 05 Aug 2022 at 17:39, Yu Tu wrote: >>=20 >>> Hi Krzysztof, >>> Thank you for your reply. >>> >>> On 2022/8/5 17:16, Krzysztof Kozlowski wrote: >>>> [ EXTERNAL EMAIL ] >>>> On 05/08/2022 10:57, Yu Tu wrote: >>>>> Added information about the S4 SOC PLL Clock controller in DT. >>>>> >>>>> Signed-off-by: Yu Tu >>>>> --- >>>>> arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 8 ++++++++ >>>>> 1 file changed, 8 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/b= oot/dts/amlogic/meson-s4.dtsi >>>>> index ff213618a598..a816b1f7694b 100644 >>>>> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi >>>>> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi >>>>> @@ -92,6 +92,14 @@ apb4: apb4@fe000000 { >>>>> #size-cells =3D <2>; >>>>> ranges =3D <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; >>>>> + clkc_pll: pll-clock-controller@8000 { >>>> Node names should be generic - clock-controller. >>>> https://devicetree-specification.readthedocs.io/en/latest/chapter2-dev= icetree-basics.html#generic-names-recommendation >>>> >>> I will change to clkc_pll: clock-controller@8000, in next version. >> Same comment applies to the binding doc. > OKay. >> Also it would be nice to split this in two series. >> Bindings and drivers in one, arm64 dt in the other. These changes goes >> in through different trees. > At present, Bindings, DTS and drivers are three series. Do you mean to put > Bindings and drivers together? If so, checkpatch.pl will report a warning. Yes because patches are not in yet so there is a good reason to ignore the warning. Warning will never show up on the actual tree if the patches are correctly ordered. > >>=20 >>>> Best regards, >>>> Krzysztof >>>> . >> .