From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBF94C4167B for ; Fri, 4 Dec 2020 14:25:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8BC7422B3F for ; Fri, 4 Dec 2020 14:25:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726998AbgLDOY6 (ORCPT ); Fri, 4 Dec 2020 09:24:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725920AbgLDOY6 (ORCPT ); Fri, 4 Dec 2020 09:24:58 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 381C3C061A4F for ; Fri, 4 Dec 2020 06:24:12 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id e7so5494331wrv.6 for ; Fri, 04 Dec 2020 06:24:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=references:user-agent:from:to:cc:subject:in-reply-to:message-id :date:mime-version; bh=jUrLTNYFEiHdTQnh4b2KYj9Mt2pIKbyV0FmvqdxpeB8=; b=Z6DkyOnE9k1kWZpvptHeGrpAXBwSapeSB8w1YdvYbnb3eftmlK2wjdSjdpN7qCOj2+ nn+uYpuGAK4xmpf1bBewVR90Ik16AG7aoY0iQEv6cw7rLmLB8GXJK4KKVyk5XMUXcfk0 EDMMpV3uJc4m6t/gnwI3sy2t4d250gGHLxpLlwGXbaZhswUraVRt94C2BMMcjp3HX10m zEQCPyhxIq0cXuBLHXrkZwPXLwpT4yin9SfAh1QeSDSJL9XPv//Px0NZy4CjDLc+UxI5 FQ+q0ZObcEIkv6JwodNHpm4IsjoWTxyMo1vL+Sg/7A6qI2A95DQjYkyf/sWjUp3flODt PKEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:message-id:date:mime-version; bh=jUrLTNYFEiHdTQnh4b2KYj9Mt2pIKbyV0FmvqdxpeB8=; b=iMYnRQFBneUNld9LCL3r1kEANYZsgCKMEbp0uvIuYnkDqya8eFYBVbGqgFplgqWmU8 a0jQz9yv8/A/hreHIfmdERdyv8bzqer/7DTLJKm27ddAYmz6y40QOke8miyT9KBe14tF S99iBsVDLn+EaJkVoNc/SsEKc6nnMn2u0MJMzn0e4n6HnG5V3CoTHF0SDmt/7QyE5SrO JMUUlOJhlcsYLc9YcfCl90xd/HZufo2xe/HvU9Whj14/LXrmbXJCub+ON3ZvtHto4Fhb WWzoP6qLZCWZ7DkAOS/ZxqrTGmkCXYcDqLjgYFwUzyzua0mLHE2flKRnSOyPkBb4NcNy FUrw== X-Gm-Message-State: AOAM530i/gt8cBvvus7u2eFJUpLquQHrfaq65fHmF/RhY2MDgVbLo14V 1y6e5Z4HNme2M7IgUCeWDUwWaA== X-Google-Smtp-Source: ABdhPJwoBA9wqffJQYc31bYbuyvOWnHNUoeQXULAdRVuAJOkUsOmNY8LZXa33e0UvMqyOWL8CHF4zQ== X-Received: by 2002:a05:6000:89:: with SMTP id m9mr5285264wrx.412.1607091850901; Fri, 04 Dec 2020 06:24:10 -0800 (PST) Received: from localhost (82-65-169-74.subs.proxad.net. [82.65.169.74]) by smtp.gmail.com with ESMTPSA id j8sm3868701wrx.11.2020.12.04.06.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Dec 2020 06:24:10 -0800 (PST) References: User-agent: mu4e 1.4.10; emacs 27.1 From: Jerome Brunet To: Linus Walleij , =?utf-8?B?5p6X5Zyj5qyi?= Cc: khilman , narmstrong , "martin.blumenstingl" , linux-gpio , linux-arm-kernel , linux-amlogic , linux-kernel Subject: Re: 0001-add-amlogic-gpio-to-irq In-reply-to: Message-ID: <1jeek5ps3b.fsf@starbuckisacylon.baylibre.com> Date: Fri, 04 Dec 2020 15:24:09 +0100 MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 04 Dec 2020 at 10:13, Linus Walleij wrote: > Hi Lisheng, > > this patch got a bit mangled but I get where you're going. > > I think Meson needs to be augmented to use hierarchical gpiolib irqchip > because this seems to be what the system is doing. > > So start with drivers/pinctrl/meson/Kconfig and add: > > select GPIOLIB_IRQCHIP > select IRQ_DOMAIN_HIEARARCHY > > Then use the generic hierarchical gpiolib irqchip as described > in Documentation/driver-api/gpio/driver.rst > Type > git grep child_to_parent_hwirq > for several examples of how to do this. One reason the irqchip has not been linked to the gpio controller so far is IRQ_EDGE_BOTH which the irqchip does not support (expect for the latest sm1 family) This is a problem we discussed a couple of years ago. This HW only has 8 irqs that can each be mapped to a pin. No direct translation can be made, we have to allocate an irq to monitor the line. So when gpio_to_irq() was called, we had to do that allocation dynamically to return a valid irq number. Since there was no counter part to gpio_to_irq(), those allocation cannot be freed during the lifetime of the device. When drivers relying IRQ_EDGE_BOTH first try the `gpio_to_irq()`, allocating the irq works but setting the type does not. We are then left with unused allocated irqs (and we don't have much) Frameworks using gpio_to_irq() are often capable() of parsing interrupt properties directly too. So far, it was enough to work around the problem. I admit, I have not been following gpiolib closely since then, maybe some progress have been made > > Yours, > Linus Walleij