From: Jerome Brunet <jbrunet@baylibre.com>
To: Neil Armstrong <narmstrong@baylibre.com>, khilman@baylibre.com
Cc: Neil Armstrong <narmstrong@baylibre.com>,
linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/6] arm64: meson-sm1: add support for DVFS
Date: Fri, 23 Aug 2019 18:10:01 +0200 [thread overview]
Message-ID: <1jlfvjeucm.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20190822142455.12506-1-narmstrong@baylibre.com>
On Thu 22 Aug 2019 at 16:24, Neil Armstrong <narmstrong@baylibre.com> wrote:
> Following DVFS support for the Amlogic G12A and G12B SoCs, this serie
> enables DVFS on the SM1 SoC for the SEI610 board.
>
> The SM1 Clock structure is slightly different because of the Cortex-A55
> core used, having the capability for each core of a same cluster to run
> at a different frequency thanks to the newly used DynamIQ Shared Unit.
>
> This is why SM1 has a CPU clock tree for each core and for DynamIQ Shared Unit,
> with a bypass mux to use the CPU0 instead of the dedicated trees.
>
> The DSU uses a new GP1 PLL as default clock, thus GP1 is added as read-only.
>
> The SM1 OPPs has been taken from the Amlogic Vendor tree, and unlike
> G12A only a single version of the SoC is available.
>
> Dependencies:
> - patch 6 is based on the "arm64: meson: add support for SM1 Power Domains" serie,
> but is not a strong dependency, it will work without
>
> Neil Armstrong (6):
> dt-bindings: clk: meson: add sm1 periph clock controller bindings
> clk: meson: g12a: add support for SM1 GP1 PLL
> clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
> clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
> clk: meson: g12a: expose SM1 CPU 1, 2 & 3 clocks
> arm64: dts: meson-sm1-sei610: enable DVFS
>
> .../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
> .../boot/dts/amlogic/meson-sm1-sei610.dts | 59 +-
> arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 69 +++
> drivers/clk/meson/g12a.c | 544 ++++++++++++++++++
> drivers/clk/meson/g12a.h | 26 +-
> include/dt-bindings/clock/g12a-clkc.h | 3 +
> 6 files changed, 697 insertions(+), 5 deletions(-)
Series looks good to me overall.
Just drop patch 5 and expose every ID necessary directly with patch 1
(same goes for the GP1 clock ID)
>
> --
> 2.22.0
prev parent reply other threads:[~2019-08-23 16:10 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-22 14:24 [PATCH 0/6] arm64: meson-sm1: add support for DVFS Neil Armstrong
2019-08-22 14:24 ` [PATCH 1/6] dt-bindings: clk: meson: add sm1 periph clock controller bindings Neil Armstrong
2019-08-22 20:49 ` Kevin Hilman
2019-08-22 14:24 ` [PATCH 2/6] clk: meson: g12a: add support for SM1 GP1 PLL Neil Armstrong
2019-08-22 14:24 ` [PATCH 3/6] clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock Neil Armstrong
2019-08-22 14:24 ` [PATCH 4/6] clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks Neil Armstrong
2019-08-22 14:24 ` [PATCH 5/6] clk: meson: g12a: expose " Neil Armstrong
2019-08-22 14:24 ` [PATCH 6/6] arm64: dts: meson-sm1-sei610: enable DVFS Neil Armstrong
2019-08-22 20:49 ` Kevin Hilman
2019-08-23 16:10 ` Jerome Brunet [this message]
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