From: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
Neil Armstrong <narmstrong@baylibre.com>,
linux-clk@vger.kernel.org, khilman@baylibre.com,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFC v1 1/3] clk: divider: Add re-usable determine_rate implementations
Date: Wed, 19 May 2021 14:31:41 +0200 [thread overview]
Message-ID: <1jv97eaor6.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <CAFBinCB+5bFH0LW4rqYGCiO-X-xmer67cp5kXpyU0d-OfxiOvw@mail.gmail.com>
On Tue 18 May 2021 at 22:33, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> Hi Jerome,
>
> On Tue, May 18, 2021 at 9:44 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
> [...]
>> > +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
>> > + const struct clk_div_table *table, u8 width,
>> > + unsigned long flags, unsigned int val)
>> > +{
>> > + int div;
>> > +
>> > + div = _get_div(table, val, flags, width);
>> > +
>> > + /* Even a read-only clock can propagate a rate change */
>> > + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
>> > + if (!req->best_parent_hw)
>> > + return -EINVAL;
>> > +
>> > + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,
>> > + req->rate * div);
>> > + }
>> > +
>> > + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
>> > +
>> > + return 0;
>> > +}
>> > +EXPORT_SYMBOL_GPL(divider_ro_determine_rate);
>>
>> For a final version, could you factorize the code with the .round_rate()
>> variant ? It would remove a bit of duplication.
> my first idea was to basically let the new _determine_rate code just
> forward all relevant parameters to _round_rate
> however, I discarded that as it turned out to be less understandable
> for me as parameters need to be mapped in both ways
>
> while writing this mail I noticed that the opposite direction
> (meaning: _round_rate forwards to _determine_rate) will probably work.
> I'll give it a try in the next days
> if you had anything else in mind then please let me know
Yep, the idea would be to use the determine_rate() part as the common
implementation. AFAICT, all you need is to build req_rate structure in
the round_rate() part.
>
>> Maybe determine_rate() can also replace round_rate() in the generic
>> divider ops ?
> sure, I'll add that as a separate patch in this series
> note to myself: testing can be done with the MMC drivers as we're
> using the generic clk_divider_ops there
>
>
> Best regards,
> Martin
next prev parent reply other threads:[~2021-05-19 12:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 20:37 [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Martin Blumenstingl
2021-05-17 20:37 ` [PATCH RFC v1 1/3] clk: divider: Add re-usable determine_rate implementations Martin Blumenstingl
2021-05-18 7:44 ` Jerome Brunet
2021-05-18 20:33 ` Martin Blumenstingl
2021-05-19 12:31 ` Jerome Brunet [this message]
2021-05-17 20:37 ` [PATCH RFC v1 2/3] clk: meson: regmap: switch to determine_rate for the dividers Martin Blumenstingl
2021-05-18 7:47 ` Jerome Brunet
2021-05-17 20:37 ` [PATCH RFC v1 3/3] clk: meson: pll: switch to determine_rate for the PLL ops Martin Blumenstingl
2021-05-18 7:50 ` Jerome Brunet
2021-05-18 20:17 ` Martin Blumenstingl
2021-05-19 15:10 ` Jerome Brunet
2021-05-18 7:37 ` [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Jerome Brunet
2021-05-18 20:20 ` Martin Blumenstingl
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