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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id m13-20020a05600c3b0d00b003a83b066401sm10964211wms.31.2022.08.29.23.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 23:39:05 -0700 (PDT) References: <20220805085716.5635-1-yu.tu@amlogic.com> <20220805085716.5635-3-yu.tu@amlogic.com> <19654574-bdc0-9fa5-6465-fc88b20e20c5@linaro.org> <1jmtccz0f4.fsf@starbuckisacylon.baylibre.com> <1j1qszv0wa.fsf@starbuckisacylon.baylibre.com> <72631035-58a6-23b5-1f7e-f1643b120432@amlogic.com> User-agent: mu4e 1.8.7; emacs 28.1 From: Jerome Brunet To: Yu Tu , Krzysztof Kozlowski , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Neil Armstrong , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl Subject: Re: [PATCH V3 2/6] arm64: dts: meson: add S4 Soc PLL clock controller in DT Date: Tue, 30 Aug 2022 08:36:00 +0200 In-reply-to: <72631035-58a6-23b5-1f7e-f1643b120432@amlogic.com> Message-ID: <1jy1v6z14n.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 30 Aug 2022 at 14:05, Yu Tu wrote: > On 2022/8/29 17:43, Jerome Brunet wrote: >> [ EXTERNAL EMAIL ] >> On Mon 15 Aug 2022 at 14:17, Yu Tu wrote: >>=20 >>> Hi Jerome=EF=BC=8C >>> >>> On 2022/8/10 21:32, Jerome Brunet wrote: >>>> [ EXTERNAL EMAIL ] >>>> On Fri 05 Aug 2022 at 17:39, Yu Tu wrote: >>>> >>>>> Hi Krzysztof, >>>>> Thank you for your reply. >>>>> >>>>> On 2022/8/5 17:16, Krzysztof Kozlowski wrote: >>>>>> [ EXTERNAL EMAIL ] >>>>>> On 05/08/2022 10:57, Yu Tu wrote: >>>>>>> Added information about the S4 SOC PLL Clock controller in DT. >>>>>>> >>>>>>> Signed-off-by: Yu Tu >>>>>>> --- >>>>>>> arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 8 ++++++++ >>>>>>> 1 file changed, 8 insertions(+) >>>>>>> >>>>>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64= /boot/dts/amlogic/meson-s4.dtsi >>>>>>> index ff213618a598..a816b1f7694b 100644 >>>>>>> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi >>>>>>> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi >>>>>>> @@ -92,6 +92,14 @@ apb4: apb4@fe000000 { >>>>>>> #size-cells =3D <2>; >>>>>>> ranges =3D <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; >>>>>>> + clkc_pll: pll-clock-controller@8000 { >>>>>> Node names should be generic - clock-controller. >>>>>> https://devicetree-specification.readthedocs.io/en/latest/chapter2-d= evicetree-basics.html#generic-names-recommendation >>>>>> >>>>> I will change to clkc_pll: clock-controller@8000, in next version. >>>> Same comment applies to the binding doc. >>> OKay. >>>> Also it would be nice to split this in two series. >>>> Bindings and drivers in one, arm64 dt in the other. These changes goes >>>> in through different trees. >>> At present, Bindings, DTS and drivers are three series. Do you mean to = put >>> Bindings and drivers together? If so, checkpatch.pl will report a warni= ng. >> Yes because patches are not in yet so there is a good reason to ignore >> the warning. Warning will never show up on the actual tree if the >> patches are correctly ordered. > > I think Binding, DTS and drivers use three series and you said two series > is not a big problem. Three series are recommended for checkpatch.pl, I > think it should be easy for that to separate and merge=E3=80=82 No - There is only 2 series. 1 for the bindings and clock drivers and one for the DT once things are in > > I've sent it to V4. Please look at V4 and give some comments. > That's not how it works. You sent that before v3 review was done. There are still comments that needed to be addressed Given the time it takes to make that review I going to completly skip v4 and I'd like on the comment to addressed before you send another version >>=20 >>> >>>> >>>>>> Best regards, >>>>>> Krzysztof >>>>>> . >>>> . >> .