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Date: Wed, 18 Sep 2002 13:23:34 -0700 (PDT)
Message-Id: <20020918.132334.102949210.davem@redhat.com>
To: ebiederm@xmission.com
Cc: hadi@cyberus.ca, akpm@digeo.com, manfred@colorfullife.com,
       netdev@oss.sgi.com, linux-kernel@vger.kernel.org
Subject: Re: Info: NAPI performance at "low" loads
From: "David S. Miller" <davem@redhat.com>
In-Reply-To: <m1hegnky2h.fsf@frodo.biederman.org>
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	<20020917.180014.07882539.davem@redhat.com>
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   From: ebiederm@xmission.com (Eric W. Biederman)
   Date: 18 Sep 2002 11:27:34 -0600

   "David S. Miller" <davem@redhat.com> writes:
   
   > {in,out}{b,w,l}() operations have a fixed timing, therefore his
   > results doesn't sound that far off.
   ????
   
   I don't see why they should be.  If it is a pci device the cost should
   the same as a pci memory I/O.  The bus packets are the same.  So things like
   increasing the pci bus speed should make it take less time.

The x86 processor has a well defined timing for executing inb
etc. instructions, the timing is fixed and is independant of the
speed of the PCI bus the device is on.