From: Chuck Ebbert <76306.1226@compuserve.com>
To: linux-kernel <linux-kernel@vger.kernel.org>
Subject: x86 IO-APIC and IRQ questions
Date: Thu, 17 Apr 2003 19:50:03 -0400 [thread overview]
Message-ID: <200304171954_MC3-1-34E7-5FFD@compuserve.com> (raw)
Why doesn't the timer IRQ have a higher priority on x86 IOAPIC
machines? Mine has interrupt vector 0x31, which is priority 3.
Shouldn't it be more like 0xe or 0xf?
And why are the IRQ entry points (in 2.4.20) not 16-byte aligned?
Up until IRQ0x0b everything is OK because the actual stubs are only
7+1 bytes long, but after that the jmp instruction needs a 32-bit
offset and they are 10+2 bytes. This puts IRQ #15 and #19 four
bytes from the end of a 16-byte cache line, and their first
instructions are 5 bytes long.
--
Chuck
next reply other threads:[~2003-04-17 23:42 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-04-17 23:50 Chuck Ebbert [this message]
2003-04-18 3:03 x86 IO-APIC and IRQ questions Chuck Ebbert
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