Re: x86 IO-APIC and IRQ questions

Re: x86 IO-APIC and IRQ questions

[Chuck Ebbert]

Chuck Ebbert wrote:


>  And why are the IRQ entry points (in 2.4.20) not 16-byte aligned?
> Up until IRQ0x0b everything is OK because the actual stubs are only
> 7+1 bytes long, but after that the jmp instruction needs a 32-bit
> offset and they are 10+2 bytes.  This puts IRQ #15 and #19 four
> bytes from the end of a 16-byte cache line, and their first
> instructions are 5 bytes long.


 This should help:


--- linux-2.4.20aa1/arch/i386/kernel/i8259.c	Tue Sep 18 02:03:09 2001
+++ linux-2.4.20irq/arch/i386/kernel/i8259.c	Thu Apr 17 22:22:12 2003
@ -35,8 +35,6 @
  * interrupt-controller happy.
  */
 
-BUILD_COMMON_IRQ()
-
 #define BI(x,y) \
 	BUILD_IRQ(x##y)
 
@ -52,6 +50,8 @
  */
 BUILD_16_IRQS(0x0)
 
+BUILD_COMMON_IRQ()
+
 #ifdef CONFIG_X86_IO_APIC
 /*
  * The IO-APIC gives us many more interrupt sources. Most of these 


--
 Chuck

x86 IO-APIC and IRQ questions

[Chuck Ebbert]

 Why doesn't the timer IRQ have a higher priority on x86 IOAPIC
machines? Mine has interrupt vector 0x31, which is priority 3.
Shouldn't it be more like 0xe or 0xf?

 And why are the IRQ entry points (in 2.4.20) not 16-byte aligned?
Up until IRQ0x0b everything is OK because the actual stubs are only
7+1 bytes long, but after that the jmp instruction needs a 32-bit
offset and they are 10+2 bytes.  This puts IRQ #15 and #19 four
bytes from the end of a 16-byte cache line, and their first
instructions are 5 bytes long.


--
 Chuck