From: joe briggs <jbriggs@briggsmedia.com>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: David Brodbeck <DavidB@mail.interclean.com>,
"'motion@lists.frogtown.com'" <motion@pdx.frogtown.com>,
andras@t-online.de,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
motion@frogtown.com
Subject: Re: [Motion] Re: IDE corruption during heavy bt878-induced interr upt load [LKM]
Date: Thu, 24 Apr 2003 06:31:49 -0400 [thread overview]
Message-ID: <200304240631.49222.jbriggs@briggsmedia.com> (raw)
In-Reply-To: <1051135875.2062.101.camel@dhcp22.swansea.linux.org.uk>
That's what I thought, which is why I suspected that the underlying problem
might be related to the scope and completeness of the hardware arbitration.
Specifically, if a PCI board is DMA'ing a block of data to main memory, how
is the operation of the direct-connect IDE device impacted? When most PCI
devices transfer data to main memory, don't they arbitrate the bus, become
master, and blast it accross in chunks? Doesn't onboard IDE (legacy?) use
the DMA controller (8237 derivate I gues) to transfer?
On Wednesday 23 April 2003 06:11 pm, Alan Cox wrote:
> On Mer, 2003-04-23 at 23:13, joe briggs wrote:
> > Is this true??? Does onboard IDE controllers appear and work the same way
> > as IDE or PCI controllers with respect to IRQ, DMA, and memory access?
>
> They appear to. Most of them nowdays are wired directly to the
> north/southbridge link for performance.
>
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--
Joe Briggs
Briggs Media Systems
105 Burnsen Ave.
Manchester NH 01304 USA
TEL/FAX 603-232-3115 MOBILE 603-493-2386
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next prev parent reply other threads:[~2003-04-24 9:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-04-23 19:22 [Motion] Re: IDE corruption during heavy bt878-induced interr upt load [LKM] David Brodbeck
2003-04-23 22:13 ` joe briggs
2003-04-23 22:11 ` Alan Cox
2003-04-24 10:31 ` joe briggs [this message]
2003-04-24 18:57 ` Alan Cox
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